Abstract: A replacement gate process for fabricating a semiconductor device with metal gates includes forming a dummy gate stack, patterning dummy gates, doping source and drain regions for the gates, and forming an inter-level dielectric layer that overlays the source and drain regions. The sacrificial layer of the dummy gates is removed to form trenches using a three stage process. The first stage begins the trenches, whereby trenches entrance corners are exposed. The second stage is an etch that rounds the corners. The third stage is a main etch for the sacrificial layer, which is typically polysilicon. The corner rounding of the second stage improves the performance of the third stage and results in a better metal back fill including a reduction in pit defects. The process improves overall device yield in comparison to an otherwise equivalent process that omits the corner rounding step.

Abstract: A method for forming a semiconductor device such as a MOSFET. The method includes forming gate electrode pillars on a silicon substrate via material deposition and etching. Following the etching step to define the pillars, an epitaxial silicon film is grown on the substrate between the pillars prior to forming recesses in the substrate for the source/drain regions of the transistor. The epitaxial silicon film compensates for substrate material that may be lost during formation of the gate electrode pillars, thereby producing source/drain recesses having a configuration amenable to be filled uniformly with silicon for later forming the source/drain regions in the substrate.

Abstract: Circuits and systems comprising one or more switches are provided. A circuit includes a first switch formed on a substrate; and a second switch formed on the substrate, the second switch including a first terminal coupled to a third terminal of the first switch. A system includes a supply; a first switch formed on a substrate, the first switch coupled to the supply; a second switch formed on the substrate, the second switch coupled to the first switch; a third switch formed on the substrate, the third switch coupled to the supply; a fourth switch formed on the substrate, the fourth switch coupled to the third switch; and a driver coupled to respective second terminals of the first, second, third, and fourth switches.

Abstract: A solid-state imaging device that includes a pixel including a photoelectric conversion section, and a conversion section that converts an electric charge generated by photoelectric conversion into a pixel signal. In the solid-state imaging device, substantially only a gate insulation film is formed on a substrate corresponding to an area under a gate electrode of at least one transistor in the pixel.

Abstract: A fabricating method of a semiconductor element includes the following steps. First, a substrate is provided. A metal gate structure and source/drain electrodes are already formed on the substrate. An amorphization process is performed in the source/drain electrodes to form an amorphous portion. An interlayer dielectric layer is formed on surfaces of the source/drain electrodes and a through hole contact is formed within the interlayer dielectric layer. A silicidation process is performed with the through hole contact and the amorphous portion of the source/drain electrodes to form a metal silicide layer. The fabricating method is capable of finishing the formation of the metal silicide layer in the condition that diameters of the through hole contact is becoming smaller and smaller.

Abstract: Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.

Abstract: A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.

Abstract: A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.

Abstract: A Vertical Power MOSFET (VDMOS) device with special features that enable the Power MOSFET or IGBT device to withstand harsh radiation environments and the process of making such a device is described. All implanted and diffused layers are “self aligned” to a “Sacrificial Poly” layer, which later on is removed, preparing the wafers for a “late gate” oxide to be grown. A starting material with graded doping profile in the epitaxial layer on the substrate is shown to increase the SEB capability of the Power MOSFET.

Abstract: A method includes forming a gate stack over a semiconductor substrate, wherein the gate stack includes a gate dielectric and a gate electrode over the gate dielectric. A portion of the semiconductor substrate adjacent to the gate stack is recessed to form a recess. A semiconductor region is epitaxially grown in the recess. The semiconductor region is implanted with a p-type impurity or an n-type impurity. A dry treatment is performed on the semiconductor region.

Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.

Abstract: A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.

Abstract: A method for manufacturing a semiconductor device includes forming a first gate electrode on a semiconductor substrate in a first transistor region; forming a channel dose region; and forming a first source extension region, wherein the channel dose region is formed by using a first mask as a mask and by ion-implanting a first dopant of the first conductivity type, and the first mask covering a drain side of the first gate electrode and covering a drain region, and the first source extension region is formed by using a second mask and the gate electrode as masks and by ion-implanting a second dopant of a second conductivity type that is a conductivity type opposite to the first conductivity type, the second mask covering the drain side of the first gate electrode and covering the drain region.

Abstract: The present invention provides a method and apparatus for manufacturing a semiconductor device using a PVD method and enabling achievement of a desired effective work function and reduction in leak current without increasing an equivalent oxide thickness. A method for manufacturing a semiconductor device in an embodiment of the present invention includes the steps of: preparing a substrate on which an insulating film having a relative permittivity higher than that of a silicon oxide film is formed; and depositing a metal nitride film on the insulating film. The metal nitride depositing step is a step of sputtering deposition in an evacuatable chamber using a metal target and a cusp magnetic field formed over a surface of the metal target by a magnet mechanism in which magnet pieces are arranged as grid points in such a grid form that the adjacent magnet pieces have their polarities reversed from each other.

Abstract: The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability.

Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Abstract: A method for designing a stressor pattern is described, wherein the stressor pattern is used to form S/D regions of a second-type MOS transistor. A first distance between a boundary of the stressor pattern and a first active area of a first-type MOS transistor is derived. If the first distance is less than a safe distance, the stressor pattern is shrunk to make the first distance at least equal to the safe distance.

Abstract: A mask ROM fabrication method which comprises steps: sequentially forming a gate dielectric layer and a first photoresist layer on a substrate; letting a light having a wavelength of 365 nm pass through a first phase shift mask to photolithographically form on the first photoresist layer a plurality of first trenches having a width of 243-365 nm; doping the substrate to form a plurality of embedded bit lines having a width of 243-365 nm; removing the first photoresist layer; sequentially forming a polysilicon layer and a second photoresist layer on the gate dielectric layer; and letting the light pass through a second phase shift mask to photolithographically form a plurality of polysilicon word lines on the polysilicon layer. Thereby is reduced the line width of mask ROM to 243-365 nm and decreased the area of mask ROM.

Abstract: The present invention provides a power transistor device with a super junction including a substrate, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The first epitaxial layer is disposed on the substrate, and has a plurality of trenches. The trenches are filled up with the second epitaxial layer, and a top surface of the second epitaxial layer is higher than a top surface of the first epitaxial layer. The second epitaxial layer has a plurality of through holes penetrating through the second epitaxial layer and disposed on the first epitaxial layer. The second epitaxial layer and the first epitaxial layer have different conductivity types. The through holes are filled up with the third epitaxial layer, and the third epitaxial layer is in contact with the first epitaxial layer. The third epitaxial layer and the first epitaxial layer have the same conductivity type.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.

Abstract: In one exemplary embodiment of the invention, a method (e.g., to fabricate a semiconductor device having a borderless contact) including: forming a first gate structure on a substrate; depositing an interlevel dielectric over the first gate structure; planarizing the interlevel dielectric to expose a top surface of the first gate structure; removing at least a portion of the first gate structure; forming a second gate structure in place of the first gate structure; forming a contact area for the borderless contact by removing a portion of the interlevel dielectric; and forming the borderless contact by filling the contact area with a metal-containing material.

Abstract: The present invention relates to CMOS ultra large scale integrated circuits, and provides a method for introducing channel stress and a field effect transistor fabricated by the same. According to the present invention, a strained dielectric layer is interposed between source/drain regions and a substrate of a field effect transistor, and a strain is induced in a channel by the strained dielectric layer which directly contacts the substrate, so as to improve a carrier mobility of the channel and a performance of the device. The specific effects of the invention include: a tensile strain may be induced in the channel by using the strained dielectric layer having a tensile strain in order to increase an electron mobility of the channel; a compressive strain may be induced in the channel by using the strained dielectric layer having a compressive strain in order to increase a hole mobility of the channel.

Abstract: The present invention relates to memory devices incorporating therein a novel memory cell architecture which includes an array of selection transistors sharing a common channel and method for making the same. A memory device comprises a semiconductor substrate having a first type conductivity, a plurality of drain regions and a common source region separated by a common plate channel in the substrate, and a selection gate disposed on top of the plate channel with a gate dielectric layer interposed therebetween. The plurality of drain regions and the common source region have a second type conductivity opposite to the first type provided in the substrate.

Abstract: The present invention provides a floating-gate non-volatile semiconductor memory device and a method of making the same. The floating-gate non-volatile semiconductor memory device comprises a semiconductor substrate, a source, a drain, a first insulator layer, a first polysilicon layer, a second insulator layer, a second polysilicon layer, a protective layer and sidewalls. The source and drain are disposed on the semiconductor substrate. The first insulator layer is disposed over a region of the semiconductor substrate other than regions corresponding to the source and drain. The first polysilicon layer is disposed over the first insulator layer, forming a floating gate. The second insulator layer is disposed over the first polysilicon layer. The second polysilicon layer is disposed over the second insulator layer, forming a control gate and a wordline. The sidewalls are disposed on two sides of the wordline, and the protective layer is disposed over the second polysilicon layer.

Abstract: A method for forming a field effect transistor device includes forming a nanowire suspended above a substrate, forming a dummy gate stack on a portion of the substrate and around a portion of the nanowire, removing exposed portions of the nanowire, epitaxially growing nanowire extension portions from exposed portions of the nanowire, depositing a layer of semiconductor material over exposed portions of the substrate, the dummy gate stack and the nanowire extension portions, and removing portions of the semiconductor material to form sidewall contact regions arranged adjacent to the dummy gate stack and contacting the nanowire extension portions.

Abstract: The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.

Abstract: A MOS transistor includes a pair of impurity regions formed in a substrate as spaced apart from each other, and a gate electrode formed on a region of the substrate located between the pair of impurity regions. Each of the impurity regions is formed of a first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The first epitaxial layer is formed of at least one first sub-epitaxial layer and a respective second sub-epitaxial layer stacked on each first sub-epitaxial layer. An impurity concentration of the first sub-epitaxial layer is less than that of the second sub-epitaxial layer.

Abstract: A three-dimensional (3-D) nonvolatile memory device includes a channel layer protruded from a substrate, a plurality of memory cells stacked along the channel layer, a source line coupled to the end of one side of the channel layer, a bit line coupled to the end of the other side of the channel layer, a first junction interposed between the end of one side of the channel layer and the source line and configured to have a P type impurity doped therein, and a second junction interposed between the end of the other side of the channel layer and the bit line and configured to have an N type impurity doped therein.

Abstract: A semiconductor device comprising a silicon substrate, a gate structure and a heteroatom-containing epitaxial structure is provided. The gate structure is disposed on a surface of the silicon substrate. The heteroatom-containing epitaxial structure is disposed adjacent to the gate structure and has a major portion and an extension portion, wherein the major portion virtual vertically extends downwards into the silicon substrate from the surface; and the extension portion further extends downwards into the silicon substrate with a tapered cross-section continuing with the major portion.

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.

Abstract: An LDMOS device may include at least one of a second conduction type buried layer and a first conduction type drain extension region. An LDMOS device may include a second conduction type drain extension region configured to be formed in a portion of the first conduction type drain extension region. The second conduction type drain extension region may include a gate pattern and a drain region. An LDMOS device may include a first conduction type body having surface contact with the second conduction type drain extension region and may include a source region. An LDMOS device may include a first guard ring formed around the second conduction type drain extension region. An LDMOS device may include a second guard ring configured to be formed around the first guard ring and configured to be connected to a different region of the second conduction type buried layer.

Abstract: The present invention relates to a method of manufacturing a semiconductor device, and the method uses the mode of thermal annealing the source/drain regions and performing Halo ion implantation to form a Halo ion-implanted region by: first removing the dummy gate to expose the gate dielectric layer to form an opening; then performing a tilted Halo ion implantation to the device from the opening to form a Halo ion-implanted region on both sides of the channel of the semiconductor device; and then annealing to activate the dopants in the Halo ion-implanted region; finally performing subsequent process to the device according to the requirement of the manufacture process.

Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

Abstract: A drain of a first transistor is formed by performing ion implantation on a semiconductor substrate using a first member as a mask for a gate electrode of the first transistor. Further, ion implantation is performed on the gate electrode of the second transistor after thinning a second member.

Abstract: The present invention provides a semiconductor device and a method for manufacturing the same. The method includes: providing a substrate; forming a gate stack on the substrate; forming an inter layer dielectric (ILD) to cover the device; etching the ILD at both sides of the gate stack and the substrate below the ILD, so as to form a groove of source and drain regions respectively; depositing a metal diffusion barrier layer in the groove; and filling the groove with a metal to form the source and drain regions. The semiconductor device includes: a substrate; a gate stack on the substrate; an inter layer dielectric (ILD) covering the device; a groove of source and drain regions formed in the ILD at both sides of the gate stack and the substrate below the ILD; and a metal diffusion barrier layer and a metal filler formed in the groove.

Abstract: An ESD protection device is described, which includes a P-body region, a P-type doped region, an N-type doped region and an N-sinker region. The P-body region is configured in a substrate. The P-type doped region is configured in the middle of the P-body region. The N-type doped region is configured in the P-body region and surrounds the P-type doped region. The N-sinker region is configured in the substrate and surrounds the P-body region.

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract: Methods for ion implantation. A method comprises forming a layer of non-crosslinking mask material over a semiconductor region; forming a patterned photoresist layer over the non-crosslinking mask layer; removing the photoresist layer and the non-crosslinking mask layer from the exposed regions, while the masked regions remain covered; and implanting dopant ions into the exposed regions, the dopant ions being blocked from the masked regions. The non-crosslinking mask layer and any remaining photoresist material may be removed. In additional embodiments, the non-crosslinking material comprises carbon. In another embodiment, the non-crosslinking material comprises an oxide. Ion implantations for source and drain, lightly doped drain, and well regions are performed.

Abstract: A semiconductor device according to the present invention includes a contact region 201 of a second conductivity type which is provided in a body region 104. The contact region 201 includes a first region 201a in contact with a first ohmic electrode 122 and a second region 201b located at a position deeper than that of the first region 201a and in contact with the body region 104. The first region 201a and the second region 201b each have at least one peak of impurity concentration. The peak of impurity concentration in the first region 201a has a higher value than that of the peak of impurity concentration in the second region 201b.

Abstract: A method for decreasing polysilicon gate resistance in a carbon co-implantation process which includes: depositing a first salicide block layer on a formed gate of a MOS device and etching it to form a first spacer of a side surface of the gate of the MOS device; performing a P-type heavily doped boron implantation process and a thermal annealing treatment, so as to decrease the resistance of the polysilicon gate; removing said first spacer, performing a lightly doped drain process, and performing a carbon co-implantation process at the same time, so as to form ultra-shallow junctions at the interfaces between a substrate and source region and drain region below the gate; re-depositing a second salicide block layer on the gate and etching the mask to form a second spacer; forming a self-aligned silicide on the surface of the MOS device. The invention can decrease the resistance of the P-type polysilicon gate.

Abstract: A method for fabricating a semiconductor device including providing a semiconductor substrate having a first opening and second opening. A dielectric layer is formed on the substrate. An etch stop layer on the dielectric layer in the first opening. Thereafter, a work function layer is formed on the etch stop layer and fill metal is provided on the work function layer to fill the first opening.

Abstract: With the evacuation of an interior of a vacuum chamber halted and with gas supply into the vacuum chamber halted, in a state that a mixed gas of helium gas and diborane gas is sealed in the vacuum chamber, a plasma is generated in a vacuum vessel and simultaneously a high-frequency power is supplied to a sample electrode. By the high-frequency power supplied to the sample electrode, boron is introduced to a proximity to a substrate surface.

Abstract: The present invention provides a method and apparatus for manufacturing a semiconductor device using a PVD method and enabling achievement of a desired effective work function and reduction in leak current without increasing an equivalent oxide thickness. A method for manufacturing a semiconductor device in an embodiment of the present invention includes the steps of: preparing a substrate on which an insulating film having a relative permittivity higher than that of a silicon oxide film is formed; and depositing a metal nitride film on the insulating film. The metal nitride depositing step is a step of sputtering deposition in an evacuatable chamber using a metal target and a cusp magnetic field formed over a surface of the metal target by a magnet mechanism in which magnet pieces are arranged as grid points in such a grid form that the adjacent magnet pieces have their polarities reversed from each other.

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a gate structure, a source region and a drain region. The gate structure is disposed on a substrate. The source and drain regions disposed at respective sides of the gate structure include a boron-doped silicon germanium (SiGeB) layer substantially without stress relaxation. The boron-doped silicon germanium (SiGeB) layer has a germanium concentration greater than 30 at % and an in-situ doping concentration of boron ranging between 2.65×1020/cm3 and 1×1021/cm3.

Abstract: A fabricating method of a semiconductor element includes the following steps. First, a substrate is provided. A metal gate structure and source/drain electrodes are already formed on the substrate. An amorphization process is performed in the source/drain electrodes to form an amorphous portion. An interlayer dielectric layer is formed on surfaces of the source/drain electrodes and a through hole contact is formed within the interlayer dielectric layer. A silicidation process is performed with the through hole contact and the amorphous portion of the source/drain electrodes to form a metal silicide layer. The fabricating method is capable of finishing the formation of the metal silicide layer in the condition that diameters of the through hole contact is becoming smaller and smaller.

Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein only the source region comprises at least one dislocation. The method for forming a transistor according to the present invention comprises forming a mask layer on a semiconductor substrate on which a gate has been formed so that the mask layer covers the gate and the semiconductor substrate; patterning the mask layer to only expose at least a portion of a source region; performing a first ion implantation to the exposed portion of the source region; and annealing the semiconductor substrate so as to form a dislocation in the exposed portion of the source region.

Abstract: Disclosed is a memory device and method of operation thereof. The memory device may include a source region and a drain region of a first dopant type, the source and drain regions contain a first semiconductor material; a body region of a second dopant type, the body region being sandwiched between the source and drain regions, the body comprising a second semiconductor material; a gate dielectric layer over at least the body region; and a gate comprising a conductive material over the gate dielectric layer. Specifically, one of the first semiconductor material and the second semiconductor material is lattice matched with the other of the first semiconductor material and the second semiconductor material and has an energy gap smaller than the energy gap of the other of the first semiconductor material and the second semiconductor material.

Abstract: A method for decreasing polysilicon gate resistance in a carbon co-implantation process which includes: depositing a first salicide block layer on a formed gate of a MOS device and etching it to form a first spacer of a side surface of the gate of the MOS device; performing a P-type heavily doped boron implantation process and a thermal annealing treatment, so as to decrease the resistance of the polysilicon gate; removing said first spacer, performing a lightly doped drain process, and performing a carbon co-implantation process at the same time, so as to form ultra-shallow junctions at the interfaces between a substrate and source region and drain region below the gate; re-depositing a second salicide block layer on the gate and etching the mask to form a second spacer; forming a self-aligned silicide on the surface of the MOS device. The invention can decrease the resistance of the P-type polysilicon gate.

Abstract: A memory includes a first tunneling field effect transistor including a first drain and a first source, the first drain coupled to a first resistive memory element. The memory includes a second tunneling field effect transistor including a second drain and sharing the first source, the second drain coupled to a second resistive memory element. The memory includes a first region coupled to the first source for providing a source node.