Abstract: A new and improved method for fabricating planarized isolation trenches, wherein erosion of insulating material at the edges of trenches is surpressed without sacrificing a minimal width of the isolation trench, has been developed. The process fabricates sidewall spacers before etching the isolation trench into the semiconductor substrate. After filling the etched trench with insulating material and plartarization of the insulating material, the sidewall spacers protect the insulating material filling the trench and prevent the formation of "divots" at the edges of the trench. Since the spacers are formed prior to the etching of the trench in the semiconductor substrate, a minimal width of the isolation trench can be maintained and less area is required for the isolation trench.

Abstract: An oxygen ion is implanted into a silicon substrate at a dose of 3.times.10.sup.17 (cm.sup.-2) or lower. Then, the silicon substrate is heated at 1250.degree. C. or lower for 40 minute or longer. And the silicon substrate is heated at 1300.degree. C. or higher in an inert gas atmosphere. Further, the silicon substrate is heated at 1300.degree. C. or higher in an atmosphere containing an oxygen gas in an amount of 1% by volume or more.

Abstract: A solar cell and a method of producing the same which realizes electrical separation of the p n junction in a simple manner, and a method of producing a semiconductor device a method of producing a semiconductor device in which an electrode is formed by using a metallic paste material on a substrate covered with a silicon nitride film or a titanium oxide film, wherein a glass paste 104 composed mainly of glass which has a property of melting silicon is provided on an n type diffusion layer 101 in the p n junction; the substrate is baked so that penetration of the n type diffusion layer 101 is effected by the glass paste; aluminum is diffused in the n type diffusion layer 101 below a p electrode 103 formed of an aluminum silver paste to thereby form a p type inversion layer 105 inverted to a p type, whereby the electrical separation of the p n junction can be realized.

Abstract: A method of fabricating a SOI wafer is disclosed, which comprises the steps of: providing a silicon-on-insulator wafer wherein an oxide is formed between a base substrate and a devise substrate; thinning the device substrate to form a Si layer; etching the Si layer to expose the surface of the oxide film, to form trenches; forming polishing stoppers within the trenches, each polishing stopper have a smaller thickness in its center portion and a greater thickness in its outer portion; heat-treating the polishing stopper; and polishing, via chemical and mechanical polishing, the Si layer using the polishing stopper to form a device formation layer.

Abstract: A trench isolation is formed in a silicon substrate for defining active areas assigned to circuit components, and has an upper surface lower than a gate oxide layer grown on the adjacent active area; when the trench isolation is formed, silicon oxide is removed from the periphery of the silicon substrate defining a trench, then the surface of the silicon substrate is oxidized so that the silicon oxide deeply penetrates from the periphery into the silicon substrate, and, thereafter, insulating material fills the secondary trench defined by the silicon oxide; even through a gate electrode is patterned over the trench isolation, a pattern image for the gate electrode is exactly transferred to a photo-resist layer extending over the trench isolation, and the deeply penetrated silicon oxide prevents the channel region from concentration of electric field, thereby preventing the field effect transistor from the kinks and the inverse narrow width effect.

Abstract: On the surface of a hydrogen-terminated diamond 1 formed by terminating a surface 2 of either a homoepitaxial diamond or a heteroepitaxial diamond or a surface-flattened polycrystal diamond are formed a drain-ohmic contact 4 and a source-ohmic contact 3 of gold or platinum, an insulating layer 5 formed of silicon oxide (SiO.sub.x : 1.ltoreq.X.ltoreq.2) and a gate electrode 6 mounted on said insulating layer, and the surface other than the element forming region is set to be an insulating region being non-hydrogen-terminated, for example, oxygen-terminated, and the elements formed on said region is being isolated.

Abstract: This invention discloses a MOSFET power device supported on a substrate. The MOSFET power device includes a plurality polysilicon-with-oxide-cap segments disposed over a gate oxide layer including two outermost segments and a plurality of inner segments include a plurality of gate oxide-plug openings. Each of the inner segments functions as agate and the two outer most segments function as a field plate and an equal potential ring separated by a termination oxide-plug gap and the gate oxide-plug openings and the termination oxide-plug gap having an aspect ratio greater or equal to 0.5. The MOSFET power device further includes a plurality of MOSFET transistor cells for each of the gates, wherein each transistor cells further includes a source region, a body region, the transistor cells further having a common drain disposed at a bottom surface of the substrate.

Abstract: An SOI semiconductor design methodology enables the implementation of simplified STI processes by the design and formation of a shallow trench isolation frame around an electrically active semiconductor region. The simplified STI processes include the fabrication of a trench by phase edge etching, trench sidewall oxidation, TEOS fill, and, finally a chemical or mechanical polish. The attribute which enables the simple process is that all isolation images can be current minimum or near minimum size, specifically no wider than twice the over-lay tolerance of the technology.

Abstract: An SOI substrate and a method for fabricating the same are provided to sharpen the departing angle at the circumference of the active substrate, and provide the active substrate with a uniform thickness. An attached wafer of the present invention is formed by processing the upper side of the base substrate so that its thickness increases from the center to the circumference, and attaching the active substrate to the processed side of the base substrate. The unattached portion of the attached wafer is removed. Then mirror processing is performed to provide the active substrate with a substantially uniform thickness along the processed side of the base substrate.

Abstract: Isolation methods for integrated circuits use plasma chemical vapor deposition of an insulating layer followed by lift-off to remove at least portions of the insulating layer. In particular, a lift-off layer is formed on an integrated circuit substrate. The lift-off layer and the integrated circuit substrate beneath the lift-off layer are etched to form a trench in the integrated circuit substrate. The trench defines a first region on one side of the trench and a second region that is narrower than the first region on the other side of the trench. Plasma chemical vapor deposition is then performed to form an insulating layer filling the trench, on the first region and on the second region, with the insulating layer on the first region being thicker than on the second region. The insulating layer is then etched to expose the lift-off layer in the second region. The lift-off layer is then lifted off from the first region.

Abstract: A semiconductor device includes a plurality of single crystal semiconductor island layers formed on a semiconductor substrate with a first insulating layer intervened therebetween, the single crystal semiconductor island layers being isolated from one another by a second insulating layer. In forming the single crystal semiconductor island layers, a single crystal semiconductor layer is formed and is selectively removed on the first insulating layer. The second insulating layer is buried between adjacent ones of the single crystal semiconductor island layers. The second insulating layer is formed over the entire surface inclusive of the single crystal semiconductor island layers and a surface portion of the second insulating layer is removed by an etching process or a polishing process.

Abstract: A semiconductor device having an adjacent P-well and N-well, such as a complementary metal oxide semiconductor (CMOS) transistor, on a silicon on insulator (SOI) substrate has a latch-up problem caused by the parasitic bipolar effect. This invention provides a semiconductor device removing the latch-up problem and methods for fabricating the same. A semiconductor device according to the present invention has a T-shaped field oxide layer connected to a buried oxide layer of the SOI substrate to prevent the latch-up problem.

Abstract: According to a preferred embodiment of the present invention, a stress-reducing region formed on a wafer allows standard bulk CMOS (non-SOI) devices and SOI devices to be reliably fabricated on the same wafer. The high-stress interface that typically exists between the SOI device regions and the non-SOI device regions is transferred to a region where the high-stress will be reduced and relaxed. Typically, this means that the high-stress interface will be fabricated so as to lie over a region of the wafer similar to Shallow Trench Isolation (STI) regions. In addition, by using another preferred embodiment of the present invention, a coplanar wafer surface can be maintained for a wafer which includes both bulk CMOS devices and SOI devices. This is accomplished by etching the silicon wafer in the SOI device regions prior to the oxygen implantation so that the surface of the area between the stress interface regions is lower than the overall surface of the remainder of the wafer. Then, when the SiO.sub.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, an active layer in the substrate and a silicon carbide buried layer which provides a conduction barrier between the substrate and at least a portion of the active layer. The buried layer is preferably formed by implanting second conductivity type dopants into the substrate so that a P-N junction barrier is provided between the active layer and the substrate. The buried layer may also be formed by implanting electrically inactive ions into the substrate so that a relatively high resistance barrier is provided between the active layer and the substrate. The electrically inactive ions are preferably selected from the group consisting of argon, neon, carbon and silicon, although other ions which are electrically inactive in silicon carbide may be used.

Abstract: The present invention provides a method of fabricating fully dielectric isolated silicon (FDIS) by anodizing a buried doped silicon layer through trenches formed between active areas to form a porous silicon layer; oxidizing the porous silicon layer through the trenches to form a buried oxide layer; and by depositing a dielectric in the trenches. The process begins by forming a buried doped layer in a silicon substrate defining a silicon top layer over the conductive buried doped layer. The silicon top layer and the buried doped layer are patterned to form trenches that extend into but not through the buried doped layer. The trenches define isolated silicon regions. The buried doped layer is anodized to form a porous silicon layer. The porous silicon layer is converted into a buried oxide layer by oxidation. The oxidation step also forms a liner oxide layer on the tops and sidewalls of the isolated silicon regions.

Abstract: A semiconductor integrated circuit is formed by MESA isolation of a thin film silicon layer, in which transistor characteristics are free from influence depending on pattern density of transistor forming regions. The thin film silicon layer on an insulating substrate is isolated by MESA isolation, and element forming regions are formed. In the middle part of a large distance between adjacent element forming regions, a LOCOS oxide film is thickly formed, and an oxide film is filled-in or buried between the LOCOS oxide film and the element forming regions contiguously at the same surface level so that there is no step-like level difference therebetween.

Abstract: A method of producing an SOI substrate having a single-crystal silicon layer on a buried oxide layer in an electrically insulating state from the substrate by implanting oxygen ions into a single crystal silicon substrate and practicing an anneal processing in an inert gas atmosphere at high temperatures to form the buried oxide layer. After the anneal processing in which the thickness of the buried oxide layer becomes a theoretical value in conformity with the thickness of the buried oxide layer formed by the implanted oxygen, the oxidation processing of the substrate is carried out in a high temperature oxygen atmosphere.

Abstract: A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after etch back. In a silicon-on-insulator (SOI) device, dummy active areas are inserted between the active areas in order to maintain the thickness of the refill layer between the mesas to insure proper isolation between the active devices. The technique is also applicable to non-SOI devices.

Abstract: After partially burying an insulation layer in a first single-crystalline silicon substrate, and flattening, the first single-crystalline silicon substrate and a second single-crystalline substrate are formed with a low impurity concentration epitaxial layer. By grinding and polishing the first single crystalline silicon substrate, an ultra thin film SOI layer having thickness of about 0.1 .mu.m is formed. On the ultra thin film SOI layer, an insulation layer 8 for isolation is formed. Thus, an SOI substrate for integrating the power element and a control circuit element including the ultra thin film SOI layer in one chip can be provided.

Abstract: A method for producing an electrically conductive element is provided in which an oxidation barrier is formed through modification of one or more layers which initially were receptive to oxidation.

Abstract: After formation of a sandwich over a substrate of a layer of silicon dioxide (3) followed by a layer of silicon (1) having a pad oxide (7) thereon and a patterned silicon nitride layer (9) over the pad oxide, the unmasked portion of the pad oxide and silicon are removed to provide mesas of silicon with silicon nitride thereover and possibly removal of some of the buried oxide layer. A flowable insulator (15), preferably silsesquioxane (H.sub.x SiO.sub.1.5, where x.ltoreq.1, depending upon the level of polymerization) in a contaminant-free, high purity solvent which is later removed during an annealing step, is placed over the exposed surface such that it fills the voids between the mesas of silicon with silicon nitride thereon and extends over the nitride. The flowable insulator, due to its flowability, provides a generally planar surface. The flowable insulator is etched back and a cap oxide (17) is optionally deposited over the etched back insulator layer.

Abstract: A photosensitive device includes an array of active pixel sensor devices, each APS device being formed in an isolated cell of silicon. Each cell has an insulating barrier around it, and sits upon an insulating layer formed on an underlying substrate. A semiconductor connector making vertical contact between the pinning layer and the body of each APS device preferably replaces at least some portion of the insulating barrier adjacent to each cell. The semiconductor connector may be a single vertical connection for each cell or it may be an elongated strip connecting multiple APS devices. It may extend only to the underlying insulating layer or it may extend through the insulating layer to the substrate, with the substrate acting to interconnect and ground the pinning layer and the body of each APS device. The invention also includes the method of making the photosensitive device.

Abstract: A method for forming an isolation wall in a silicon semiconductor substrate wherein a trench is etched into the silicon using a hard mask, a layer of silicon dioxide is formed on the side walls of the trench, a filling of polysilicon is placed in the region between the side wall layers, the polysilicon is planarized by etching while the hard mask remains in place, and the hard mask then is stripped from the silicon, permitting field oxide to be grown over the trench region.

Abstract: A polysilicon film is deposited in a trench formed in a silicon element substrate. The polysilicon film in the trench and on the silicon element substrate is anisotropically etched, so that the film remains on the side wall of the trench. The polysilicon film on the side wall is oxidized to obtain an insulating film, which buries the trench. At the same time, an oxidized film is formed on the surface of the silicon element substrate to complete a trench-mold separation area.

Abstract: In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.

Abstract: The present invention relates to a method of manufacturing a semiconductor device for forming an insulated gate field effect transistor in a completely isolated SOI layer, and has for its object to prevent depletion or inversion surely by introducing impurities of sufficiently high concentration into an SOI layer adjacent to an isolating film filled up between element regions of the SOI layer and a backing insulating layer and to aim at flattening of the SOI substrate surface, and further, includes the steps of implanting impurity ions into a semiconductor layer from an oblique direction so as to reach the semiconductor layer under an oxidation-preventive mask using the oxidation-preventive mask as a mask for ion implantation, heating the semiconductor layer in an oxidizing atmosphere with the oxidation-preventive mask so as to form a local oxide film to isolate the semiconductor layer, and also forming a impurity region with impurities implanted into the semiconductor layer in a region adjacent to the local

Abstract: A method of forming an isolating trench device in a semiconductor device comprising the steps of; sequentially forming a first material layer and a second material layer over a surface of a semiconductor substrate, exposing a portion of the semiconductor substrate in which a device isolation region is to be formed by selectively etching the first and second material layers, forming side wall spacers on exposed lateral sidewalls of the first and second material layers, forming a trench by etching the exposed portion of the semiconductor substrate using the side wall spacers as a mask, depositing an insulating film having an underlayer dependency characteristic over the surface of the resulting structure, etching the surface of the insulating film, and removing the first and second material layers.

Abstract: A method of making an integrated circuit in semiconductor on insulator material and the circuit which comprises providing a semiconductor on insulator structure having a device layer, preferably silicon, and an electrically insulating layer, the device layer being in contact with one surface of the electrically insulating layer. An underlayer is provided which contacts the opposing surface of the electrically insulating layer. The structure is then patterned and trenches are etched to expose a surface of the underlying layer and to form mesas extending from the underlying layer. Ions can now optionally be implanted into selected regions of the underlying layer. A dielectric is provided between the mesas extending to or into the substrate and fabrication of the integrated circuit is then completed. The dielectric can be a thermal oxide at the exposed surface with a dielectric over the thermal oxide.

Abstract: A method of fabricating a semiconductor device which includes the steps of forming a trench (4), and repeating the formation and removal of an oxide film (a sacrificial oxide film) twice to provide a rounded configuration (5b) of an opening portion of the trench (4) and a rounded configuration (6b) of a bottom thereof and to draw defects in a semiconductor layer into a silicon oxide film (8), reducing the defects adjacent the inner wall of the trench (4), whereby electric field concentration on a gate is prevented and the mobility of carriers in channels is improved for an improvement in characteristic, particularly an on-state voltage, of a power device.

Abstract: Isolation regions for a semiconductor layer of a semiconductor-on-insulator substrate are fabricated by forming a patterned implantation mask on the semiconductor layer. The patterned implantation mask includes mask sidewalls. An implantation masking film is formed on the sidewalls of the patterned implantation mask. Ions are implanted into the semiconductor layer, using the patterned implantation layer and the implantation masking film as a mask, to thereby form a doped region in the semiconductor layer. Sidewall spacers are formed on the implantation masking film, opposite the patterned implantation mask. The doped region between the sidewall spacers is etched to thereby define a trench in the semiconductor layer between the sidewall spacers and a doped edge layer in the semiconductor layer which extends from the trench to the implantation masking film. Insulating material is then formed in the trench.

Abstract: A method of forming an isolation oxide (30) on a silicon-on-insulator (SOI) substrate (21) includes disposing a mask layer (26, 27) over a region of a silicon layer (24) of the SOI substrate (21). The isolation oxide (30) is grown in a different region (28) of the silicon layer (24). The isolation oxide (30) is grown to a depth (32) within the silicon layer (24) of less than or equal to a thickness (29) of the silicon layer (24). After removing the mask layer (26, 27), the isolation oxide (30) is further grown in the different region (28) of the silicon layer (24) such that the isolation oxide (30) is coupled to a buried electrically insulating layer (23) within the SOI substrate (21). The buried electrically insulating layer (23) and the isolation oxide (30) electrically isolate an active region (43) of a semiconductor device (20).

Abstract: The present invention provides a method of forming an SOI substrate which causes no variation in thickness of SOI layers formed by polishing the silicon substrate, thereby causing no factor interfering with a reduction in thickness of the SOI layers.In the method of forming an SOI substrate, the surface of a silicon substrate which is form to have unevenness is covered with an insulator serving as a polishing stopper layer, and a polishing substrate is laminated on the insulator. The rear side of the silicon substrate is chemically polished with a polishing solution consisting of an alkali solution to leave as SOI layers the projection portions of the silicon substrate.

Abstract: Oxygen induced lattice slip defects are reduced in device layer 26 of silicon-on-insulator structure 12, 16, 26. At the bottom of trenches 22 notches 28 are etched into the dielectric layer 16. A thermal oxide process provides protrusions 30 of oxide into the substrate. The protrusions 30 direct defects into the support layer 12.

Abstract: A SIMOX substrate 1 is processed through high temperature oxidation treatment after forming a mask-pattern 3 to shield specified electrodes from oxidation in order to increase partly a thickness of a buffed oxide layer 2 to form an area 4. Next, after an oxide film is removed from the surface of the substrate and LOCOS separation is practiced, MOSFET is produced by fabricating a source S and a drain D on the area 4 or the buffed oxide layer 2. Since the buried oxide layer corresponding to electrodes parts influenced by disadvantages of parasitic capacitance are thickened, an operation speed of an inverter is not much decreased and since mean thickness of the buried oxide layer can be thinner, a decrease of a drain electric current by negative electrical resistance can be suppressed. Furthermore, since the thickness of the buffed oxide layer can be controlled in response to each device, plural devices having different breakdown voltages are formed together on the same substrate.

Abstract: In a semiconductor island structure with passive side isolation, a method and structure for reducing corner breakdown where a device conductor crosses the edge of the island. The decrease in the field strength at the island edge between the conductor and the adjacent conducting region may be achieved by increasing the depth of the insulator beneath the conductor where it crosses the island edge without the necessity for increasing the thickness of the layer of insulation applied directly to the surface of the island by the use of a second or higher level interconnect, e.g., the conventional deposition of one or more additional layers of insulation over the device terminal to increase the spacing between the conductor and the surface of the island. In this way the process by which the device is constructed may remain unchanged.

Abstract: A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Abstract: A buried oxide film and an SOI layer are formed on the main surface of a substrate. A nitride film patterned in predetermined configuration is formed on the surface of the SOI layer. The first selective oxidation treatment is applied to the SOI layer with the nitride film used as a mask. At this stage, the isolating oxide film is formed not to reach the buried oxide film. Anisotropic etching is applied to the isolating oxide film with the nitride film used as a mask. A sidewall insulating layer of oxidation-resistant material is formed on the sidewall of the nitride film. With the sidewall insulating layer and nitride film used as masks, the second selective oxidation treatment is applied to the SOI layer, thereby forming an isolating oxide film. Thereby, it becomes possible to prevent a parasitic MOS transistor being formed in the end of the SOI layer.

Abstract: One or a plurality of silicon growth layers are formed on both sides of a silicon base substrate wafer and the product is then divided, with the dividing plane in said silicon base substrate wafer parallel to the main surface, into two pieces to obtain two substrates used for manufacturing silicon semiconductor elements. Said dividing-in-half process is a process in which said silicon base substrate wafer portion is cut along a plane parallel to the main surface, or a process which includes said cutting process followed by a process of treating the cut-surface. Said process which cuts the silicon base substrate wafer portion is a process in which the wafers are cut one by one, or cut after a plurality of them are laminated.

Abstract: A fabrication method of a semiconductor device that can realize a semiconductor device having an improved radiation performance of heat together with a low parasitic capacitance between a semiconductor substrate and a conductor of the device. An SOI structure having a single-crystal silicon layer formed on an insulating substructure is prepared and then, device regions are formed on the substructure by using the single-crystal silicon layer. Sidewall insulators are formed to cover side faces of the respective device regions, laterally isolating the device regions from each other. A resistive silicon layer is formed on a non-device region of the substructure. The resistive silicon layer has a resistivity or specific resistance greater than that of the device regions. Electronic elements are formed in the device regions. The resistive silicon layer may be made of polysilicon or single-crystal silicon.

Abstract: Disclosed is a semiconductor device in which dummy regions which are lower than an isolated element region are formed around the isolated element region. Another dummy region which has a height nearly equal to those of element regions may be formed at a non-element-region-existing region, accompanying with lower dummy regions. The method for making the semiconductor device has the steps of suitably forming the element regions and dummy regions on a insulating layer on a substrate, depositing a insulator on the entire surface of the insulating layer and polishing the insulator to obtain a plane surface.

Abstract: A contact region for a trench in a semiconductor device and a method for electrically contacting the conductive material in a trench that is too narrow for conventional electrical contacts may include a contact region in which the trench is divided into two or more trench sections, each section having the same narrow width as the undivided trench. The two or more trench sections are separated by one or more islands that are isolated from the semiconductor device. An aperture through the material above the contact region provides access for electrically contacting the conductive material in the trench sections.

Abstract: An electrostatic image is developed by disposing an electrostatic image bearing member which holds an electrostatic image on its surface and a developer carrying member which carries an insulating developer on its surface with a certain gap provided therebetween, at a developing section bringing an insulating developer containing a nitrogen-containing compound to a thickness thinner than the gap on the developer carrying member and transferring said developer onto the above electrostatic image bearing member at the developing section. The nitrogen-containing compound has nitrogen in the form of a heterocyclic ring and imparts stable positive chargeability to the developer.