Abstract: A dielectrically separated wafer and a fabrication method of the same are provided according to the first, second and third embodiments of the present invention. According to the first embodiment, it becomes possible to expand the device fabrication surface area of the dielectrically separated silicon islands by laminating a low concentration impurity layer including a dopant of the same conductivity on a high concentration impurity layer formed on the bottom of the island. According to the second embodiment, a dielectrically separated wafer and a fabrication method for the same which can grow a polysilicon layer without producing voids in the dielectrically separating oxide layer is provided by forming a seed polysilicon layer at low temperature and under low pressure and by forming, on the seed polysilicon layer, a high temperature polysilicon layer 16.

Abstract: The present invention provides a SOI wafer produced by an ion implantation delamination method wherein a width of a SOI island region in a terrace portion generated in an edge portion of the SOI wafer where a surface of a base wafer is exposed is narrower than 1 mm and a density of pit-shaped defects having a size of 0.19 &mgr;m or more existing in a surface of a SOI layer detected by a LPD inspection is 1 counts/cm2 or less, and also provides a method for producing the SOI wafer. Thereby, there is provided a SOI wafer produced by an ion implantation delamination method wherein generation of SOI islands generated in delamination can be suppressed and a defect density of LPDs existing in a surface of the SOI wafer can be reduced, and a method for producing the same, so that device failure can be reduced.

Abstract: The present invention provides two or more test structures/substructures (100) that are used in a test pattern (500, 600, 700, 800) to determine a cracking threshold for a dielectric material (104) on a substrate. Each test structure/substructure (100) includes two metal structures (102) separated by the dielectric material (104) having a width (G) which is different for each test structure/substructure (100). The cracking threshold will be approximately equal to the largest width (G) of dielectric material (104) that is cracked after processing. The present invention also provides a method for determining the cracking threshold for the dielectric material (104). Two or more test structures (100) are formed on the substrate (402) followed by a determination of whether the dielectric material (104) between the two metal structures (102) for each test structure (100) has cracked during processing (404).

Abstract: A semiconductor device with dynamic threshold transistors includes a complex element isolation region composed of a shallow element isolation region made of shallow trench isolation and deep element isolation regions provided on both sides of the shallow element isolation region. Since the shallow element isolation region is made of the shallow trench isolation, Bird's beak in the shallow element isolation region is small. This prevents off leakage failure due to stress caused by the bird's beak. The deep element isolation region has an approximately constant width which allows the complex element isolation region to be wide.

Abstract: A method of forming a silicon oxide, shallow trench isolation (STI) region, featuring a silicon rich, silicon oxide layer used to protect the STI region from a subsequent wet etch procedure, has been developed. The method features depositing a silicon oxide layer via PECVD procedures, without RF bias, using a high silane to oxygen ratio, resulting in a silicon rich, silicon oxide layer, located surrounding the STI region. The low etch rate of the silicon rich, silicon oxide layer, protect the silicon oxide STI region from buffered hydrofluoric wet etch procedures, used for removal of a dioxide pad layer.

Abstract: An integration process in a SOI substrate of a semiconductor device having at least a dielectrically insulated well, the process including: an oxidizing step directed to form an oxide layer; a depositing step of a nitride layer onto the oxide layer; a masking step, carried out onto the nitride layer using a resist layer and directed to define suitable photolithographic openings for forming at least one dielectric trench effective to provide side insulation for the well; an etching step of the nitride layer and oxide layer, as suitably masked by the resist layer, the nitride layer being used as a hardmask; a step of forming the at least one dielectric trench, which step comprises at least one step of etching the substrate, an oxidizing step of at least sidewalls of the at least one dielectric trench, and a step of filling the at least one trench with a filling material; and a step of defining active areas of components to be integrated in the well, being carried out after the step of forming the at least one d

Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.

Abstract: A semiconductor-on-insulator (SOI) device includes a thermoelectric cooler on a back side of the device. The thermoelectric cooler is formed on a thinned portion of a deep bulk semiconductor layer of the SOI device. The thermoelectric device includes a plurality of pairs of opposite conductivity semiconductor material blocks formed on a metal layer deposited on the thinned portion. The thinning of the thinned portion may be accomplished in multiple etching steps of the deep silicon layer, such as a fast etching down to an etch stop and a slower, more controlled etch to the desired thickness for the thinned portion.

Abstract: A method of fabricating a semiconductor device capable of suppressing defective etching in formation of a deep trench also when the number of polishing steps is reduced is obtained. This method of fabricating a semiconductor device comprises steps of forming a first trench on an element isolation region of a semiconductor substrate, forming a first film consisting of an insulator film to fill up the first trench, forming a second trench larger in depth than the first trench in the first trench, forming an embedded film in the second trench and substantially simultaneously polishing an excess depositional portion of the first film and an excess depositional portion of the embedded film.

Abstract: A method for fabricating a strained Si layer on insulator, a structure of the strained Si layer on insulator, and electronic systems comprising such layers are disclosed. The method comprises the steps of forming epitaxially a relaxed SiGe layer on top of a Si layer on insulator; transforming the crystalline Si layer and the lower portion of the crystalline relaxed SiGe layer into an amorphous material state by ion implantation; and re-crystallizing the amorphous material from the crystalline top portion of the SiGe layer. The larger lattice constant of the SiGe seed layer forces a tensile strain in the Si layer.

Abstract: Disclosed are an SOI substrate and a method for manufacturing the same. The SOI substrate comprises a silicon substrate including an active region defined by a field region. The field region includes a first oxygen-ion-injected isolation region having a first thickness and being formed under the active region. The center of the first region is at a first depth from a top surface of the silicon substrate. The field region of the SOI substrate further includes a second oxygen-ion-injected region having a second thickness greater than the first thickness. The second region is formed at sides of the active region and is also formed from a top surface of the silicon substrate. The center of the second ion injected region is at a second depth from the top surface of the silicon substrate. The first and second ion injected regions surround the active region for device isolation. The SOI substrate is formed by implementing two sequential ion injecting processes.

Abstract: A SIMOX substrate having a buried oxide layer and a surface single crystal silicon layer formed therein is produced by a method which comprises implanting oxygen ions into a silicon single crystal substrate and subsequently performing a heat treatment at an elevated temperature on the substrate. The method is characterized by performing the former stage of the heat treatment at a temperature of not lower than 1150° C. and lower than the melting point of single crystal silicon in an atmosphere obtained by adding oxygen under a partial pressure of not more than 1% to an inert gas and subsequently performing at least part of the latter stage of the heat treatment by increasing the partial pressure of oxygen within a range in which no internal oxidation is suffered to occur in the buried oxide layer. It can also be prepared by performing the former stage of the high temperature heat treatment at a temperature of not lower than 1150° C.

Abstract: A semiconductor device of the present invention includes a MISFET provided in an element formation region Re of a semiconductor substrate 11 and a trench isolation 13 surrounding the sides of the element formation region Re. An oxygen-passage-suppression film 23 is provided from the top of the trench isolation 13 to the top of a portion of the element formation region Re adjacent to the trench isolation 13. The oxygen-passage-suppression film 23 is made of a silicon nitride film or the like through which oxygen is less likely to permeate. Therefore, since it becomes hard that the upper edge of the element formation region Re of the semiconductor substrate 11 is oxidized, an expansion of the volume of the upper edge is suppressed, thereby reducing a stress.

Abstract: A semiconductor apparatus includes a MOS transistor and a resistive element having insulative first polysilicon and conductive second polysilicon films, an insulating film for a resistive element, and a third polysilicon film. The second polysilicon film is formed in a region adjacent each side edge of the first polysilicon film, and has a contact hole formed therein. The third polysilicon film determines a resistance value of the resistive element, and is continuously formed on the second polysilicon film and the insulating film formed on the first polysilicon film. The MOS transistor is formed in an active region surrounded by the field insulating film, and includes a gate oxide film and a gate electrode including a polysilicon film formed as a lower layer with the second polysilicon film and a polysilicon film formed as an upper layer with the third polysilicon film. A method of making this semiconductor apparatus is also described.

Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.

Abstract: A patterned SOI/SON composite structure and methods of forming the same are provided. In the SOI/SON composite structure, the patterned SOI/SON structures are sandwiched between a Si over-layer and a semiconductor substrate. The method of forming the patterned SOI/SON composite structure includes shared processing steps wherein the SOI and SON structures are formed together. The present invention also provides a method of forming a composite structure which includes buried conductive/SON structures as well as a method of forming a composite structure including only buried void planes.

Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.

Abstract: There is provided a process for fabrication of a SIMOX substrate wherein oxygen ions are implanted into a single crystal silicon substrate and then subjected to a high-temperature heat treatment to form a buried oxide layer and a surface single crystal silicon layer, wherein the single crystal silicon substrate used has a mean resistivity of 100 &OHgr;cm or greater, and there is conducted a step of maintaining a temperature of from 800° C. to 1250° C. for a predetermined time in the final stage of the high-temperature heat treatment, as well as a SIMOX substrate wherein the mean resistivity of the substrate obtained by the process is 100 &OHgr;cm or greater.

Abstract: A nanoscale force sensing device includes a probe having a tip with multiple isolated channels which can receive different materials. The device may be either straight or cantilevered and may be mounted to permit detection of surface forces while performing other functions at the same time.

Abstract: A silicon-on-insulator (SOI) device and a method for manufacturing the same includes a substrate, which includes a base layer, a buried oxide layer, and a semiconductor layer, and an isolation layer which is formed in a trench that defines an active region on the semiconductor layer. The trench comprises a first region having a depth smaller than the thickness of the semiconductor layer and a second region having a depth as much as the thickness of the semiconductor layer. The isolation layer includes an oxide layer and a nitride liner that are sequentially formed along the surface of the trench and a dielectric layer that fills the trench.

Abstract: A substrate for a semiconductor device includes a crystalline silicon substrate; an insulative silicon compound layer thereon and a crystalline insulation layer on the insulative silicon compound layer, wherein the insulative silicon compound layer contains not more than 10 at % of component element of a material constituting the crystalline insulation layer, the component element being provided in the insulative silicon compound layer by diffusion.

Abstract: In a method of producing a trench insulation in a silicon substrate a first silicon-oxide layer is deposited on a front surface of a sequence of layers including the silicon substrate. Then the first silicon-oxide layer is structured so as to define a mask for a subsequent production of a trench. A trench is etched with a predetermined depth in the silicon substrate making use of the mask and filled with a silicon oxide. Then a first polysilicon layer is conformally deposited on the first silicon-oxide layer and on the oxide-filled trench. The first polysilicon layer is removed in such a way that a polysilicon cover remains on the oxide-filled trench, and the first silicon-oxide layer is removed.

Abstract: A method of fabricating a CMOS have self-aligned shallow trench isolation, includes preparing a silicon substrate; forming a gate stack; depositing a layer of first polysilicon; trenching the substrate by shallow trench isolation to form a trench; filling the trench with oxide; depositing a second layer of polysilicon wherein the top surface of the second polysilicon layer is above the top surface of the first polysilicon layer; depositing a sacrificial oxide layer having a thickness of at least 1.5× that of the first polysilicon layer; CMP the sacrificial oxide layer to the level of the upper surface of the second polysilicon layer; depositing a third layer of polysilicon; patterning and etching the gate stack; implanting ions to form a source region, a drain region and the polysilicon gate; and completing the CMOS structure.

Abstract: An alignment mark structure (22) for aligning a mask with prior formed features of in a circuit region when an opaque material layer (88) covers the alignment mark structure (22) is provided. The features of the alignment mark structure (22) are formed in an alignment mark region (20) concurrently while features for a circuit region having vertical gate transistors are being formed. There are no extra or added processing steps added for forming the alignment mark structure (22) because it is formed concurrently while forming features in the circuit region. The resulting alignment mark structure (22) has step features (62) so that the step features (62) can be seen after the opaque material layer (88) covers the alignment mark structure (22).

Abstract: Certain embodiments relate to methods for making a semiconductor device that inhibit the formation of a parasitic device. A method for making a semiconductor device includes a delimiting step and a dopant implantation step. The delimiting step partially oxidizes a single-crystal silicon layer provided on a semiconductor substrate 11 with an insulating layer therebetween to form a plurality of isolated single-crystal-silicon-layer segments 13a delimited by the insulating layer 16. In the implantation step, dopant ions 18 are implanted into the single-crystal-silicon-layer segments 13a to activate the single-crystal-silicon-layer segments 13a. In this implantation step, the dopant is implanted into the single-crystal-silicon-layer segments 13a by an implantation energy which is set so that the position of the maximum of the dopant concentration lies at bottom edges Ea and Eb of each single-crystal-silicon-layer segment 13a.

Abstract: A technique for reducing an on-resistance of a transistor is provided. A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration. Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate. Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased. Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor 1 can be reduced.

Abstract: In an integrated circuit process for SOI including trench device isolation, the problem of voids in the trench fill is addressed by a triple fill process, in which a thermal oxide sidewall having recesses at the bottom corners is covered with a LPCVD deposition that fills in the recesses, followed by a void-free HDP deposition. Densification results in substantially the same etch rate for the three types of oxide.

Abstract: Within a local oxidation of silicon (LOCOS) method for forming a silicon oxide isolation region, there is first amorphized areally completely at least a surface sub-layer portion of a silicon layer within an isolation region location within the silicon layer defined by an oxidation mask layer formed over the silicon layer, to form an amorphized silicon region within the isolation region location. Thus, when thermally oxidizing the silicon layer having formed thereover the oxidation mask layer to form at least in part from the amorphized silicon region a silicon oxide isolation region, the silicon oxide isolation region is formed with an attenuated bird's beak extension.

Abstract: A method for forming a trench in a semiconductor substrate includes configuring a mask on the substrate. The mask has a window in which a substrate surface is uncovered. The substrate is electrochemically etched proceeding from the substrate surface. A porous substrate is formed in a trench-shaped region proceeding from the substrate surface. The trench is formed by removing the porous substrate from the trench-shaped region.

Abstract: In a process for producing a semiconductor member, and a solar cell, making use of a thin-film crystal semiconductor layer, the process includes the steps of: (1) anodizing the surface of a first substrate to form a porous layer at least on one side of the substrate, (2) forming a semiconductor layer at least on the surface of the porous layer, (3) removing the semiconductor layer at its peripheral region, (4) bonding a second substrate to the surface of the semiconductor layer, (5) separating the semiconductor layer from the first substrate at the part of the porous layer, and (6) treating the surface of the first substrate after separation and repeating the above steps (1) to (5).

Abstract: Disclosed is a method of manufacturing a semiconductor device. A plurality of device separation regions are formed in an SOI layer of an SOI substrate, a desired impurity is implanted into a body portion of an Si active layer region, and therereafter a gate electrode is formed with a gate insulation film therebetween. Thereafter, an impurity is implanted into the Si active layer region to form extension portions of source/drain portions, and then an impurity different in polarity from the impurity in the source/drain portions is halo-implanted to form a reverse-characteristic layer. In the halo implantation, the range of projection is set to reach the inside of a buried oxide film. With this configuration, in a fully depleted SOI-MOSFET or the like provided with a thin film SOI layer, it is made possible to simultaneously achieve an improvement of roll-off characteristic and a reduction in parasitic resistance and to secure a sufficient driving capability.

Abstract: A method for manufacturing a thin film semiconductor device is provided which is capable of achieving simplification of manufacturing processes and of improving alignment accuracy without using a plurality of alignment masks. An alignment pattern is formed by using a resist layer having a plurality of regions each having a different film thickness corresponding to each of a plurality of patterns produced using a halftone mask having a halftone exposure region as a photomask and by forming a light transmitting portion to be an aperture pattern and by etching an underlying silicon layer. By having an underlying silicon layer exposed and implanting ions into an entire resist layer, only a main pattern region is doped with the ions.

Abstract: A damascene structure includes a hard mask layer that is applied in a liquid phase to a line dielectric layer. Contemplated hard mask layers comprise a Si—N bond and are densified such that the etch resistivity of the hard mask layer is greater than the etch resistivity of the line dielectric layer and the via dielectric layer in the damascene structure. Particularly preferred hard mask layers include polyperhydrosilazane.

Abstract: An attempt is made to achieve an upward leap in the capacitance of a capacitor of MIM structure and further improvements in the reliability of a semiconductor device. A method of manufacturing a semiconductor device has a step of forming an amorphous silicon film on the surface of a lower electrode of a capacitor, a step for roughening the silicon film, to thereby form rough polysilicon, and a step for etching metal film of a lower electrode while the rough polysilicon is taken as a mask, thereby roughening the surface of the lower electrode. Through the foregoing steps, the surface of a lower electrode of a capacitor of MIM (metal/insulator/metal) structure is formed roughly, thereby increasing the surface area of the capacitor. Thus, a large-capacitance capacitor of MIM structure can be fabricated.

Abstract: In a method for forming a silicon-on-insulator FET having a contact that provides a fixed potential to a substrate, the substrate-biasing between the SOI transistor and the silicon substrate is performed via a plug. As a result, a contact hole for the substrate-biasing does not need to pass through the insulating layer, the silicon layer, and the interlayer insulating layer of the structure. Therefore, the interlayer insulating layer can be made to have shallow depth. Ions can thus be implanted to the surface of the substrate via the contact hole for substrate-biasing. The contact hole for substrate-biasing can be formed without causing an opening fault.

Abstract: A surface flashover resistant multilayer ceramic capacitor. The capacitor has a plurality of layers of the dielectric material and a plurality of electrodes disposed between the layers of dielectric material. The end caps are located at the end of the capacitor and connected to the internal electrodes. A coating of an insulative layer is applied to the outer surface of the capacitor and selected portions of the coating are subsequently removed. The insulative layer coating is a polymer, and specifically a poly-para-xylylene. The insulative layer is applied through a vapor deposition process. The selected portions of the insulative layer are removed by laser ablation.

Abstract: A method for forming an isolation structure (22) on a SOI substrate (11) is provided. A three layer stack of an etchant barrier layer (16), a stress relief layer (17), and an oxide mask layer (18) is formed on the SOI substrate (11). The three layer stack is patterned and etched to expose portions of the etchant barrier layer (16). The silicon layer (13) below the exposed portions of the etchant barrier layer (16) is oxidized to form the isolation structure (22). The isolation structure (22) comprises a bird's head region (21) with a small encroachment which results in higher edge threshold voltage. The method requires minimum over-oxidation and provides for an isolation structure (22) that leaves the SOI substrate (11) planar. Minimal over-oxidation reduces the number of dislocations formed during the oxidation process and improves the source to drain leakage of the device.

Abstract: First, a trench of a semiconductor substrate is filled with a polysilicon film deposited on the surface of the semiconductor substrate. A selective thin film having etching selectivity with respect to the polysilicon film is formed on the polysilicon film. Then, the selective thin film is etched (etched back) so that a part of the selective thin film remains in a depression of the polysilicon film, as a self-aligning mask. The polysilicon film is further etched with the self-aligning mask, thereby forming a polysilicon embedded layer in the trench with a flat surface.

Abstract: A method of forming an electrical isolation trench in a silicon-on-insulator (SOI) structure. The method comprises forming a first oxide layer on top of the upper silicon layer of the SOI structure, forming a polysilicon layer on top of said oxide layer, forming a second oxide layer on top of said polysilicon layer, patterning the first oxide layer, polysilicon layer, and second oxide layer to provide an etch mask, etching the upper silicon layer of the SOI structure to form said trench, and removing said second oxide layer and said polysilicon layer.

Abstract: A method of producing an integrated circuit configuration where trenches are formed surrounding active regions in a main surface of a semiconductor substrate. A photoresist layer is applied to the insulating layer and structured forming a mask using a data processing device, by the following steps: Providing an idealized pattern representing trenches with contours corresponding to contours of the trenches. Producing an idealized mask pattern on the basis of the idealized pattern shifted by an allowance in comparison with the idealized pattern, the idealized mask pattern has surface zones whose distance apart is shorter than a given minimum measurement. The idealized mask pattern is used to produce a further idealized mask pattern in which the surface zones are replaced by minimum surface elements with length measurements which are greater than the given minimum measurement. The trenches are then filled by depositing an insulating layer using the formed mask.

Abstract: A method of forming shallow trench isolation (STI) in a substrate. A shield layer is formed on part of the substrate. Using the shield layer as a mask, part of the substrate is removed to form a trench in the substrate. A first insulation layer is formed in part of the trench, where the trench remains an opening. The first insulation layer is partially etched back to leave a remaining first insulation layer at the bottom of the trench and to expose the sidewall of the trench above the remaining first insulation layer. The trench is filled up with a second insulation layer extending onto the shield layer. A planarization is performed on the second insulation layer, where the shield layer serves as a stop layer for the planarization. Thus, a void-free trench isolation area is formed in a substrate.

Abstract: The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).

Abstract: A manufacturing method for a buried insulating layer-type semiconductor silicon carbide substrate comprises the step of placing an SOI substrate 100, which has a surface silicon layer 130, of a predetermined thickness and a buried insulator 120, in a heating furnace 200 and of increasing the temperature of the atmosphere within heating furnace 200 while supplying a mixed gas (G1+G2) of a hydrogen gas G1 and of a hydrocarbon gas G2 into heating furnace 200, thereby, of metamorphosing surface silicon layer 130 of SOI substrate 100 into a single crystal silicon carbide thin film 140.

Abstract: A silicon-on-insulator substrate having improved thickness uniformity as well as a method of fabricating the same is provided. Specifically, improved thickness uniformity of a SOI substrate is obtained in the present invention by subjecting a bonded or SIMOX (separation by ion implantation of oxygen) SOI substrate to a high-temperature oxidation process that is capable of improving the thickness uniformity of said SOI substrate. During this high-temperature oxidation process surface oxidation of the superficial Si-containing (i.e., the Si-containing layer present atop the buried oxide (BOX) region) occurs; and (ii) internal thermal oxidation (ITOX), i.e., diffusion of oxygen via the superficial Si-containing layer into the interface that exists between the BOX and the superficial Si-containing layer also occurs.

Abstract: A method of forming a trench isolation structure prevents a nitride liner from being over-etched, i.e., prevents the so-called dent phenomenon from occurring. An etching mask pattern is formed on a semiconductor substrate. A trench is formed in the substrate by using the etching mask pattern as an etching mask. A nitride liner, serving as an oxidation barrier layer, is formed at the sides and bottom of the trench, and is then annealed in a furnace to density the same. In a subsequent etching process, such as that used to remove the etching mask pattern, the densified nitride liner resists being etched. Accordingly, a trench isolation structure having a good profile is produced.

Abstract: A silicon wafer having a thick, high-resistivity epitaxially grown layer and a method of depositing a thick, high-resistivity epitaxial layer upon a silicon substrate, such method accomplished by: a) providing a silicon wafer substrate and b) depositing a substantially oxygen free, high-resistivity epitaxial layer, with a thickness of at least 50 &mgr;m, upon the surface of the silicon wafer. The silicon wafer substrate may then, optionally, be removed from the epitaxial layer.

Abstract: A highly-integrated, high speed semiconductor device includes a device isolation film defining an active region at a SOI wafer having a stacked structure of a first silicon layer, a filled insulating film and a second silicon layer-the second silicon layer being the active region between the device isolation film with an intervening first silicide layer; the first silicide layer formed on a gate electrode on the active region and an impurity junction region; and a second silicide layer intervening at the interface of a device isolation film and a second silicon layer and connected to the first silicide layer. Thus, operating characteristics of the device are improved by minimizing the resistance of an impurity junction region and reducing the manufacturing cost.

Abstract: A silicon wafer having a thick, high-resistivity epitaxially grown layer and a method of depositing a thick, high-resistivity epitaxial layer upon a silicon substrate, such method accomplished by: a) providing a silicon wafer substrate and b) depositing a substantially oxygen free, high-resistivity epitaxial layer, with a thickness of at least 50 &mgr;m, upon the surface of the silicon wafer. The silicon wafer substrate may then, optionally, be removed from the epitaxial layer.

Abstract: A process for fabricating an integrated circuit sensor/actuator is described. High aspect ratio deep silicon beams are formed by a process of deep trench etch and silicon undercut release etch by using oxide spacers to protect the silicon beam sidewalls during release etch. An oxide layer is then formed, followed by deposition of a controlled thickness of polysilicon which is then thermally oxidized. The polysilicon layer inside the trenches gets fully oxidized resulting in void-free trench isolation. This process creates a silicon island or beam on three sides leaving the third side for interfacing with the sensor/actuator beams. The sensor/actuator is formed by a similar process of deep trench etch and release etch process on the same substrate. These suspended beams of the sensors and actuators are bridged with the silicon islands from the fourth side. The above process finally results in suspended silicon beams connected to electrically isolated silicon islands.

Abstract: Methods and semiconductor structures are provided for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices. A bulk silicon substrate layer is provided that defines one power distribution rail. A high energy deep oxygen implant is performed to create a deep buried oxide layer and a first intermediate silicon layer. The deep buried oxide layer is disposed between the bulk silicon substrate layer and the first intermediate silicon layer. The first intermediate silicon layer defines another power distribution rail. A lower energy oxygen implant is performed to create a shallow buried oxide layer and a second intermediate silicon layer The shallow buried oxide layer is disposed between the first intermediate silicon layer and the second intermediate silicon layer. A connection to the bulk silicon substrate layer is formed without making electrical connection to the intermediate silicon layers.