Abstract: A process for forming a polycrystalline TFT LCD is provided, thereby greatly reducing the manufacturing cost and time. The process includes steps of performing a first masking procedure to define a gate conductive region, successively forming an insulation layer, an amorphous channel semiconductor layer, a catalytic layer and a doped semiconductor layer, performing a second masking procedure to remove portions of the semiconductor layer and the catalytic layer to define an electrode region, performing a thermal treatment to respectively convert the electrode region and the amorphous semiconductor channel layer into a source/drain region and a crystalline semiconductor channel layer by the catalytic layer, performing a third masking procedure to define data lines, performing a fourth masking procedure to form a contact hole, and performing a fifth masking procedure to define a transparent pixel electrode region, thereby forming the TFT.

Abstract: In a method of producing a trench insulation in a silicon substrate a first silicon-oxide layer is deposited on a front surface of a sequence of layers including the silicon substrate. Then the first silicon-oxide layer is structured so as to define a mask for a subsequent production of a trench. A trench is etched with a predetermined depth in the silicon substrate making use of the mask and filled with a silicon oxide. Then a first polysilicon layer is conformally deposited on the first silicon-oxide layer and on the oxide-filled trench. The first polysilicon layer is removed in such a way that a polysilicon cover remains on the oxide-filled trench, and the first silicon-oxide layer is removed.

Abstract: A process for manufacturing a SOI wafer with buried oxide regions without cusps that includes forming, in a wafer of monocrystalline semiconductor material, trenches extending between, and delimiting laterally, protruding regions; forming masking regions, implanted with nitrogen ions, the masking regions surrounding completely the tips of the protruding regions; and forming retarding regions on the bottom of the trenches, wherein nitrogen is implanted at a lower dose than the masking regions. A thermal oxidation is then carried out and starts at the bottom portion of the protruding regions and then proceeds downwards; thereby, a continuous region of buried oxide is formed and is overlaid by non-oxidized regions corresponding to the tips of the protruding regions and forming nucleus regions for a subsequent epitaxial growth.

Abstract: A method for improving an edge recess of a shallow trench isolation (STI). A SiOx layer with gap-filling ability is formed to fill the edge recess at the top corner of the STI. A part of the SiOx layer on the substrate is then removed, leaving a part of the SiOx layer to fill the edge recess and to cover a sidewall of the substrate at the edge.

Abstract: A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion, depositing a second insulator over substrate (the first insulator has different thermal dissipation characteristics than the second insulator), polishing the second insulator to form a planar surface, and attaching a silicon film over the first insulator and the second insulator.

Abstract: In a semiconductor device of this invention, a first trench having a uniformly inclined surface at a predetermined angle is formed downward from the surface of a semiconductor substrate. A second trench is formed vertically downward from the first trench. These trenches are filled with an insulating film to form a trench element isolation structure. The inclined surface of the first trench can disperse stepwise the electric field generated at an element isolation end and can relax concentration of electrical charges. The second trench vertically extending downward can reliably isolate elements. The semiconductor device of this invention has a trench element isolation structure made of the insulating film filling the trenches. The outer edge of a portion projecting from the semiconductor substrate is covered with a thermal oxide film formed by heat-treating a polysilicon film. The structure is more resistant to etching, cleaning, and the like.

Abstract: A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.

Abstract: A method and apparatus for forming and annealing a dielectric layer. According to the present invention an active atomic species is generated in a first chamber. A dielectric layer formed on a substrate is then exposed to the active atomic species in a second chamber, wherein the second chamber is remote from the first chamber.

Abstract: A method of forming a trench for semiconductor device isolation includes the steps of making a trench at a device isolation area of a silicon wafer by etching the silicon wafer and within through a mask pattern, forming a liner oxide on the silicon wafer with the trench through thermal oxidation, forming a nitride on the liner oxide through low pressure chemical vapor deposition, and anisotropically dry-etching the nitride such that the nitride is left only at the sidewalls of the trench. A trench-filling oxide is then deposited onto the entire surface of the silicon wafer through high pressure chemical vapor deposition, and annealed. The trench-filling oxide is planarized through chemical mechanical polishing until the top surface of the trench-filling oxide is positioned slightly over the liner oxide on the silicon wafer. The silicon wafer is then wet-cleaned, and thermally oxidized such that a pad oxide is grown at the surface of the silicon wafer.

Abstract: A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.

Abstract: Before forming a trench in a silicon substrate through a patterned silicon nitride film serving as a mask, etching is executed until the main surface of the silicon substrate is exposed. Thereafter exposed side walls of a silicon dioxide film and a polysilicon film and the exposed surface of the silicon substrate are oxynitrided thereby forming an silicon oxynitride film. Thereafter the trench is formed, then a silicon dioxide film is formed on its inner wall, and thereafter the trench is filled with an insulation. In the process of forming the silicon dioxide film on the inner wall, a bird's beak is formed on the side walls of the silicon dioxide film and the polysilicon film. The silicon oxynitride film suppresses excessive growth of the bird's beak and prevents the bird's beak from formation of a depressed part. Thus, reduction of the area of an active region caused by the bird's beak is suppressed without no depression part formed on the upper end of an STI structure.

Abstract: In one aspect, the invention includes a semiconductor processing method of removing water from a material comprising silicon, oxygen and hydrogen, the method comprising maintaining the material at a temperature of at least about 100° C., more preferably at least 300° C., and at a pressure of greater than 1 atmosphere to drive water from the material. In another aspect, the invention includes a semiconductor processing method of forming SiO2 having a wet etch removal rate of less than about 700 Angstroms/minute comprising: a) forming a layer comprising Si(OH)x; b) maintaining the Si(OH)x at a temperature of at least about 300° C. and at a pressure of greater than 1 atmosphere to drive water from the Si(OH)x; and c) converting the Si(OH)x to SiO2, the SiO2 having a wet etch removal rate of less than about 700 Angstroms/minute under the conditions of a buffered oxide etch utilizing 20:1 H2O:HF, at about atmospheric pressure and at a temperature of about 30° C.

Abstract: A method for forming a shallow trench isolation structure. A substrate having a pad oxide layer and a first mask layer is provided. The first mask layer is patterned to form a first opening, a spacer is formed on the first mask layer sidewalls. The patterned first mask layer and the spacer are used as a hard mask, a portion of the pad oxide layer and the substrate are removed to form a shallow trench within the substrate. A liner layer is formed on the shallow trench surface. An insulation layer is deposited over the patterned first mask layer and within the shallow trench. Using the patterned first mask layer as a stop layer, a portion of the insulation layer above the patterned first mask layer surface is removed. Then, the patterned first mask layer and the spacer are removed. A patterned second mask layer having a second opening is formed on the substrate to expose the insulation layer and a portion of the pad oxide layer.

Abstract: Silicon-on-insulator (SOI) islands are formed in a silicon substrate. A first set of trenches is formed in the silicon substrate, leaving laterally-isolated rows of silicon between the trenches. The first set of trenches is then filled with silicon oxide. A second set of trenches is then formed in the silicon substrate at a direction orthogonal to the first set of trenches. Silicon nitride is then deposited over the sidewalls of the second set of trenches. An isotropic chemical etch is then used to fully undercut narrow the laterally-isolated rows of silicon between the second set of trenches to form evacuated regions beneath silicon islands. A subsequent oxidation step fills the evacuated regions to form the SOI islands.

Abstract: A method for fabricating a shallow trench isolation (STI) structure is provided. The method contain sequentially forming a pad oxide layer, a hard layer, and a polysilicon layer on the substrate, all of which are patterned to form a trench in the substrate to define several active areas. The hard layer usually includes silicon nitride. An insulating layer is formed over the substrate so that the trench is also filled. A CMP process is performed to polish the insulating layer. The CMP process is continuously performed until the hard layer is completely exposed. The hard layer and the pad oxide layer are sequentially removed to form the STI structure.

Abstract: A method of fabricating an SOI transistor device comprises the following steps. a silicon semiconductor structure is provided. A silicon oxide layer is formed over the silicon semiconductor structure. A silicon-on-insulator layer is formed over the oxide layer. A well is implanted in the silicon-on-insulator layer. A gate oxide layer is grown over the silicon-on-insulator layer. A polysilicon layer is deposited over the gate oxide layer. The polysilicon layer, gate oxide layer, and silicon oxide layer are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised shallow trench isolation regions (STIs). The polysilicon layer is patterned and the non-gate portions are removed polysilicon adjacent the raised STIs forming a gate conductor between the raised STIs with the gate conductor and said raised STIs having exposed sidewalls.

Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

Abstract: A SOI device, comprising: a SOI wafer having a stack structure of a silicon substrate, a buried oxide layer having a first and a second contact holes and a silicon layer; an isolation layer formed in the silicon layer to define a device formation region; a transistor including a gate formed over the device formation region of the silicon layer defined by the isolation layer, source and drain regions formed at the both side of the gate in the device formation region, and a channel region which is a portion of the device formation region between the source and drain region; a conduction layer being contacted with the buried oxide layer; an impurity region for well pick-up formed in the silicon layer to be contacted with the buried oxide layer; a first contact layer formed within the first contact hole of the buried oxide layer to electrically connect the channel region of the transistor and the conduction layer; and a second contact layer formed with the second contact hole of the buried oxide layer to electri

Abstract: A unique electrochemical process fills oxygen vacancies in dielectrics while reducing oxidation of nearby electrodes and conductors. Preferably, an electromagnetic field or bias is applied to a dielectric. The bias causes oxygen vacancies in the dielectric to migrate to the surface of the dielectric. As the oxygen vacancies migrate toward the surface, oxygen ions fill the oxygen vacancies. In one embodiment, a unique plasma treatment provides the oxygen ions that react with the oxygen vacancies. In another embodiment, a unique electrolysis treatment provides the oxygen ions that react with the oxygen vacancies.

Abstract: In fabrication of a semiconductor device, firstly an isolation trench is formed on a substrate to isolate a plurality of semiconductor elements, and then a thermal oxide film is formed on a sidewall of the trench, whereupon a silicon oxide film is formed on the substrate by chemical vapor deposition. Finally the entire substrate is annealed in a high-pressure ambient.

Abstract: A process for making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure. The SOI structure has a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer. Next, a nitride layer is deposited on top of the SOI structure. The SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region. The silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure. An epitaxial layer is grown on top of the exposed silicon substrate to form the bulk region. The nitride portion above the SOI structure is finally removed.

Abstract: A Method for forming a shallow trench isolation using HDP silicon oxynitride. A pad oxide layer is formed on a semiconductor substrate having an active area and an isolation area and a barc layer is formed over the pad oxide layer. The barc layer, the pad oxide layer, and the semiconductor substrate are patterned to form a trench having rounded corners in the isolation area. A liner oxide layer is formed over the semiconductor substrate, and a gap fill layer is formed on the liner oxide layer. An important feature of the invention is that the gap fill layer is composed of silicon oxynitride formed using a high density plasma chemical vapor deposition process. A portion of the gap fill layer over the active area can be removed using a reverse trench mask etch, and the gap fill layer is further planarized with a chemical mechanical polishing process using the liner oxide layer as chemical mechanical polishing stop.

Abstract: A method of forming a trench for semiconductor device isolation includes the steps of making a trench at a device isolation area of a silicon wafer overlaid with a pad oxide and a nitride through photolithography and etching, forming a liner oxide at an inner wall of the trench, filling the trench through depositing an insulating layer onto the entire surface of the silicon wafer, densifying the insulating layer, and planarizing the densified insulating layer such that the insulating layer is left only at the inside of the trench.

Abstract: A method of forming a shallow trench isolation (STI) structure. A dielectric layer is formed over the interior surface of a shallow trench. Spacers are formed on the sidewalls of the shallow trench such that a portion of the dielectric layer at the bottom of the shallow trench is exposed. When a silicon oxide layer is subsequently deposited into the shallow trench using ozone and tetra-ethyl-ortho-silicate as reactive gases in a chemical vapor deposition, the silicon oxide layer is deposited faster from the dielectric layer than from the spacers.

Abstract: A process for fabricating a tapered trench on a silicon substrate. The process comprises the steps of forming an initial trench in the substrate and implanting nitrogen ions on the initial trench side walls. More nitrogen ions are implanted adjacent the exposed surface of the substrate than adjacent the trench bottom. Finally, the initial trench side walls are oxidized to create the tapered shape.

Abstract: The present invention is directed to a method of fabricating a dual gate structure for use in FET devices wherein the dual gate structure comprises a bottom gate that is substantially a mirror image of the top gate. The method utilizes a shallow trench isolation process for the purpose of planarization and gate alignment. Also disclosed is a dual gate structure which is fabricated utilizing the method of the present invention.

Abstract: A BiCMOS integrated circuit is formed with CMOS transistors on an SOI substrate in a silicon layer having a standard thickness of 0.1 &mgr;m to 0.2 &mgr;m and with Bipolar SiGe transistors formed in an epitaxial layer nominally 0.5 &mgr;m thick. The CMOS transistors are formed first with standard processing, then covered with an insulating film. The insulating film is stripped in the bipolar areas and an epitaxial SiGe layer is deposited on the Si substrate. The bipolar transistors are formed using the SiGe epi layer for the base and having an encapsulated structure for device isolation using shallow isolation trenches and the buried oxide.

Abstract: An object is to provide a semiconductor substrate processing method and a semiconductor substrate that prevent formation of particles from the edge part of the substrate. Silicon ions are implanted into the edge part of an SOI substrate (10) in the direction of radiuses of the SOI substrate (10) to bring a buried oxide film (2) in the edge part of the SOI substrate (10) into a silicon-rich state. Thus an SOI substrate (100) is provided, where the buried oxide film (2) has substantially been eliminated in the edge part.

Abstract: A process of producing controllable thicknesses of silicon-on-insulator (SOI) for fully-depleted double-gate applications is provided. The process comprises depositing an oxide layer on a silicon wafer, depositing a nitride layer of a controlled thickness on the oxide layer, etching the nitride layer to open a first trench of controlled thickness, opening a second trench down to the silicon substrate, growing epitaxial silicon using epitaxial lateral overgrowth (ELO) to fill the second trench and grow sideways to fill the first trench, perform planarization of ELO silicon using the nitride layer as a chemical-mechanical polishing (CMP) stop layer, and fabricating a SOI device in the first trench.

Abstract: A method of forming shallow trench isolation that reduces junction leakage at the boundary of shallow trench isolation and contact metallurgy of adjacent transistors and that avoids a reduction of carrier concentration in the source and drain region of transistors adjacent to the shallow trench isolation is described. The method to form a shallow trench isolation feature begins by providing a semiconductor substrate having a surface coated with at least one layer of an insulating material and a plurality of shallow trenches formed in the surface of the semiconductor substrate. A nitrogen doped insulating layer is then grown on the internal surfaces or sidewalls of the shallow trenches.

Abstract: A semiconductor device and a method for fabricating the same are disclosed, in which floating body effect is reduced by applying a bias to a body in an SOI MOSFET. The semiconductor device includes first and second impurity ion implanting layers of a conductivity type formed in a semiconductor substrate having a buried oxide film and surface silicon layers thereon, first and second transistors of a conductivity type respectively formed on the first and second impurity ion implanting layers, having source/drain regions and a gate, trenches formed between the first and second transistors, single crystal silicon layers connected to any one of the source/drain regions of the respective transistors and the first and second impurity ion implanting layers at sides of the trenches, and carrier exhausting electrodes connected to the first and second impurity ion implanting layers at one sides of the respective transistors, for exhausting carrier generated by ionization impact in the respective transistors.

Abstract: A process for making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure. The SOI structure has a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer. Next, a nitride layer is deposited on top of the SOI structure. The SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region. The silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure. An epitaxial layer is grown in top of the exposed silicon substrate to form the bulk region. The nitride portion above the SOI structure is finally removed.

Abstract: A method of forming a semiconductor substrate (and the resulting structure), includes etching a groove into a bulk silicon substrate, forming a dielectric in the groove and planarizing the silicon substrate to form at least one patterned dielectric island in the silicon substrate, forming an amorphous silicon (or SiGe) layer on exposed portions of the silicon substrate and the at least one dielectric island, crystallizing the amorphous silicon (or SiGe) layer using the exposed silicon substrate as a seed, the silicon substrate having direct contact with the formed silicon layer serving as a crystal growth seeding for the crystallization process, and converting the silicon (or SiGe) layer to crystallized silicon, and performing a shallow trench isolation (STI) process, to form oxide isolations between devices.

Abstract: Silicon-on-insulator (SOI) islands are formed in a silicon substrate. A first set of trenches formed in the silicon substrate, leaving laterally-isolated rows of silicon between the trenches. The first set of trenches is then filled with silicon oxide. A second set of trenches is then formed in the silicon substrate at a direction orthogonal to the first set of trenches. Silicon nitride is then deposited over the sidewalls of the second set of trenches. An isotropic chemical etch is then used to fully undercut narrow the laterally-isolated rows of silicon between the second set of trenches to form evacuated regions beneath silicon islands. A subsequent oxidation step fills the evacuated regions to form de SOI islands.

Abstract: The present invention is directed to a method of fabricating a dual gate structure for use in FET devices wherein the dual gate structure comprises a bottom gate that is substantially a mirror image of the top gate. The method utilizes a shallow trench isolation process for the purpose of planarization and gate alignment. Also disclosed is a dual gate structure which is fabricated utilizing the method of the present invention.

Abstract: Silicon-on-insulator (SOI) islands are formed in a silicon substrate. A first set of trenches is formed in the silicon substrate, leaving laterally-isolated rows of silicon between the trenches. The first set of trenches is then filled with silicon oxide. A second set of trenches is then formed in the silicon substrate at a direction orthogonal to the first set of trenches. Silicon nitride is then deposited over the sidewalls of the second set of trenches. An isotropic chemical etch is then used to fully undercut narrow the laterally-isolated rows of silicon between the second set of trenches to form evacuated regions beneath silicon islands. A subsequent oxidation step fills the evacuated regions to form the SOI islands.

Abstract: A method of forming an insulated well in an upper portion of a silicon substrate, including the steps of providing a structure of silicon-on-insulator type including a silicon substrate, an insulating layer, and a thin single-crystal silicon layer; removing the insulating layer and the thin silicon layer outside locations where the insulated well is desired to be formed; growing an epitaxial layer; performing a planarization; and making a vertical insulating wall above the periphery of the maintained portion of the thin insulating layer.

Abstract: A method for stabilizing an SOI semiconductor device which comprises the steps of: providing an SOI semiconductor device constituted of an SOI substrate including a support substrate, a buried insulating film formed on the support substrate and a surface semiconductor layer formed on the buried insulating film, source/drain regions formed in the surface semiconductor layer and a gate electrode formed on the surface semiconductor layer between the source/drain regions with intervention of a gate insulating film; and applying an electric stress between the support substrate and one of the source/drain regions so that a back channel is formed in a side of the surface semiconductor layer to the buried insulating film, thereby to introduce a capturing potential at least near an interface between said one of the source/drain regions and the surface semiconductor layer in the buried insulating film side.

Abstract: A method for planarizing a polycrystalline silicon layer deposited on a trench, which is formed on a semiconductor substrate, comprises the following steps. First, a polycrystalline silicon layer with an enough thickness is deposited on the surface of the semiconductor substrate to overfill the trench. At least one dimple is undesirably developed on the polycrystalline silicon layer during the polycrystalline silicon deposition. Then, an oxide layer with an enough thickness is formed on the polycrystalline silicon layer to overfill the at least one dimple. Next, the polycrystalline silicon layer is partially oxidized so as to transform the upper portion thereof into a polysilicon oxide layer. As a result of a non-uniform distribution of the oxidization rate, the bottom surface of the polysilicon oxide layer, i.e. the interface between the polysilicon oxide layer and the non-oxidized portion of the polycrystalline silicon layer, is substantially planar.

Abstract: Using sub-micron technology, silicon on insulator (SOI) rows and islands are formed in a silicon substrate. Trenches are directionally-etched in the silicon substrate, leaving rows of silicon between the trenches. Silicon nitride is then deposited over the trenches, extending partly down the sides of the trenches. An isotropic chemical etch is then used to partially undercut narrow rows of silicon in the substrate. A subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas. Devices, such as transistors for CMOS and DRAMs, are then formed in active areas, wherein the active areas are defined on the silicon rows by LOCal Oxidation of Silicon (LOCOS).

Abstract: A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material to the side of an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A method for making the interconnect structure maintains a preexisting geometry of the active region during etching of an interconnect structure hole in which the interconnect structure is formed and saves process steps. Under the method, a region of insulating material is formed immediately adjacent the active region location. A nitride layer is formed over the active region and protects the active region while an interconnect structure hole is etched partially into the region of insulating material adjacent the active region location with an etching process that is selective to the nitride layer.

Abstract: A vertical type power MOSFET made of silicon carbide includes a surface channel layer doped with nitrogen as dopant with a concentration equal to or less than 1.times.10.sup.15 cm.sup.-3. Accordingly, when a gate oxide film is formed on the surface channel layer, an amount of silicon nitride produced in the gate oxide film and at the interface between the gate oxide film and the surface channel layer becomes extremely small. As a result, carrier traps are prevented from being produced by silicon nitride, resulting in stable FET characteristics and high reliability to the gate oxide film.

Abstract: A method is described for filling trenches with dielectric for shallow trench isolation which completely fills the trench and avoids problems due to dishing at the top of the trench. A trench is formed in a substrate having a second dielectric material formed thereon. The trench is lined with a third dielectric material. Sub atmospheric chemical vapor deposition, SACVD, of tetra-ethyl-ortho-silicate and ozone is used to grow a fourth dielectric on the surface of the second dielectric material and in the trench lined with the third dielectric material. The growth rate of fourth dielectric on the third dielectric is greater than the growth rate of the fourth dielectric on the second dielectric using SACVD of tetra-ethyl-ortho-silicate and ozone. The difference in growth rate assures that the trench is completely filled with fourth dielectric even for relatively thin layers of fourth dielectric grown on the second dielectric.

Abstract: The present invention proposes a method for fabricating shallow trench regions for isolation. An oxide hard mask is utilized for the silicon etching. A silicon oxynitride film is created near the trench corners to prevent the gate wrap-around and corner parasitic leakage. Forming trench regions on a semiconductor substrate by using a thick pad oxide layer as an etching hard mask. A thermal oxide film is grown to recover the etching damages. An undoped LPCVD amorphous silicon film is then deposited on entire surface of the semiconductor substrate. A high temperature/pressure oxidation process follows to convert the undoped amorphous silicon film into thermal oxide. A thick CVD oxide layer is deposited on the semiconductor substrate. The oxide film outside the trench regions is removed by using a CMP process. Finally, the MOS devices are fabricated on the semiconductor substrate by standard processes, and thus complete the present invention.

Abstract: A method for effectively generating limited trench width isolation structures without incurring the susceptibility to dishing problems to produce high quality ICs employs a computer to generate data representing a trench isolation mask capable of being used to etch a limited trench width isolation structure about the perimeter of active region layers, polygate layers, and Local Interconnect (LI) layers. Once the various layers are defined using data on the computer and configured such that chip real estate is maximized, then the boundaries are combined using, for example, logical OR operators to produce data representing an overall composite layer. Once the data representing the composite layer is determined, the data is expanded evenly outward in all horizontal directions by a predetermined amount, .lambda., to produce data representing a preliminary expanded region.

Abstract: A field oxide film which is fine and having smaller upheaval of a bird's head is formed, so as to improve electrical characteristic of a conductive layer formed with end portions positioned on the field oxide film. A planarizing silicon film is formed on a silicon nitride film and a thermal oxide film, so as to planarize a concave generated between the thermal oxide film and a silicon nitride film. The planarizing silicon film is thermally oxidized, so as to form a planarizing thermal oxide film integrated with the thermal oxide film. Thereafter, the planarizing thermal oxide film is etched back to form the field oxide film, and the silicon nitride film and a polycrystalline silicon film are removed. Thereafter, the conductive layer with end portions positioned on the field oxide film is formed.

Abstract: A recess-free buffer layer is formed on a semiconductor substrate having island structures formed thereon. A first buffer layer is formed over the substrate and the island structures. A first reflow process is then performed for reflowing the first buffer layer into spaces between the island structures. A portion of the first buffer layer located outside the spaces is removed. A second buffer layer is formed over the first buffer layer and the island structures. The method can further include a step of performing a second thermal soft-bake process to the second buffer layer. The second buffer layer can also be patterned after the soft-bake process.

Abstract: A method for fabricating shallow trench isolation stricture wherein a surface oxide layer and a polycrystalline silicon buffer layer are formed on a semiconductor body. Openings are formed through the layers and into the body that constitute trenches. A lining oxide layer is formed on the trench and buffer layer surfaces. A thick oxide layer is deposited on the body to fill the trench, and the layer planarized by chemical-mechanical polishing. The exposed portions of the buffer layer are removed and the horizontal surface oxide layer portions removed by anisotropic etching.

Abstract: A method for dissipating accumulated charge in a trench isolation structure, comprising the steps of: etching the trench region into a silicon substrate; forming an insulating region on the sidewalls of the trench and the base of the trench; removing the insulator at the bottom of the trench; and filling the trench with polysilicon, the polysilicon engaging the second layer of silicon below the insulator layer.

Abstract: A semiconductor process in which a first nitrogen bearing oxide is formed on an upper surface of a semiconductor substrate. A silicon nitride layer is then formed on the nitrogen bearing oxide. The first oxide and the silicon nitride layer are then patterned to expose an upper surface of the substrate over a trench region of the substrate. An isolation trench is then etched into the trench region of the substrate and a nitrogen bearing liner oxide is then formed on sidewalls and a floor of the trench. An isolation dielectric is then formed within the trench and, thereafter, the silicon nitride layer is removed from the wafer. A suitable thickness of the first nitrogen bearing oxide and of the liner oxide is in the range of approximately 30 to 100 angstroms. A consumption of adjacent active regions caused by the thermal oxidation process is preferably less than approximately 50 angstroms.