Abstract: The present invention provides a semiconductor device in which a bottom-gate TFT or an inverted stagger TFT arranged in each circuit is suitably constructed in conformity with the functionality of the respective circuits, thereby attaining an improvement in the operating efficiency and reliability of the semiconductor device. In the structure, LDD regions in a pixel TFT are arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in an N-channel TFT of a drive circuit is arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in a P-channel TFT of the drive circuit is arranged so as to overlap with a channel protection insulating film and to overlap with the gate electrode.

Abstract: The present invention relates to a method of fabricating a liquid crystal display panel that involves patterning a silicon film crystallized by sequential lateral solidification. The method comprises the steps of preparing a silicon film, crystallizing the silicon film by growing silicon grains on a slant with respect to a horizontal direction of the silicon film, and forming a driver and a pixel part using the crystallized silicon film wherein the driver and pixel part comprise devices having channels arranged in horizontal and perpendicular directions relative to the silicon film. The crystallized silicon film has uniform grain boundaries in the channels of the devices, thereby improving the products by providing uniform electrical characteristics of devices that comprise a driver and a pixel part of an LCD panel.

Abstract: A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; epitaxially growing a silicon cap on the Si1−XGeX layer; implanting hydrogen ions through the Si1−XGeX layer to a depth of between about 3 nm to 100 nm below the Si1−XGeX/Si interface; amorphizing the Si1−XGeX layer to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.

Abstract: A process to fabricate a thin film transistor using an intrinsic polycrystalline silicon film, by a method of: preparing a semiconductor assembly; forming an insulation layer on a substrate; forming a first amorphous silicon layer on said insulation layer; forming silicon nucleation sites on said first amorphous silicon layer; converting said first amorphous silicon layer into hemispherical grained silicon, said hemispherical grained silicon being formed about said silicon nucleation sites; forming a second amorphous silicon layer covering said hemispherical grained silicon; annealing said second amorphous silicon layer to convert said second amorphous silicon layer into a grained silicon film, said grained silicon film being formed about said hemispherical grained silicon and having a dimension of approximately 0.1 microns to 0.

Abstract: A termination structure and reduced mask process for its manufacture for either a FRED device or any power semiconductor device comprises at least two concentric diffusion guard rings and two spaced silicon dioxide rings used in the definition of the two guard rings. A first metal ring overlies and contacts the outermost diffusion. A second metal ring which acts as a field plate contacts the second diffusion and overlaps the outermost oxide ring. A third metal ring, which acts as a field plate, is a continuous portion of the active area top contact and overlaps the second oxide ring. The termination is useful for high voltage (of the order of 1200 volt) devices. The rings are segments of a common aluminum or Palladium contact layer.

Abstract: A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; epitaxially growing a silicon cap on the Si1−XGeX layer; implanting hydrogen ions through the Si1−XGeX layer to a depth of between about 3 nm to 100 nm below the Si1−XGeX/Si interface; amorphizing the Si1−XGeX layer to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.

Abstract: First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Next, an amorphous silicon layer is deposited, an annealing process is executed to form inter-layer reaction layers on the drain electrode, the gate pad and the data pad, which are exposed through the contact holes. Then, the amorphous silicon layer is removed.

Abstract: A film contains first and second metal or metal alloy layers separated by a crosslinked polymeric spacing layer whose thicknesses are such that the film is visible light-transmissive and infrared reflective. The film can be joined or laminated into glazing (especially non-planar vehicular safety glazing) with reduced likelihood that the metal or metal alloy layers will be damaged or distorted.

Abstract: Various methods are provided of forming capacitor electrodes for integrated circuit memory cells in which out-diffusion of dopant from doped silicon layers is controlled by deposition of barrier layers, such as layers of undoped silicon and/or oxide. In one aspect, a method of forming hemispherical grain silicon on a substrate is provided that includes forming a first doped silicon layer on the substrate and a first barrier layer on the doped silicon layer. A hemispherical grain polysilicon source layer is formed on the first barrier layer and a hemispherical grain silicon layer on the hemispherical grain polysilicon source layer. By controlling out-diffusion of dopant, HSG grain size, density and uniformity, as well as DRAM memory cell capacitance, may be enhanced, while at the same time maintaining reactor throughput.

Abstract: A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate. Inert dopants are then implanted within the substrate to form amorphized source/drain regions in the substrate extending to a first depth significantly greater than the intended junction depth. The amorphized source/drain regions are implanted with source/drain dopants such that the dopants extend into the substrate to a second depth less than the first depth, above and spaced apart from the end-of-range defect region created at the first depth by the amorphization process. Laser thermal annealing recrystallizes the amorphous regions, activates the source/drain regions and forms source/drain junctions.

Abstract: A first layer made of polysilicon is formed on the surface of an underlying substrate. The surface of the first layer is exposed to an environment which etches silicon oxide. If the surface of the first layer is covered with a silicon oxide film, the silicon oxide film is removed. An energy is supplied to the first layer, the energy allowing silicon crystal to re-grow. Solid phase growth of silicon occurs in the first layer to planarize the surface thereof. A polysilicon film having small root mean square of roughness can be formed.

Abstract: A method for forming a semiconductor film capable allowing easy cleaning of the processing equipment and capable of forming an epitaxial film at low temperatures as well as a manufacturing method for semiconductor devices utilizing this forming method is needed for achieving selective crystalline growth on semiconductor film. The forming method comprises a process for forming a mask having an aperture exposing a substrate surface on substrate, and a process for forming a semiconductor film by selective crystalline growth on a semiconductor piece by means of catalytic chemical vapor deposition on a substrate surface exposed by an aperture on a mask; as well as a manufacturing method for semiconductor devices utilizing the semiconductor film forming method.

Abstract: A method for depositing doped polycrystalline or amorphous silicon film. The method includes placing a substrate onto a susceptor. The susceptor includes a body having a resistive heater therein and a thermocouple in physical contact with the resistive heater. The susceptor is located in the process chamber such that the process chamber has a top portion above the susceptor and a bottom portion below the susceptor. The method further includes heating the susceptor. The method further includes providing a process gas mix into the process chamber through a shower head located on the susceptor. The process gas mix includes a silicon source gas, a dopant gas, and a carrier gas. The carrier gas includes nitrogen. The method further includes forming the doped silicon film from the silicon source gas.

Abstract: System and methods for processing an amorphous silicon thin film sample into a single or polycrystalline silicon thin film are disclosed.

Abstract: There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, different potentials are applied to the two counter electrodes, respectively and inversion driving is carried out each other. Since a potential of an image signal can be made low by doing so, it is possible to lower a voltage necessary for operation of a driver circuit. As a result, it is possible to realize improvement of reliability of an element such as a TFT and reduction of consumed electric power. Moreover, since it is possible to lower a voltage of a timing pulse supplied by the driver circuit, a booster circuit can be omitted, and reduction of an area of the driver circuit can be realized.

Abstract: The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper surface. A second semiconductor substrate is provided which comprises a monocrystalline material having a damage region therein. The second semiconductor substrate is bonded to the silicon-containing structures of the first substrate at the upper surface. The monocrystalline material is then cleaved along the damage region. The invention also encompasses a semiconductor construction comprising a first substrate having silicon-containing structures separated from one another by an insulative material, and a second substrate comprising a monocrystalline material.

Abstract: Disclosed is an ISFET comprising a H+-sensing membrane consisting of RF-sputtering a-WO3. The a-WO3/SiO2-gate ISFET of the present invention is very sensitive in aqueous solution, and particularly in acidic aqueous solution. The sensitivity of the present ISFET ranges from 50 to 58 mV/pH. In addition, the disclosed ISFET has high linearity. Accordingly, the disclosed ISFET can be used to detect effluent.

Abstract: Disclosed is a method for SOI device, and particularly to a method for fabricating a full depletion type SOI device capable of minimizing a change in a threshold voltage of transistor according to a change in a thickness of semiconductor layer.

Abstract: A method for an efficient extended pulse laser annealing process is provided. The method comprises: supplying a substrate with a thickness; selecting an energy density; selecting an extended pulse duration; laser annealing a substrate region; in response to cooling the substrate region, crystallizing the substrate region; and, efficiently extending the lateral growth of crystals in the substrate region. When the substrate has a thickness of approximately 300 Å, the energy density is selected to be in the range of 400 to 500 millijoules pre square centimeter (mJ/cm2). The pulse duration is selected to be in the range between 70 and 120 nanoseconds (ns). More preferably, the pulse duration is selected to be in the range between 90 and 120 ns. Most preferable, the pulse duration is approximately 100 ns. Then, efficiently extending the lateral growth of crystals in the substrate region includes laterally growing crystals at a rate of approximately 0.029 microns per nanosecond.

Abstract: In a thin film transistor, a metallic element promoting crystallization of an amorphous silicon film is effectively removed and the productivity is improved. By using a silicon film containing an element belonging to the group 15 such as phosphorus through contact holes reaching a source region and a drain region, a metallic element promoting crystallization of an amorphous silicon film can be effectively removed or decreased and the productivity can be improved.

Abstract: A thermal type infrared sensor and a method of manufacturing the same that have a high degree of freedom of structure and a low cost. An infrared ray detecting portion and a support leg are formed above flat plate-shape void formed inside of a semiconductor substrate, and a processing circuit section of a signal from a detecting portion is fabricated on the semiconductor substrate. Because the structure of the processing circuit section is not influenced by a substrate structure, characteristics are improved. Furthermore, the structure is simplified, and it is possible to reduce a manufacturing cost.

Abstract: The present invention describes a method and apparatus for forming a uniform silicon containing film in a single wafer reactor. According to the present invention, a silicon containing film is deposited in a resistively heated single wafer chamber utilizing a process gas having a silicon source gas and which provides an activation energy less than 0.5 eV at a temperature between 750° C.-550° C.

Abstract: The photovoltaic element of the present invention is a photovoltaic element comprised of a semiconductor-junctioned element, characterized in that the element includes a first electrically conductive type semiconductor layer, a non-crystalline i type semiconductor layer, a microcrystalline i type semiconductor layer and a microcrystalline second electrically conductive type semiconductor layer and is pin-junctioned, and a method of and an apparatus for manufacturing the same are characterized by efficiently and continuously mass-producing the photovoltaic element having an excellent current-voltage characteristic and excellent photoelectric conversion efficiency.

Abstract: Systems and methods for epitaxial deposition. The reactor includes a hot wall process cavity enclosed by a heater system, a thermal insulation system, and chamber walls. The walls of the process cavity may comprises a material having a substantially similar coefficient thermal expansion as the semiconductor substrate, such as quartz and silicon carbide, and may include an isothermal or near isothermal cavity that may be heated to temperatures as high as 1200 degrees C. Process gases may be injected through a plurality of ports, and are capable of achieving a fine level of distribution control of the gas components, including the film source gas, dopant source gas, and carrier gas. The gas supply system includes additional methods of delivering gas to the process cavity, such as through temperature measurement devices, and through a showerhead. In one embodiment of the present invention, the system is capable of utilizing silane as a silicon source gas.

Abstract: An improved method and system for laser doping a semiconductor material is described. In the invention, phosphorous nitride is used as a dopant source. The phosphorous nitride is brought into close proximity with a region of the semiconductor to be doped. A pulse of laser light decomposes the phosphorous nitride and briefly melts the region of semiconductor to be doped to allow incorporation of dopant atoms from the phosphorous nitride into the semiconductor.

Abstract: The present invention discloses a polycrystalline silicon thin film transistor connected to a gate line and a data line that includes a source electrode contacting the data line; a gate electrode contacting the gate line; a drain electrode spaced apart from the source electrode; a polysilicon layer positioned between and contacting the source and the drain electrodes, and acting as a channel area in which electrons flow; at least one metal layer positioned near the polysilicon layer and parallel to a flow direction of the electrons; and a buffer layer interposed between the metal layer and the polysilicon layer.

Abstract: There is provided a semiconductor device including a semiconductor substrate and a conductive layer above the semiconductor substrate, wherein the conductive layer contains copper, a surface region of the conductive layer contains at least one of C—H bonds and C—C bonds, and a total amount of C atoms forming the C—H bonds and C atoms forming the C—C bonds in the surface region is 30 atomic % or more of a whole amount of elements in the surface region.

Abstract: A process for bonding oxide-free silicon substrate pairs and other substrates at low temperature. This process involves modifying the surface of the silicon wafers to create defect regions, for example by plasma-treating the surface to be bonded with a or boron-containing plasmas such as a B2H6 plasma. The surface defect regions may also be created by ion implantation, preferably using boron. The surfaces may also be amorphized. The treated surfaces are placed together, thus forming an attached pair at room temperature in ambient air. The bonding energy reaches approximately 400 mJ/M2 at room temperature, 900 mJ/M2 at 150° C., and 1800 mJ/M2 at 250° C. The bulk silicon fracture energy of 2500 mJ/m2 was achieved after annealing at 350-400° C. The release of hydrogen from B—H complexes and the subsequent absorption of the hydrogen by the plasma induced modified layers on the bonding surfaces at low temperature is most likely responsible for the enhanced bonding energy.

Abstract: Method and apparatus for depositing an amorphous silicon film on a substrate using a high density plasma chemical vapor deposition (HDP-CVD) technique is provided. The method generally comprises positioning a substrate in a processing chamber, introducing an inert gas into the processing chamber, introducing a silicon source gas into the processing chamber generating a high density plasma, and depositing the amorphous silicon film. The amorphous silicon film is deposited at a substrate temperature 500° C. or less. The amorphous silicon film may then be annealed to improve film properties.

Abstract: A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

Abstract: A method of fabricating a semiconductor device capable of improving productivity by efficiently polycrystallizing an amorphous silicon film is obtained. This method of fabricating a semiconductor device comprises steps of forming an amorphous film on a substrate, forming a conductor film on the substrate, arranging the substrate so that the surface of the conductor film is substantially parallel to an electric field in a waveguide and irradiating the conductor film with an electromagnetic wave thereby making the conductor film generate heat and crystallizing the amorphous film with the heat. Thus, the substrate is arranged to be substantially parallel to the electric field in the waveguide, whereby the absorptivity of the conductor film for the electromagnetic wave is improved and hence the conductor film can be efficiently heated. Thus, crystallization is performed in a short time, thereby improving productivity.

Abstract: Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed.

Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.

Abstract: Semiconductor crystal grains are formed by metal-induced lateral crystallisation. The positions of the grain boundaries normal to the crystallisation direction are controlled, to position the grains correctly for subsequent formation of electronic devices within them. In a first technique, the grains are positioned by depositing the metal in short strips which each induce the crystallisation of a single corresponding grain. In a second technique, the grains are positioned by pre-patterning the amorphous silicon which is used to form the grains. Electronic circuit elements can be formed in each grain. The resultant structure can be used in a microelectronic mechanical system. Several grains can be formed successively and circuit elements formed in each layer to form a three-dimensional integrated circuit.

Abstract: There is disclosed a semiconductor device having: a semiconductor substrate; a first gate electrode constructed of a multi-layered stack member provided in a memory region, formed with memory cells, of a surface area of the semiconductor substrate so that the first gate electrode is insulated by a first insulating layer from the semiconductor substrate; and a second gate electrode provided in a logic region, formed with a logic circuit for controlling at least the memory cells, of the surface area of the semiconductor substrate so that the second gate electrode is insulated by a second insulating layer from the semiconductor substrate, wherein said layer, brought into contact with the first insulating layer, of the first gate electrode and the layer, brought into contact with the second insulating layer, of the second gate electrode, are composed of materials different from each other.

Abstract: A solution containing a cyclic silane compound, which does not contain carbon, and/or a silane compound modified by boron or phosphorus is applied onto a substrate and a silicon precursor film is formed, and the film is then transformed into semiconductor silicon by heat and/or light treatment. Thereby, it is possible to easily produce a silicon film having satisfactory characteristics as an electronic material at low costs, differing from the vacuum process, such as by CVD methods.

Abstract: In a semiconductor thin-film formation process comprising feeding a semiconductor thin-film material gas into a discharge space, and applying a high-frequency power thereto to cause plasma to take place and decompose the material gas to form an amorphous semiconductor thin film on a desired substrate, the high-frequency power is applied changing its power density continuously or stepwise from a high power density to a low power density and thereafter again changing the power density continuously or stepwise from a low power density to a high power density, to form a semiconductor thin film made different in film quality in the direction of layer thickness while retaining the same conductivity type. This process enable formation of high-quality semiconductor thin films by plasma CVD.

Abstract: A method of forming an insulation layer on a semiconductor substrate includes modifying a surface of a semiconductor substrate with a metal or a metal-containing compound and oxygen to form an insulation layer on the surface of the semiconductor substrate, wherein the insulation layer comprises the metal or metal-containing compound, oxygen, and silicon such that the dielectric constant of the insulation layer is greater relative to an insulation layer formed of silicon dioxide, and wherein the insulation layer comprises metal-oxygen-silicon bonds.

Abstract: In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material.

Abstract: A thin film deposition method uses a vacuum confinement cup that employs a dense hot filament and multiple gas inlets. At least one reactant gas is introduced into the confinement cup both near and spaced apart from the heated filament. An electrode inside the confinement cup is used to generate plasma for film deposition. The method is used to deposit advanced thin films (such as silicon based thin films) at a high quality and at a high deposition rate.

Abstract: Work function control layers are provided in in-laid, metal gate electrode, Si-based MOS transistors and CMOS devices by a process which avoids deleterious dopant implantation processing resulting in damage to the thin gate insulator layer and undesirable doping of the underlying channel region. According to the invention, an amorphous Si layer is formed over the thin gate insulator layer by a low energy deposition process which does not adversely affect the gate insulator layer and subsequently doped by means of another low energy process, e.g., low sheath voltage plasma doping, which does not damage the gate insulator layer or dope the underlying channel region of the Si-based substrate. Subsequent thermal processing during device manufacture results in activation of the dopant species and conversion of the a-Si layer to a doped polycrystalline Si layer of substantially increased electrical conductivity.

Abstract: In but one aspect of the invention, a method of depositing polysilicon comprises providing a substrate within a chemical vapor deposition reactor, with the substrate having an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the crystalline region and not the amorphous region. In another aspect a method of fabricating a field effect transistor on a substrate comprises forming a gate dielectric layer and a gate over semiconductive material. Doped source/drain regions are formed within semiconductive material laterally proximate the gate. Substantially amorphous insulating material is formed over and laterally proximate the gate. The substrate is provided within a chemical vapor deposition reactor.

Abstract: A semiconductor structure with selective doping includes a monocrystalline silicon substrate, an amorphous oxide material overlying the monocrystalline silicon substrate, a monocrystalline perovskite oxide material overlying the amorphous oxide material, at least one monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material, and a transistor in the at least one monocrystalline compound semiconductor material and including active regions having different conductivity levels under substantially identical bias conditions.

Abstract: Contamination of an interface of respective films constituting a TFT due to an contaminant impurity in a clean room atmosphere becomes a great factor to lower the reliability of the TFT. Besides, when an impurity is added to a crystalline semiconductor film, its crystal structure is broken. By using an apparatus for manufacturing a semiconductor device including a plurality of treatment chambers, a treatment can be made without being exposed to a clean room atmosphere in an interval between respective treatment steps, and it becomes possible to keep the interface of the respective films constituting the TFT clean. Besides, by carrying out crystallization after an impurity is added to an amorphous semiconductor film, the breakdown of the crystal structure of the crystalline semiconductor film is prevented.

Abstract: A substrate processing apparatus includes a CVD (chemical vapor deposition) processing chamber and a RTO (rapid thermal oxidation) processing chamber. In the CVD processing chamber, a film growing process, in which thin amorphous film is deposited on a substrate, and an impurity removing process, in which specific impurities included in the grown amorphous film are removed, are repeatedly performed multiple times to provide an impurity removed amorphous film with good step coverage. Thus treated amorphous film on the substrate is then crystallized in the RTO process chamber to provide a crystalline film.

Abstract: A method is provided to optimize the channel characteristics of thin film transistors (TFTs) on polysilicon films. The method is well suited to the production of TFTs for use as drivers on liquid crystal display devices. Regions of polycrystalline silicon can be formed with different predominant crystal orientations. These crystal orientations can be selected to match the desired TFT channel orientations for different areas of the device. The crystal orientations are selected by rotating a mask pattern to a different orientation for each desired crystal orientation. The mask is used in connection with lateral crystallization ELA processes to crystallize deposited amorphous silicon films.

Abstract: Disclosed herein is a method of forming a microcrystalline silicon film by using a raw gas containing at least a silicon compound by a high-frequency plasma CVD method, wherein the formation of the film is conducted in such a manner that the residence time, &tgr; (ms) of the raw gas in a film deposition chamber, which is defined as &tgr; (ms)=78.9×V×P/M, in which V is a volume (cm3) of the deposition chamber, P is a deposition pressure (Torr), and M is a total flow rate (sccm) of the raw gas, satisfies &tgr;<40. The method permits the formation of a good-quality microcrystalline silicon film at low cost.

Abstract: A semiconductor structure and a scheme for forming a layer of amorphous material on a semiconductor substrate are provided. In accordance with one embodiment of the present invention, a semiconductor structure is provided comprising an amorphous alloy formed over at least a portion of a semiconductor substrate. The amorphous alloy comprises amorphous aluminum nitride (AlN) and amorphous gallium nitride (GaN). The amorphous alloy may be characterized by the following formula: AlxGa1−xN where x is a value greater than zero and less than one. The amorphous alloy may further comprise indium nitride. Relative proportions of aluminum and gallium in the amorphous aluminum gallium nitride alloy are controlled to engineer the band gap of the amorphous alloy.

Abstract: A method of fabricating device quality, thin-film a-Si:H for use as semiconductor material in photovoltaic and other devices, comprising in any order; positioning a substrate in a vacuum chamber adjacent a plurality of heatable filaments with a spacing distance L between the substrate and the filaments; heating the filaments to a temperature that is high enough to obtain complete decomposition of silicohydride molecules that impinge said filaments into Si and H atomic species; providing a flow of silicohydride gas, or a mixture of silicohydride gas containing Si and H, in said vacuum chamber while maintaining a pressure P of said gas in said chamber, which, in combination with said spacing distance L, provides a P×L product in a range of 10-300 mT-cm to ensure that most of the Si atomic species react with silicohydride molecules in the gas before reaching the substrate, to thereby grow a a-Si:H film at a rate of at least 50 Å/sec.

Abstract: A laser annealing apparatus is provided in which laser light is irradiated onto an amorphous semiconductor layer placed inside an annealing chamber (100) through a chamber window (120), thereby poly-crystallizing the amorphous semiconductor film. Inside the annealing chamber 100 a low degree vacuum (about 1.3×103 Pa to about 1.3 Pa) is maintained at a room temperature. An inert gas such as nitrogen, hydrogen, or argon is introduced into the atmosphere while maintaining the low degree vacuum. As a result, the surface smoothness of the polycrystalline semiconductor layer is comparable to that resulting from high degree vacuum annealing, while, unlike high degree vacuum annealing, there is less contamination of the chamber window (120) and productivity is improved.