Abstract: An integrated circuit (IC) includes a strained-silicon layer formed by deposition of amorphous silicon onto either a region of a semiconductor layer that has been implanted with ions to create a larger spacing between atoms in a crystalline lattice of the semiconductor layer or a silicon-ion layer that has been epitaxially grown on the semiconductor layer to have an increased spacing between atoms in the silicon-ion layer. Alternatively, the IC includes a strained-silicon layer formed by silicon epitaxial growth onto the region of the semiconductor layer that has been implanted with ions. The IC also preferably includes a CMOS device that preferably, but not necessarily, incorporates sub-0.1 micron technology. The implanted ions may preferably be heavy ions, such as germanium ions, antimony ions or others. Ion implantation may be done with a single implantation process, as well as with multiple implantation processes.

Abstract: Thin-film phase-change memories having small phase-change switching volume formed by overlapping thin films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a resistance, an insulating layer disposed between the first and second phase change layers; and a third phase change layer having a resistance, and coupled to each of the first and second phase change layers, bridging the insulating layer and electrically coupling the first and second phase change layers, wherein the resistance of the third phase change layer is greater than both the resistance of the first phase change layer and the second phase change layer.

Abstract: A method of manufacturing a low temperature polysilicon film is provided. A first metal layer is formed on a substrate; and openings have been formed in the first metal layer. A second metal layer is formed on the first metal layer: and a hole corresponding to each of the openings is formed in the second metal layer. A silicon layer is formed on the second metal layer; a silicon seed is formed on the substrate inside each of the holes. After removing the first and the second metal layers, an amorphous silicon layer is formed on the substrate by using the silicon seed. Then a laser crystallization step is performed to form a polysilicon layer from the amorphous layer. Since the position of the silicon seed can be controlled, the size and distribution of the silicon grain and the number of the silicon crystal interface can also be controlled.

Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.

Abstract: Method for forming a strained Si layer on a substrate (1), including formation of: an epitaxial SiGe layer (4) on a Si surface, and of: the strained Si layer by epitaxial growth of the Si layer on top of the epitaxial SiGe layer (4), the Si layer being strained due to the epitaxial growth, wherein the substrate (1) is a Silicon-On-Insulator substrate with a support layer (1), a buried silicon dioxide layer (BOX) and a monocrystalline Si surface layer (3), the method further including: ion implantation of the Si surface layer (3) and the epitaxial SiGe layer (4) to transform the Si surface layer (3) into an amorphous Si layer (3B) and a portion of the epitaxial SiGe layer (4) into an amorphous SiGe layer (5), a further portion of the epitaxial SiGe layer (4) being a remaining monocrystalline SiGe layer (6), the amorphous Si layer (3B), the amorphous SiGe layer and the remaining monocrystalline SiGe layer (6) forming a layer stack (3B, 5, 6) on the buried silicon dioxide layer (BOX), with the amorphous Si layer

Abstract: A storage node, phase change memory device having a storage node, a method of fabricating the phase change memory device and a method of operating the phase change memory device are provided. The phase change memory device includes a switching device and a storage node connecting to the switching device. The storage node includes a bottom electrode, a phase change layer formed on the bottom electrode, a material layer formed on the phase change layer and a top electrode formed on the phase change layer around the material layer.

Abstract: A laser beam pattern mask includes an opaque substrate and a plurality of transmission portions formed in the substrate to transmit light, wherein each of the transmission portions extend in a first direction while being uniformly spaced apart from one another by a predetermined distance in a second direction perpendicular to the first direction, each of the transmission portions including hexagonal cells arranged in the first direction and in contact with one another.

Abstract: A method of fabricating a semiconductor thin film is provided, comprising: forming an insulation layer on a semiconductor substrate; etching the insulation layer to form a plurality of openings exposing the substrate at the bottom of the openings; filling the openings with a semiconductor seed layer; forming an amorphous layer on the seed layer and the insulation layer; transforming the amorphous layer to a polycrystalline layer by exposing the amorphous layer to a first laser irradiation at a first energy level; and forming a single semiconductor crystalline film by annealing the polycrystalline layer and the semiconductor seed layer with a second laser irradiation at a second energy level.

Abstract: [Problem] To provide technology that allows, by controlling a crystal orientation, forming a crystalline semiconductor film aligned in orientation and obtaining a crystalline semiconductor film whose impurity concentration is reduced. [Means, for Resolution] On an insulating surface, a first semiconductor region made of an amorphous semiconductor is formed, a continuous wave laser beam is scanned from one end of the first semiconductor region to the other end thereof, thereby the first semiconductor region is once melted and crystallized, thereafter in order to form an active layer of a TFT the first semiconductor region is etched, and thereby a second semiconductor region is formed. In a pattern of the second semiconductor region formed by the etching, in order to improve a field-effect mobility in the TFT, a scanning direction of the laser beam is allowed roughly coinciding with a channel length direction in a thin film transistor. [Selected Drawing] FIG. 1.

Abstract: In an image pickup device, a step of forming an embedded plug includes a step of forming a connecting hole in the insulation film in which the embedded plug is to be formed, a metal layer deposition step of depositing a metal layer on the insulation film in which the connecting hole is formed, thereby covering an interior of the connecting hole and at least a part of an upper surface of the insulation film in a laminating direction thereof, and a metal layer removing step of polishing the upper surface of the insulation film on which the metal layer is deposited thereby removing the metal layer except for the interior of the connecting hole, an etch-back method performed on the embedded plug in at least an insulation film, and a chemical mechanical polishing method performed on the embedded plug in another insulation film.

Abstract: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A four-component wet etch mixture is tuned to selectively etch the amorphous region while retaining the epitaxial region, wherein the four-component wet etch mixture comprises an oxidizing agent, an etchant, a buffer and a diluent.

Abstract: A memory device is described an active material configured to be placed in a more or less conductive state by means of appropriate switching processes. The active material is positioned between a material having low thermal conductivity or material layers having low thermal conductivity.

Abstract: A method for crystallizing silicon is provided. The method includes: forming an amorphous silicon layer on a substrate; aligning a mask above the substrate, the mask being divided into a plurality of blocks, each block having at least two transmission patterns, the transmission patterns of one block and the transmission patterns of another adjacent block being complimentary with each other and the mask including at least two diffraction patterns disposed between the transmission patterns; forming a first crystallization region on the amorphous silicon layer by irradiating a laser beam through the transmission patterns of the mask; and displacing the substrate or the mask by a predetermined distance and irradiating a laser beam onto the substrate to recrystallize the crystallization region using the laser beam that passes through the diffraction patterns, and forming a second crystallization region using the laser beam that passes through the transmission patterns.

Abstract: A method for fabricating a pixel structure of an OELD includes the following steps. First, a first gate, a scan line and a second gate are formed on a substrate. Next, a gate insulation layer is formed on the substrate to cover the first gate, the scan line and the second gate. Then, on the gate insulation layer, a first channel layer and a second first channel layer are formed, which are located over the first gate and the second gate, respectively. Afterwards, a first source and a first drain beside the first channel layer and a data line are formed; meanwhile, a second source and a second drain beside the second channel layer, and a cathode electrically connected to the second drain are formed. Further, an organic functional layer is formed on the cathode. Finally, an anode is formed on the organic functional layer.

Abstract: A method for introducing impurities includes a step for forming an amorphous layer at a surface of a semiconductor substrate, and a step for forming a shallow impurity-introducing layer at the semiconductor substrate which has been made amorphous, and an apparatus used therefore. Particularly, the step for forming the amorphous layer is a step for irradiating plasma to the surface of the semiconductor substrate, and the step for forming the shallow impurity-introducing layer is a step for introducing impurities into the surface which has been made amorphous.

Abstract: A phase change memory device is manufactured by forming a first insulation layer on a semiconductor substrate having a plurality of phase change cell forming regions; defining a groove by etching the first insulation layer; forming a lower electrode in the groove; recessing the lower electrode; forming a second insulation layer on the recessed lower electrode to fill the groove; etching the second insulation layer and to define a hole for exposing the lower electrode; forming a lower electrode contact in the hole; and forming a phase change layer and an upper electrode on the lower electrode contact. By manufacturing the phase change memory device in this manner, the interface between the lower electrode contact and a phase change layer can be defined in a stable manner, resulting in the uniformity of a programming circuit.

Abstract: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A four-component wet etch mixture is tuned to selectively etch the amorphous region while retaining the epitaxial region, wherein the four-component wet etch mixture comprises an oxidizing agent, an etchant, a buffer and a diluent.

Abstract: In a method of making a c-Si-based cell or a ?c-Si-based cell, the improvement of increasing the minority charge carrier's lifetime, comprising: a) placing a c-Si or polysilicon wafer into CVD reaction chamber under a low vacuum condition and subjecting the substrate of the wafer to heating; and b) passing mixing gases comprising NH3/H2 through the reaction chamber at a low vacuum pressure for a sufficient time and at a sufficient flow rate to enable growth of an a-Si:H layer sufficient to increase the lifetime of the c-Si or polysilicon cell beyond that of the growth of an a-Si:H layer without treatment of the wafer with NH3/H2.

Abstract: A method to enhance grain size in polysilicon films while avoiding formation of hemispherical grains (HSG) is disclosed. The method begins by depositing a first amorphous silicon film, then depositing silicon nuclei, which will act as nucleation sites, on the amorphous film. After deposition of silicon nuclei, crystallization, and specifically HSG, is prevented by lowering temperature and/or raising pressure. Next a second amorphous silicon layer is deposited over the first layer and the nuclei. Finally an anneal is performed to induce crystallization from the embedded nuclei. Thus grains are formed from the silicon bulk, rather than from the surface, HSG is avoided, and a smooth polysilicon film with enhanced grain size is produced.

Abstract: In a step of doping a silicon-based semiconductor film as a TFT active layer such as channel doping or the like, a protective film is formed by a CVD method as a pretreatment so as to prevent the silicon-based semiconductor film from being contaminated and etched. However, in the case of using the protective film formed by the CVD method, the problems in terms of throughput and production cost (an expensive apparatus is required) have been pointed out. The present invention is intended to solve the above-mentioned problems. Instead of the CVD method, a step of forming a chemical oxide film on a silicon-based semiconductor film is introduced as the pretreatment in the step of doping the silicon-based semiconductor film. Alternatively, a step is introduced in which unsaturated bonds present at the surface of the silicon-based semiconductor film are made to terminate with an element (for instance, oxygen) to be bonded with bonding energy higher than that of Si—H bonds.

Abstract: Methods of forming semiconductor structures characterized by a thin active silicon layer on an insulating substrate by a crystal imprinting or damascene approach. The methods include patterning an insulating layer to define a plurality of apertures, filling the apertures in the patterned insulating layer with amorphous silicon to define a plurality of amorphous silicon features, and re-growing the amorphous silicon features to define a thin active silicon layer consisting of regrown silicon features. The amorphous silicon features may be regrown such that a number have a first crystal orientation and another number have a different second crystal orientation.

Abstract: It is an object of the present invention to provide a method for removing the metal element from the semiconductor film which is different from the conventional gettering step for removing the metal element from the semiconductor film. In the present invention, when Ni element (Ni) is used as the metal element and a silicon-based film (referred to as a silicon film) is used as the semiconductor film, nickel silicide segregates in the ridge formed in the silicon film by irradiating the pulsed laser light. Next, etching solution of hydrofluoric acid based etchant is used to remove the nickel silicide segregated in the ridge. When the surface of the semiconductor film is rough after removing the metal element by means of etching, the laser light may be irradiated to the semiconductor film under the insert atmosphere to flatten the surface thereof.

Abstract: A method to form a strain-inducing epitaxial film is described. In one embodiment, the strain-inducing epitaxial film is a three-component epitaxial film comprising atoms from a parent film, charge-neutral lattice-substitution atoms and charge-carrier dopant impurity atoms. In another embodiment, the strain-inducing epitaxial film is formed by a multiple deposition/etch cycle sequence involving hydrogenated amorphous silicon, followed by charge carrier dopant and charge-neutral lattice-forming impurity atom implant steps and, finally, a kinetically-driven crystallization process.

Abstract: Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in the trench from a semiconductor layer with a second crystalline orientation. Additional isolation structures are formed within the silicon material in the trench and within the semiconductor layer. A patterned amorphization process is performed on the silicon material in the trench and followed by a recrystallization anneal such that the silicon material in the trench recrystallizes with the same crystalline orientation as the silicon substrate. The resulting structure is a semiconductor wafer with isolated semiconductor areas on the same plane having different crystalline orientations as well as isolated sections within each semiconductor area for device formation.

Abstract: After a bottom electrode film is formed, a ferroelectric film is formed on the bottom electrode film. Then, a heat treatment is performed for the ferroelectric film in an oxidizing atmosphere so as to crystallize the ferroelectric film. Then, a top electrode film is formed on the ferroelectric film. In the heat treatment (i.e., annealing for crystallization), a flow rate of oxidizing gas is set to be in a range of from 10 sccm to 100 sccm.

Abstract: A semiconductor device manufacturing method, includes a step of forming refractory metal silicide layers 13a to 13c in a partial area of a semiconductor substrate 10, a step of forming an interlayer insulating film 21 on the refractory metal silicide layers 13a to 13c, a step of forming a first conductive film 31, a ferroelectric film 32, and a second conductive film 33 in sequence on the interlayer insulating film 21, a step of forming a capacitor Q consisting of a lower electrode 31a, a capacitor dielectric film 32a, and an upper electrode 33a by patterning the first conductive film 33, the ferroelectric film 32, and the second conductive film 31, and a step of performing an annealing for an annealing time to suppress a agglomeration area of the refractory metal silicide layers 13a to 13c within an upper limit area.

Abstract: A mask for crystallization of amorphous silicon to polysilicon is provided. The mask includes a plurality of slit patterns for defining regions to be illuminated. The plurality of slit patterns are formed along a longitudinal first direction and the mask moves along a longitudinal second direction. The first longitudinal direction is substantially perpendicular to the second longitudinal direction. Each of the split patterns is deviated apart by substantially a same distance from another. Thus, the polysilicon using the mask are grown to be isotropic with respect to the horizontal and vertical directions.

Abstract: A process for bonding oxide-free silicon substrate pairs and other substrates at low temperature. This process involves modifying the surface of the silicon wafers to create defect regions, for example by plasma-treating the surface to be bonded with a or boron-containing plasmas such as a B2H6 plasma. The surface defect regions may also be created by ion implantation, preferably using boron. The surfaces may also be amorphized. The treated surfaces are placed together, thus forming an attached pair at room temperature in ambient air. The bonding energy reaches approximately 400 mJ/m2 at room temperature, 900 mJ/m2 at 150° C., and 1800 mJ/m2 at 250° C. The bulk silicon fracture energy of 2500 mJ/m2 was achieved after annealing at 350-400° C. The release of hydrogen from B—H complexes and the subsequent absorption of the hydrogen by the plasma induced modified layers on the bonding surfaces at low temperature is most likely responsible for the enhanced bonding energy.

Abstract: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A heat treatment is carried out for an amorphous semiconductor thin film, to thereby obtain a crystalline semiconductor thin film. After the crystalline semiconductor thin film is irradiated with ultraviolet light or infrared light, a heat treatment at a temperature range of 900 to 1200° C. is carried out in a reducing atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grain boundaries and crystal grains disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained.

Abstract: There is disclosed a liquid crystal display device and a fabricating method thereof that reduce the number of processes and production cost. A liquid crystal display device and a fabricating method thereof according to an embodiment of the present invention forms a poly-silicon pattern by partially crystallizing an amorphous silicon, and simultaneously etches the amorphous silicon and the poly-silicon pattern, thereby removing the amorphous silicon and leaving the poly-silicon pattern on the substrate.

Abstract: By using a combination of solid phase epitaxy re-growth and laser annealing, the present invention provides a low thermal budget method which allows the crystal lattice of a semiconductor surface to recover after the doping by ion implantation. The low thermal budget limits the out-diffusion of the dopants ions, thus avoiding the enlargement of the doped source/drain regions. Therefore, the method is suited, for instance, for the fabrication of ultra-shallow source/drain regions in MOS transistors elements. The method according to the present invention comprises a first pre-amorphization process in order to limit channeling effects, a doping process by ion implantation and a re-crystallization by solid phase epitaxy, followed by laser annealing.

Abstract: Chemical vapor deposition methods are used to deposit silicon-containing films over mixed substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, high deposition rates, and higher manufacturing productivity. An example is in forming the base region of a heterojunction bipolar transistor, including simultaneous deposition over both single crystal semiconductor surfaces and amorphous insulating regions.

Abstract: A method for making a structure which may have at least one layer on a supporting substrate. The method includes at least the steps for forming from the supporting substrate an intermediate structure which may have an amorphous layer, a first crystalline layer containing point defects and, a second crystalline layer located immediately underneath the amorphous layer and in the lower portion of the intermediate structure. The method may also include bonding a receiving substrate on the upper face of the intermediate structure and removing the layer of the intermediate structure in which point defects have formed so that amorphous layer forms the upper layer of the intermediate structure. A structure made by such a method may comprise at least one thin layer of an amorphous material on a supporting substrate. The structure may comprise a receiving substrate, a central crystalline layer and an amorphous layer, all of which may lack any EOR type point defect.

Abstract: A high-quality isotropic polycrystalline silicon (poly-Si) and a method for fabricating high quality isotropic poly-Si film are provided. The method includes forming a film of amorphous silicon (a-Si) and using a MISPC process to form poly-Si film in a first area of the a-Si film. The method then anneals a second area, included in the first area, using a Laser-Induced Lateral Growth (LILaC) process. In some aspects, a 2N-shot laser irradiation process is used as the LILaC process. In some aspects, a directional solidification process is used as the LILaC process. In response to using the MISPC film as a precursor film, the method forms low angle grain boundaries in poly-Si in the second area.

Abstract: It is an object of the present invention to provide a porous body containing an oxide semiconductor in which more efficient photocatalytic reactions and photoelectrode reactions occur. The present invention relates to a porous body having a network structure skeleton wherein 1) the aforementioned skeleton is composed of an inner part and a surface part, 2) the aforementioned inner part is substantially made of carbon material, and 3) all or part of the aforementioned surface part is an oxide semiconductor, and to a manufacturing method therefor.

Abstract: A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.

Abstract: A method of forming a field effect transistor is provided which includes forming an amorphized semiconductor region having a first depth from a single-crystal semiconductor region and subsequently forming a first gate conductor above a channel portion of the amorphized semiconductor region. A first dopant including at least one of an n-type dopant and a p-type dopant is then implanted to a second depth into portions of the amorphized semiconductor region not masked by the first gate conductor to form source/drain portions adjacent to the channel portion. The substrate is then heated to recrystallize the channel portion and the source/drain portions of the amorphized semiconductor region. After the heating step, at least a part of the recrystallized semiconductor region is locally heated to activate a dopant in at least one of the channel portion and the source/drain portion.

Abstract: Disclosed herein are methods of fabricating a polycrystalline silicon film and methods of fabricating a thin film transistor (TFT) using the same. The method of fabricating a polycrystalline silicon film includes forming an electrically insulating thermally conductive layer using a material selected from the group consisting of aluminum-containing ceramics, cobalt-containing ceramics, and iron-containing ceramics, on a substrate; forming an amorphous silicon layer on the thermally conductive layer; forming an amorphous silicon island by patterning the amorphous silicon layer; and crystallizing amorphous silicon by annealing the amorphous silicon island. A polycrystalline silicon film having a very large grain size and a TFT using the same can be formed in desired positions.

Abstract: A method of fabrication a polysilicon layer is provided. A substrate is provided and then a buffer layer having a plurality of trenches thereon is formed over the substrate. Thereafter, an amorphous silicon layer is formed over the buffer layer. Finally, a laser annealing process is conducted so that the amorphous silicon layer melts and crystallizes into a polysilicon layer starting from the upper reach of the trenches. This invention can be applied to fabricate the polysilicon layer of a low temperature polysilicon thin film transistor liquid crystal display such that the crystals inside the polysilicon layer are uniformly distributed and have a larger average size.

Abstract: The mobility of carriers may be increased in strained channel epitaxial source/drain transistors. Doped silicon material may be blanket deposited after removing ion implanted source/drain regions. The blanket deposition forms amorphous films over non-source/drain areas and crystalline films in source/drain regions. By using an etch which is selective to amorphous silicon, the amorphous material may be removed. This may avoid some problems associated with selective deposition of the doped silicon material.

Abstract: It is an object of the present invention to provide a high order silane composition that contains a polysilane having a higher molecular weight than conventionally, this being from the viewpoints of wettability when applying onto a substrate, boiling point and safety, and hence in particular enables a high-quality silicon film to be formed easily, and also a method of forming an excellent silicon film using the composition. The present invention attains this object by providing a high order silane composition containing a polysilane obtained through photopolymerization by irradiating a solution of a photopolymerizable silane or a photopolymerizable like-liquid silane with ultraviolet light. Moreover, the present invention provides a method of forming a silicon film comprising the step of applying such a high order silane composition onto a substrate.

Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.

Abstract: A thin film transistor formed by using a Metal Induced Lateral Crystallization process and method for fabricating the same. The thin film transistor comprises an active layer having source/drain regions and a channel region, a gate electrode, an insulating layer having contact holes for exposing a portion of each of the source/drain regions, and a crystallization inducing pattern exposing a portion of the active layer. The source/drain electrodes are coupled to the source/drain regions through the contact holes, and the crystallization inducing pattern does not couple the source/drain regions to the source/drain electrodes.

Abstract: A method of manufacturing a low temperature polysilicon film is provided. A first metal layer is formed on a substrate; and openings have been formed in the first metal layer. A second metal layer is formed on the first metal layer: and a hole corresponding to each of the openings is formed in the second metal layer. A silicon layer is formed on the second metal layer; a silicon seed is formed on the substrate inside each of the holes. After removing the first and the second metal layers, an amorphous silicon layer is formed on the substrate by using the silicon seed. Then a laser crystallization step is performed to form a polysilicon layer from the amorphous layer. Since the position of the silicon seed can be controlled, the size and distribution of the silicon grain and the number of the silicon crystal interface can also be controlled.

Abstract: Chemical vapor deposition methods are used to deposit amorphous silicon-containing films over various substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, high deposition rates, and higher manufacturing productivity. Preferably, the deposited amorphous silicon-containing film is annealed to produce crystalline regions over all or part of an underlying substrate.

Abstract: A micro-electro mechanical system includes a flexure, wherein the flexure is made of an amorphous material. Similarly, a method for forming a micro-electro mechanical system includes forming a substrate, and forming an amorphous flexure, the amorphous flexure being coupled to the substrate.

Abstract: A method of forming a liquid crystal display device includes forming an amorphous silicon layer over a substrate and forming a light reflecting layer only over a first portion of the amorphous silicon layer. The amorphous silicon layer is then irradiated with a laser to convert it to a polysilicon layer. The light reflecting layer partially reflects the light away from the first portion of the amorphous silicon layer such that a first portion of the polysilicon layer has a first polysilicon grain size and a second portion of the polysilicon layer has a second polysilicon grain size, which is larger than the first polysilicon grain size. A first plurality of thin film transistors having reduced leakage current characteristics may then be formed from the first portion of the polysilicon layer.

Abstract: Contamination of an interface of respective films constituting a TFT due to an contaminant impurity in a clean room atmosphere becomes a great factor to lower the reliability of the TFT. Besides, when an impurity is added to a crystalline semiconductor film, its crystal structure is broken. By using an apparatus for manufacturing a semiconductor device including a plurality of treatment chambers, a treatment can be made without being exposed to a clean room atmosphere in an interval between respective treatment steps, and it becomes possible to keep the interface of the respective films constituting the TFT clean. Besides, by carrying out crystallization after an impurity is added to an amorphous semiconductor film, the breakdown of the crystal structure of the crystalline semiconductor film is prevented.

Abstract: A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

Abstract: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A catalytic element for facilitating crystallization of an amorphous semiconductor thin film is added to the amorphous semiconductor thin film, and a heat treatment is carried out to obtain a crystalline semiconductor thin film. After the crystalline semiconductor thin film is irradiated with ultraviolet light or infrared light, a heat treatment at a temperature of 900 to 1200° C. is carried out in a reducing atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grains and crystal grain boundaries disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained.