Abstract: This invention discloses a process of phosphorus diffusion for manufacturing solar cell, comprising annealing a mono-crystalline silicon wafer in a nitrogen atmosphere at 900-950° C. for twenty to thirty minutes, carrying oxidation treatment in a hydrogen chloride atmosphere at 850-1050° C. to form a 10 to 30 nm thick oxide layer on the surface of said silicon wafer, diffusing from a phosphorus source at 850-900° C., until a block resistance of a material surface is controlled at 40 to 50 ohms, and the junction depth is at 0.2 to 1.0 microns, and annealing in a nitrogen atmosphere at 700-750° C. for thirty to sixty minutes to complete the phosphorus diffusion of said mono-crystalline silicon wafer. This invention allows the use of 4 N˜5 N mono-crystalline silicon as the material for manufacturing solar cells, so, the low purity material such as metallurgical silicon can be used, which greatly reduces the cost of materials.

Abstract: A method of forming a diffusion region is disclosed. The method includes depositing a nanoparticle ink on a surface of a wafer to form a non-densified thin film, the nanoparticle ink having set of nanoparticles, wherein at least some nanoparticles of the set of nanoparticles include dopant atoms therein. The method also includes heating the non-densified thin film to a first temperature and for a first time period to remove a solvent from the deposited nanoparticle ink; and heating the non-densified thin film to a second temperature and for a second time period to form a densified thin film, wherein at least some of the dopant atoms diffuse into the wafer to form the diffusion region.

Abstract: A method for forming a diffused, doped backside layer on a device wafer oxide bonded to a handle wafer in an integrated circuit is provided. The method comprises forming a thermal bond oxide layer on a backside surface of the device wafer of the integrated circuit. Implanting the bond oxide with a diffusing dopant. Diffusing dopant from the bond oxide into the backside surface of the device wafer. Depositing an oxide layer on the bond oxide and bonding the deposited oxide layer to the handle wafer of the integrated circuit.

Abstract: [PROBLEMS] To provide a semiconductor element manufacturing method by which a semiconductor element having high accuracy and high function can be manufactured by controlling diffusion depth and diffusion concentration in a pn junction region with high accuracy. [MEANS FOR SOLVING PROBLEMS] A diffusion control layer (2) composed of a thin film of a substance having a smaller diffusion coefficient than that of a diffusion source (3) is formed between a surface of a substrate (1) and the diffusion source (3), and an element of the diffusion source (3) is permitted to thermally diffuse through the diffusion control layer (2). Thus, the diffusion depth and the diffusion concentration in the semiconductor region, which is formed on the surface portion of the substrate and has a conductivity type different from that of the substrate, can be highly accurately controlled, and the semiconductor element having high accuracy and high function can be manufactured.

Abstract: A method for forming an electronic device provides a carrier formed from a composite material comprising a plastic binder and an embedded material. A substrate material is attached to the carrier. The substrate is processed to form the electronic device thereon. The substrate is then detached from the carrier to yield the resultant electronic device.

Abstract: A method of fabricating a non-volatile memory is provided. First, two openings are formed on a substrate. A stacked gate structure comprising a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer is formed on the substrate between the two openings. A liner is formed on a bottom and a portion of a sidewall of the tow openings, wherein a top surface of the liner is lower than that of the substrate. A second conductive layer is formed on the liner at the bottom of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner. A third conductive layer is formed on the second conductive layer and the liner, wherein a top surface of the third conductive layer is co-planar with that of the substrate and lower than that of the first dielectric layer.

Abstract: A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer and the gate electrode region. The semiconductor layer and the gate dielectric layer share a common interfacing surface which defines a reference direction perpendicular to the common interfacing surface and pointing from the semiconductor layer to the gate dielectric layer. Next, a resist layer is formed on the gate dielectric layer and the gate electrode region. Next, a cap portion of the resist layer directly above the gate electrode region in the reference direction is removed without removing any portion of the resist layer not directly above the gate electrode region in the reference direction.

Abstract: Embodiments of a method of quantum well intermixing (QWI) comprise providing a wafer comprising upper and lower epitaxial layers, which each include barrier layers, and a quantum well layer disposed between the upper and lower epitaxial layers, applying at least one sacrificial layer over the upper epitaxial layer, and forming a QWI enhanced region and a QWI suppressed region by applying a QWI enhancing layer over a portion of the sacrificial layer, wherein the portion under the QWI enhancing layer is the QWI enhanced region, and the other portion is the QWI suppressed region. The method further comprises the steps of applying a QWI suppressing layer over the QWI enhanced region and the QWI suppressed region, and annealing at a temperature sufficient to cause interdiffusion of atoms between the quantum well layer and the barrier layers of the upper epitaxial layer and the lower epitaxial layer.

Abstract: A method by which solid phase crystallization (SPC) thermal budget for crystallizing an undoped (or a lightly doped) amorphous Si (a-Si) is significantly reduced. First, a composite layer structure consisting of an undoped (or a lightly doped) a-Si layer and a heavily doped (either p-type or n-type) a-Si layer is formed and it is subsequently annealed at an elevated temperature. The solid phase crystallization starts from the heavily doped amorphous silicon layer at a substantially reduced thermal budget and proceeds to crystallize the undoped amorphous silicon layer in contact with the heavily doped film at reduced thermal budget. The method can be applied to form poly silicon thin film transistor at reduced thermal budgets.

Abstract: The method described herein enables the introduction of external impurities into Silicon Carbide (SiC) to be conducted at a temperature between 1150-1400° C. Advantages include: a) low temperature diffusion procedure with greater control of the doping process, b) prevent roughness of SiC surface, c) less surface defects and d) better device performance and higher yield. The method described herein involves depositing a ceramic layer that contains the desired impurity and a certain element such as oxygen (in the form of oxide), or other elements/compounds that draw out the silicon and carbon atoms from the surface region of the SiC leaving behind carbon and silicon vacancies which then allow the external impurity to diffuse into the SiC more easily. In another embodiment, the deposited layer also has carbon atoms that discourage carbon from escaping from the SiC, thus generating a surface region of excess carbon in addition to the silicon vacancies.

Abstract: A P-type polysilicon layer having a stable and desired resistivity is formed by alternately depositing a plurality of silicon atom layers and a plurality of group IIIA element atom layers on a semiconductor substrate by atomic layer deposition, and thereafter forming a P-type polysilicon layer by thermally diffusing the plurality of group IIIA element atom layers into the plurality of silicon atom layers. The plurality of group IIIA element atom layers may comprise Al, Ga, In, and/or Tl.

Abstract: The present invention relates to a method of fabricating a semiconductor-on-insulator-type heterostructure that includes at least one insulating layer interposed between a receiver substrate of semiconductor material and an active layer derived from a donor substrate of semiconductor material. The method includes the steps of bonding and active layer transfer. Prior to bonding, an atomic species which is identical or isoelectric with the insulating layer material is implanted in the insulating layer. The implantation forms a trapping layer, which can retain gaseous species present in the various interfaces of the heterostructure, thereby limiting formation of defects on the surface of the active layer.

Abstract: The present invention is a method for manufacturing a solar cell by forming a p-n junction in a semiconductor substrate having a first conductivity type, wherein, at least: a first coating material containing a dopant and an agent for preventing a dopant from scattering, and a second coating material containing a dopant, are coated on the semiconductor substrate having the first conductivity type so that the second coating material may be brought into contact with at least the first coating material; and, a first diffusion layer formed by coating the first coating material, and a second diffusion layer formed by coating the second coating material the second diffusion layer having a conductivity is lower than that of the first diffusion layer are simultaneously formed by a diffusion heat treatment; a solar cell manufactured by the method; and a method for manufacturing a semiconductor device.

Abstract: A method for producing a semiconductor component, in particular a solar cell, having regions which are doped to different extents. A layer is formed which inhibits the diffusion of a dopant and can be penetrated by a dopant, on at least one part of the surface of a semiconductor component material. The diffusion-inhibiting layer is at least partially removed in at least one high-doping region. A dopant source is formed on the diffusion-inhibiting layer and in the at least one high-doping region. Then the dopant is diffused from the dopant source into the semiconductor component material. The semiconductor component is suitable for use in integrated circuits, electronic circuits, solar cell modules, and to produce solar cells having a selective emitter structure.

Abstract: A method for introducing one or more impurities into nano-structured materials. The method includes providing a nanostructured material having a feature size of about 100 nm and less. The method includes subjecting a surface region of the nanostructured material to one or more impurities to form a first region having a first impurity concentration within a vicinity of the surface region. In a specific embodiment, the method includes applying a driving force to one or more portions of at least the nanostructured material to cause the first region to form a second region having a second impurity concentration.

Abstract: A method of fabricating a silicon-on-plastic layer via layer transfer includes depositing a layer of SiGe on a silicon substrate; depositing a layer of silicon; implanting splitting hydrogen ions into the silicon substrate; bonding a glass substrate to the silicon layer; splitting the wafer; removing the silicon layer and a portion of the SiGe layer; depositing a dielectric on the silicon side of the silicon-on-glass wafer; applying adhesive and bonding a plastic substrate to the silicon side of the silicon-on-glass wafer; removing the glass from the glass side of the bonded, silicon-on-glass wafer to form a silicon-on-plastic wafer; and completing a desired IC device on the silicon-on-plastic. Multi-level structure may be fabricated according to the method of the invention by repeating the last few steps of the method of the invention.

Abstract: A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon layers is initiated. A semiconductor alloy layer is deposited followed by an oxidation procedure used to segregate a germanium component from the overlying semiconductor alloy layer into an underlying single crystalline silicon body. The level of germanium segregated into the underlying single crystalline silicon body determines the level of strain, which is in tensile state of a subsequently selectively grown silicon layer.

Abstract: A solution containing impurity ions is applied onto the surface of a silicon film to form a solution layer, followed by drying into a compound layer containing the impurities. Heat treatment is performed by irradiation with an energy beam so as to diffuse the impurity atoms in the compound layer toward the silicon film into a source region and a drain region. Subsequently, the compound layer is removed.

Abstract: A diode is disclosed. One embodiment provides a semiconductor body having a front and a back, opposite the front in a vertical direction of the semiconductor body. The semiconductor body contains, successively in the vertical direction from the back to the front, a heavily n-doped zone, a weakly n-doped zone, a weakly p-doped zone and a heavily p-doped zone. In the vertical direction, the weakly p-doped zone has a thickness of at least 25% and at most 50% of the thickness of the semiconductor body.

Abstract: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silican particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The dispersions can be printed as an ink for appropriate applications. The dispersions can be used to selectively dope semiconductor materials such as for the formation of photovoltaic cells or for the formation of printed electronic circuits.

Abstract: A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized.

Abstract: The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to be reliably dissipated, and for dendrite formation to be prevented, by a discharge doping region formed in the first and second doping regions.

Abstract: A method for manufacturing a semiconductor device capable of reducing a short channel effect, whereby the semiconductor device includes a pair of impurity regions for a source and a drain formed on a semiconductor substrate, a gate having a gate electrode used to control a drain current, side walls formed on both sides of the gate electrode, and a pair of electrode members formed on both sides of the semiconductor substrate and in contact with the side walls. First impurity regions are formed by thermal diffusion of impurities from each of the electrode members, and second impurity regions each having thickness smaller than the first impurity region and extending below the gate electrode are formed by thermal diffusion of impurities from the side walls.

Abstract: Consistent with an example embodiment, a method of manufacturing a semiconductor device comprises MOS transistors having gate electrodes formed in a number of metal layers deposited upon one another. Active silicon regions having a layer of a gate dielectric and field-isolation regions insulating these regions from each other are formed in a silicon body. Then, a layer of a first metal is deposited in which locally, in a part of the active regions, nitrogen is introduced. On the layer of the first metal, a layer of a second metal is then deposited, after which the gate electrodes are etched in the metal layers. Before nitrogen is introduced into the first metal layer, an auxiliary layer of a third metal permeable to nitrogen is deposited an the first metal layer. Thus, the first metal layer can be nitrided locally without the risk of damaging the underlying gate dielectric.

Abstract: Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an LDD ion implantation layer; forming an insulation spacer on a sidewall of the gate electrode; forming a diffusion barrier; performing a high-density ion implantation process with respect to the substrate, thereby forming a source/drain; performing a first thermal treatment process with respect to a resultant structure, so as to activate impurities in the source/drain, and simultaneously causing a diffusion velocity of the impurities in the source/drain to be reduced by the diffusion barrier; and forming a salicide layer.

Abstract: After gate insulating film formation films are formed in an element formation region of a semiconductor substrate, a gate electrode formation film is formed on the gate insulating film formation films. A fluorine-containing insulting film is formed on the gate electrode formation film. Then, thermal treatment is performed to diffuse and introduce the fluorine contained in the fluorine-containing insulating film to interfaces between the semiconductor substrate and the gate insulting film formation films.

Abstract: The present invention achieves a shallow junction of a source and a drain, and provides a doping method which makes device properties reproducible and a semiconductor device fabricated using the method. In the present invention, doping for the semiconductor is conducted by attaching a molecular species with a higher electron affinity or lower ionization energy out of fullerene derivatives or metallocenes to the semiconductor surface to induce charge transfer from the molecule to the semiconductor.

Abstract: FinFET devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and methods for producing the same. The methods involve dopant implants into the insulator layer, thereby creating borophosphosilicate glass (BPSG) diffusion sources within the insulation layer underlying the active regions of the SOI wafer. Backend high temperature processing steps induce diffusion of the dopants contained in the diffusion source into the active regions, thereby forming a retrograde dopant profile extending towards the channel region. The method can be selectively applied to selected portions of a wafer to tailor device characteristics, such as for memory cells.

Abstract: A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface layer has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concentration of about 5×1017 atoms per cm3 to about 1×1019 atoms per cm3. The ultra-shallow highly-doped surface layer is formed by diffusion of ions from a doped layer into the substrate or by a plasma doping process. The ultra-shallow pinned layer is in contact with a charge collection region of a second conductivity type.

Abstract: A method of removing the cap from a gate of an embedded SiGe semiconductor device includes the formation of the embedded SiGe semiconductor device with the cap consisting of a cap material on top of the gate, first sidewall spacers on side surfaces of the gate, and embedded SiGe in source and drain regions. Second sidewall spacers are formed on the first sidewall spacers, these second sidewall spacers consisting of a material different from the cap material. The cap is stripped from the top of the gate with an etchant that selectively etches the cap material and not the second sidewall spacer material.

Abstract: Methods for fabrication of emitter wrap through (EWT) back-contact solar cells and cells made by such methods. Certain methods provide for higher concentration of dopant in conductive vias compared to the average dopant concentration on front or rear surfaces, and provided increased efficiency. Certain methods provide for selective doping to holes for forming conductive vias by use of printed dopant pastes. Other methods provide for use of spin-on glass substrates including dopant.

Abstract: A method for implanting gate regions essentially without implanting regions of the semiconductor layer where source/drain regions will be later formed. The method includes the steps of (a) providing (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, (iii) a gate region on the gate dielectric layer, wherein the gate region is electrically insulated from the semiconductor layer by the gate dielectric layer; (b) forming a resist layer on the gate dielectric layer and the gate region; (c) removing a cap portion of the resist layer essentially directly above the gate region essentially without removing the remainder of the resist layer; and (d) implanting the gate region essentially without implanting the semiconductor layer.

Abstract: Methods of fabricating MOSFETs in semiconductor/r devices are disclosed. One example method may include forming an isolation layer on a semiconductor substrate and forming a capping layer thereon, forming an epitaxial active region which is not covered with the isolation layer on said semiconductor substrate by using selectively epitaxial growth, and forming a gate dielectric layer and a gate electrode on said epitaxial active region, sequentially. The example method may also include forming a source/drain plug spaced apart from the both sides of said gate electrode in said epitaxial active region, forming a source/drain into said epitaxial active region on which said source/drain plug is formed, forming an interlayer dielectric layer on the entire surface of the resultant structure after the source/drain is formed; and forming contacts in said interlayer dielectric layer, wherein said contacts are connected to said gate electrode and said source/drain plug, respectively.

Abstract: A method of manufacturing a semiconductor device, which comprises forming a first semiconductor film on a surface of a semiconductor substrate, adsorbing a first impurity on a surface of the first semiconductor film, adsorbing a second impurity on the surface of the first semiconductor film, forming a second semiconductor film on the surface of the first semiconductor film, and solid-phase-diffusing the first impurity and the second impurity into a region of the semiconductor substrate which is located adjacent to the first and second semiconductor films to thereby form a first diffusion region containing the first impurity and a second diffusion region containing the second impurity, a concentration of the first impurity in the first diffusion region being higher than that of the second impurity in the second diffusion region, and the first diffusion region having the bottom thereof covered by the second diffusion region.

Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A super-saturated doped source silicide metallic layer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide metallic layer incorporates a substantially uniformly distributed dopant therein in a substantially uniform super-saturated concentration. The silicide metallic layer is reacted with the semiconductor substrate therebeneath to form a salicide layer and outdiffuse the dopant from the salicide layer into the semiconductor substrate therebeneath. The outdiffused dopant in the semiconductor substrate is then activated to form a shallow source/drain junction beneath the salicide layer. An interlayer dielectric is then deposited above the semiconductor substrate, and contacts are formed in the interlayer dielectric to the salicide layer.

Abstract: A method of manufacturing a semiconductor device has the steps of: (a) evacuating a sputtering chamber to a pressure of 1.5×10?8 torr to 9×10?8 torr and heating a silicon substrate to a temperature of 330° C. to 395° C.; (b) sputtering Co on the heated silicon substrate; (c) after the step (b), forming a cap layer having a small oxygen transmission performance on the silicon substrate without exposing the silicon substrate in air; (d) after the step (c), performing primary annealing; (e) after the step (d), removing the cap layer and unreacted Co; and (f) after the step (e), performing secondary annealing by heating the silicon substrate to a temperature of 450° C. to 750° C.

Abstract: A method is provided for forming NMOS and PMOS transistors with ultra shallow source/drain regions having high dopant concentrations. First sidewall spacers and nitride spacers are sequentially formed on the sides of a gate electrode followed by forming a self-aligned oxide etch stop layer. The nitride spacer is removed and an amorphous silicon layer is deposited. The etch stop layer enables a controlled etch of the amorphous silicon layer to form silicon sidewalls on the first sidewall spacers. Implant steps are followed by an RTA to activate shallow and deep S/D regions. The etch stop layer maintains a high dopant concentration in deep S/D regions. After the etch stop is removed and a titanium layer is deposited on the substrate, an RTA forms a titanium silicide layer on the gate electrode and an extended silicide layer over the silicon sidewalls and substrate which results in a low resistivity.

Abstract: A method of fabrication of laser gain material and utilization of such media includes the steps of introducing a transitional metal, preferably Cr2+ thin film of controllable thickness on the ZnS crystal facets after crystal growth by means of pulse laser deposition or plasma sputtering, thermal annealing of the crystals for effective thermal diffusion of the dopant into the crystal volume with a temperature and exposition time providing the highest concentration of the dopant in the volume without degrading laser performance due to scattering and concentration quenching, and formation of a microchip laser either by means of direct deposition of mirrors on flat and parallel polished facets of a thin Cr:ZnS wafer or by relying on the internal reflectance of such facets.

Abstract: Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.

Abstract: A method of manufacturing a semiconductor device includes forming a layer over a substrate, and doping the layer with a dopant, after which the layer is laser thermal annealed. The layer can be a nitride, an oxide, or a polysilicon layer. The dopants can be arsenic, phosphorous, boron, or nitrogen. During the laser thermal annealing, certain portions of a surface of the semiconductor device are laser thermal annealed and other portions of a surface of the semiconductor device are not exposed. Also, the surface of the layer is smoother after the laser thermal annealing.

Abstract: A semiconductor device includes source and drain contact regions which include a non-compounded combination of a semiconductor material and at least one metal. The metal may include an elemental metal, such as gold or aluminum, or may include an intermetallic. The contact regions may be formed by depositing a limited amount of the at least one metal on a source and a drain of the device, and annealing the device to induce diffusion of the at least one metal into the source and drain. The annealing time and temperature may be selected to limit diffusion of the at least one metal.

Abstract: A ROM embedded DRAM allows hard programming of ROM cells by shorting DRAM capacitor plates during fabrication. In one embodiment, the intermediate dielectric layer is removed and the plates are shorted with a conductor. In another embodiment, an upper conductor and dielectric are removed and a conductor is fabricated in contact with the DRAM storage plate. The memory allows ROM cells to be hard programmed to different data states, such as Vcc and Vss.

Abstract: A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.

Abstract: This invention provides an SOI substrate manufacturing method using a transfer method (bonding and separation). A separation layer (12) is formed on a silicon substrate (11). A silicon layer (13), SiGe layer (14), silicon layer (15′), and insulating layer (21) are sequentially formed on the resultant structure to prepare a first substrate (10′). This first substrate (10′) is bonded to a second substrate (30). The bonded substrate stack is separated into two parts at the separation layer (12). Next, Ge in the SiGe layer (14) is diffused into the silicon layer (13) by hydrogen annealing. With this process, a strained SOI substrate having the SiGe layer on the insulating layer (21) and a strained silicon layer on the SiGe layer is obtained.

Abstract: The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first major surface of said semiconducting substrate; step 2) diffusing the dopant atoms from said solids-based dopant source into said substrate by a controlled heat treatment step in a gaseous environment surrounding said semi-conducting substrate, the dopant from said solids-based dopant source diffusing directly into said substrate to form a first diffusion region and, at the same time, diffusing said dopant from said solids-based dopant source indirectly via said gaseous environment into said substrate to form a second diffusion region in at least some areas of said substrate to form a second diffusion region in at least some areas of said substrate not covered by said pattern; and step 3) forming a metal contact pattern substantially in alignment with

Abstract: In a semiconductor device (10), plural diffusion layer areas (2, 3) are formed so that the impurity concentration of the diffusion layer area (2) is set to be higher than that of the diffusion layer area (3), and a first contact wire (4) connected to the diffusion layer area (2) having the higher impurity concentration is set to be larger in sectional area than a second contact wire (5) connected to the diffusion layer area (3) having the lower impurity concentration.

Abstract: A first conductive electrode material is formed on a substrate. Chalcogenide comprising material is formed thereover. The chalcogenide material comprises AxSey. A silver comprising layer is formed over the chalcogenide material. The silver is irradiated effective to break a chalcogenide bond of the chalcogenide material at an interface of the silver comprising layer and chalcogenide material and diffuse at least some of the silver into the chalcogenide material. After the irradiating, the chalcogenide material outer surface is exposed to an iodine comprising fluid effective to reduce roughness of the chalcogenide material outer surface from what it was prior to the exposing. After the exposing, a second conductive electrode material is deposited over the chalcogenide material, and which is continuous and completely covering at least over the chalcogenide material, and the second conductive electrode material is formed into an electrode of the device.

Abstract: A non-doped n-type boron carbide semiconductor polytype and a method of fabricating the same is provided. The n-type boron carbide polytype may be used in a device for detecting neutrons, electric power conversion, and pulse counting. Such a device may include an n-type boron carbide layer coupled with a substrate where the boron carbide may be an electrically active part of the device. This n-type boron carbide layer may be fabricated through the use of closo-1,7-dicarbadodecaborane (metacarborane). Specifically, the non-doped n-type polytype may be fabricated using SR-CVD by placing the substrate in a vacuum chamber, cooling the substrate, introducing metacarborane into the chamber, adsorbing the metacarborane onto the surface of the substrate through the use of incident X-ray radiation or electron beam irradiation, decomposing the adsorbed metacarborane, and allowing the substrate to reach ambient temperature. The n-type polytype of the present invention may also be fabricated by PECVD.

Abstract: A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. A trench is formed in the epitaxial layer. A deep implanted N layer is formed below the trench at the interface between the substrate and the epitaxial layer, and N-type dopant is implant through the bottom of the trench to form an N region in the epitaxial layer below the trench but above and separated from the deep N layer. The structure is heated to cause the N layer to diffuse upward and the N region to diffuse downward. The diffusions merge to form a continuous N-type drain-drift region extending from the bottom of the trench to the substrate. Alternatively, the drain-drift region may be formed by implanting N-type dopant through the bottom of the trench at different energies, creating a stack of N-type regions that extend from the bottom of the trench to the substrate.

Abstract: A semiconductor doping process which enhances the dopant incorporation achievable using the Gas Immersion Laser Doping (GILD) technique. The enhanced doping is achieved by first depositing a thin layer of dopant atoms on a semiconductor surface followed by exposure to one or more pulses from either a laser or an ion-beam which melt a portion of the semiconductor to a desired depth, thus causing the dopant atoms to be incorporated into the molten region. After the molten region recrystallizes the dopant atoms are electrically active. The dopant atoms are deposited by plasma enhanced chemical vapor deposition (PECVD) or other known deposition techniques.