Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05?v?0.8, 0?w?0.9, 0.05?x?0.8, 0?y?0.3, 0.05?z?0.08 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structure embedded in a plurality of materials having a plurality of vaporization temperatures. The plurality of materials is formed on the electronic chip and the conductive structure is coupled to the electronic chip. To fabricate the circuit assembly, a support structure, including interstices, is formed on an electronic chip. The interstices of the support structure are filled with a material having a vaporization temperature that is less than the vaporization temperature of the support structure. Conductive structures are embedded in the support structure and the material, and a connective structure is mounted on the support structure. Finally, the material is removed from the interstices by heating the circuit assembly.

Abstract: Disclosed is a ball grid array (BGA) package substrate, in which a wire bonding pad and a solder ball pad are formed on a via hole, making high freedom in design of a circuit pattern and a high density circuit pattern possible, and a method of fabricating the same.

Abstract: A method for treating an inter-metal dielectric (IMD) layer to improve a mechanical strength and/or repair plasma etching damage including providing a low-K silicon oxide containing dielectric insulating layer; and carrying out a super critical fluid treatment of the low-K dielectric insulating layer including supercritical CO2 and a solvent including a silicon bond forming substituent having a bonding energy greater than a Si—H to replace at least a portion of the Si—H bonds with the silicon bond forming substituent.

Abstract: A fabricating method for a flat panel display device having a thin film pattern over a substrate is disclosed. The fabricating method includes depositing a hydrophilic resin over a substrate and patterning the hydrophilic resin to form hydrophilic resin patterns over areas outside where thin film patterns are to be formed over the substrate. The fabricating method also includes depositing a hydrophobic nano powder thin film material over the substrate and between the hydrophilic resin patterns and removing the hydrophilic resin patterns to form hydrophobic nano powder thin film patterns over the substrate. Moreover, the fabricating method includes treating the hydrophobic nano powder thin film patterns to form the thin film pattern.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A semiconductor package includes: a build-up wiring structure in which an insulating layer formed from a resin and a wiring layer formed from a conductive plating layer are stacked one on top of the other; a fine-wiring structure which is formed by patterning a conductive foil on a resin tape to which the conductive foil is attached, and includes a wiring layer that is finer than the wiring layer of the build-up wiring structure; and a junction layer which is formed from a thermoplastic resin and interposed between the build-up wiring structure and the fine-wiring structure, thereby bonding the structures together.

Abstract: A silicon condenser microphone package is disclosed. The silicon condenser microphone package comprises a transducer unit substrate, and a cover. The substrate includes an upper surface having a recess formed therein. The transducer unit is attached to the upper surface of the substrate and overlaps at least a portion of the recess wherein a back volume of the transducer unit is formed between the transducer unit and the substrate. The cover is placed over the transducer unit and includes an aperture.

Abstract: A method for manufacturing a structure includes depositing a dense dielectric over the entire wafer, which includes areas that require low dielectric capacitance and areas that require high mechanical strength. The method further includes masking areas of the dense dielectric over the areas that require high mechanical strength and curing unmasked areas of the dense dielectric to burn out porogens inside the dense dielectric and transform the unmasked areas of the dense dielectric to porous dielectric material. A semiconductor structure comprises porous and dense hybrid interconnects for high performance and reliability semiconductor applications.

Abstract: A printed wiring board for mounting electronic components includes an insulating layer and a wiring pattern formed on one surface of the insulating layer, wherein one end portion of a filled via 4 is connected with the wiring pattern and the other end portion is overlaid with a covering layer 9 obtained by applying a conductive paste to cover at least the boundary between the filled via 4 and the insulating layer 2; alternatively, a plating resist 7 is formed at the other end portion to cover at least the boundary between the filled via 4 and the insulating layer 2, and is removed after an end portion of the filled via 4 enclosed within the plating resist 7 is plated to produce a terminal layer, thereby preventing a wet processing liquid such as a tin plating solution from leaking in between the filled via 4 and the insulating layer 2.

Abstract: The present invention provides a method of manufacturing a semiconductor device and a semiconductor device that allow use of interlayer and interconnect insulating films having a low dielectric constant in forming a dual damascene structure. A first insulating film, a second insulating film, a first-mask forming layer, a second-mask forming layer, a third-mask forming layer, and a fourth-mask forming layer are sequentially deposited over a substrate. The fourth-mask forming layer is patterned to form a fourth mask having an interconnect trench pattern. After a resist mask is formed on the fourth mask, the layers to the second insulating film are etched to open via holes. The third-mask forming layer is etched through the fourth mask to thereby form a third mask having the interconnect trench pattern and to extend the via holes downward partway across the first insulating film.

Abstract: A method of manufacturing a multilevel interconnect structure using a screen printing method is disclosed. In the multilevel interconnect structure, an interlayer insulating film having a through hole with a conductive bump therein, and a second interconnect line are stacked on a substrate with a first interconnect line formed thereon. The first interconnect line is electrically connected to the second interconnect line via the conductive bump. The method includes a step of forming a first region of the interlayer insulating film on the substrate with the first interconnect line formed thereon, the first region including a part of a peripheral wall of the through hole; a step of forming a second region of the interlayer insulating film on the substrate with the first region formed thereon, the second region including a remaining part of the peripheral wall of the through hole; and a step of forming the conductive bump.

Abstract: A method to form interconnect structures including nano-scale, e.g., sub-lithographic, lines and vias for future generation of semiconductor technology using self-assembly block copolymers that can be placed at a specific location using a pre-fabricated hard mask pattern is provided. The inventive method provides an interconnect structure in which the line is self-aligned to the via.

Abstract: The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel salt.

Abstract: The electronic device includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of the second interconnect layer is smaller in area than the opposite end face. The via plug is exposed on the surface of the first interconnect layer facing the second interconnect layer. An insulating resin forming the first interconnect layer is higher in thermal decomposition temperature than an insulating resin forming the second interconnect layer.

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract: Silicon nitride film is formed on a silicon wafer mounted in a boat in an LPCVD tool by feeding a silicon source (SiH2Cl2, SiCl4, Si2Cl6, etc.) from an injector and feeding a mixed gas of monomethylamine (CH3NH2) and ammonia (NH3) as the nitrogen source from an injector. This addition of monomethylamine to the source substances for film production makes it possible to provide an improved film quality and improved leakage characteristics even at low temperatures (450-600° C.).

Abstract: A method of forming via-first, dual damascene interconnect structures by using a gap-filling, bottom anti-reflective coating material whose thickness is easily controlled by a solvent is provided. After application to a substrate, the bottom anti-reflective coating is partially cured by baking at a low temperature. Next, a solvent is dispensed over the coated wafer and allowed to contact the coating for a period of time. The solvent removes the bottom anti-reflective coating at a rate controlled by the bottom anti-reflective coating's bake temperature and the solvent contact time to yield a bottom anti-reflective coating thickness that is thin, while maintaining optimum light-absorbing properties on the dielectric stack. In another possible application of this method, sufficient bottom anti-reflective coating may be removed to only partially fill the vias in order to protect the bottoms of the vias during subsequent processing.

Abstract: A ferroelectric polymer memory device and its method of formation are disclosed. In accordance with one embodiment, lower electrode memory device portions are formed using a damascene patterning process and upper electrode memory device portions are formed using a subtractive patterning process.

Abstract: A semiconductor device manufacturing method comprises the steps of forming a metal film (24) on an organic interlayer insulating film (22) formed over a semiconductor substrate to get a metal diffusion preventing metal carbide film (23) on a boundary between the organic interlayer insulating film (22) and the metal film (24), and leaving the metal carbide film (23) on the organic interlayer insulating film (22) by removing selectively the metal film (24) from the metal carbide film (23).

Abstract: An interconnecting substrate for carrying a semiconductor device, comprising: an insulating layer; an interconnection set on an obverse surface of the insulating layer; an electrode which is set on a reverse surface side of the insulating layer and formed in such a way that, at least, a lateral face of an obverse end of the electrode is all round brought into contact with the insulating layer, while, at least, a reverse surface of the electrode is not in contact with said insulating layer; a via conductor which is disposed on an obverse surface of the electrode and formed in the insulating layer so as to connect this electrode with the interconnection; and a supporting structure on the surface of the insulating layer.

Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.

Abstract: A method of forming an interconnection line in a semiconductor device includes forming an interlayer insulating layer on an underlying layer having a lower conductive layer, patterning the interlayer insulating layer to form an opening exposing the lower conductive layer, forming an additional material layer conformally on the underlying layer including the opening, anisotropically etching the additional material layer to form an opening spacer covering a sidewall of the opening, performing a wet etch process using the opening spacer as an etch mask, forming a conductive layer pattern in the opening, and performing a heat treatment on the opening spacer.

Abstract: A method for fabricating an insulating layer having contact openings of varying depths for logic/DRAM circuits is achieved using a single mask and etch step. After forming stacked or trench capacitors, a planar insulating layer is formed. Contact openings are etched in the planar insulating layer to the substrate, and contact openings that extend over the edge of the stacked or trench capacitor top electrode, having an ARC, are etched using a novel mask design and a single etching step. This allows one to make contacts to the substrate without overetching while making low-resistance contacts to the sidewall of the capacitor top electrode. In the trench capacitor open areas are formed to facilitate making contact openings that extend over the top electrode. A series of contact openings that are skewed or elongated also improve the latitude in alignment tolerance.

Abstract: A method of making circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device.

Abstract: Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a via with a hydrogen silsesquioxane (HSQ)-based filler as expressed by the general chemical formula: (RSiO3/2)x(HSiO3/2)y, wherein x and y satisfy the relationships x+y=1 and 0<x<y<1, and R is selected from C4-C24 alkyl, C4-C24 alkenyl, C4-C24 alkoxy, C8-C24 alkenoxy, substituted C4-C24 hydrocarbon, non-substituted C1-C4 hydrocarbon or substituted C1-C4 hydrocarbon; and, partially etching the filler filling the via and an interlayer dielectric to form a trench, which is connected to the via in the region where the dual damascene interconnections are to be formed. Then, the filler remaining in the via is removed, and the trench and the via are filled with an interconnection material to complete the dual damascene interconnections.

Abstract: A thin film dielectric layer comprises a top portion and a bottom portion and has density and permittivity characteristics that vary substantially uniformly from the top portion to the bottom portion. Control over the density and/or permittivity is accomplished through varying deposition parameters such as flow rate of constituent process gases or deposition chamber pressure, or through a post deposition treatment, such as plasma treatment or curing.

Abstract: An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.

Abstract: A method is provided for processing a substrate including providing a processing gas comprising an organosilicon compound comprising a phenyl group to the processing chamber, and reacting the processing gas to deposit a low k silicon carbide barrier layer useful as a barrier layer in damascene or dual damascene applications with low k dielectric materials.

Abstract: The CD uniformity of a damascene pattern and the reliability of interconnection lines may be enhanced when a semiconductor device is manufactured by a method including: forming a first insulating layer on a semiconductor substrate, the first insulating layer having a contact hole partially exposing the substrate; forming a photoresist layer filling the contact hole; removing the photoresist layer such that the first insulating layer is exposed and a recess is formed in the contact hole; reducing, removing or substantially eliminating the recess by removing an upper portion of the first insulating layer; forming a second insulating layer having a trench exposing the photoresist layer and a portion of the first insulating layer adjacent thereto; and removing the remaining photoresist layer.

Abstract: Methods of forming a multi-level metal line of a semiconductor device are disclosed. One example method includes subsequently stacking first and second metal layers, wherein a conductive etching stopper layer is interposed at an interface between the first and second metal layers; forming first and second metal layer pattern by patterning the first metal layer, the etching stopper layer, and the second metal layer, wherein the first metal layer pattern is formed as a lower metal line; forming a connection contact in form of a plug by selectively etching the second metal layer pattern until the etching stopper layer is exposed; forming an interlayer insulating layer to cover the connection contact and the first metal layer pattern; and exposing an upper surface of the connection contact by planarizing the interlayer insulating layer.

Abstract: An insulating portion of the respective wiring layers for a semiconductor device is constituted of insulating films. The one insulating film is made of a material whose conductivity is higher than that of the other insulating film that is made of an ordinary silicon oxide film and is provided in contact with the wiring. An electric charge accumulated in the wiring generated in the course of manufacture of the semiconductor device is discharged through the one insulating film at a stage where a charge accumulation in the wiring is low. This permits the heat release value generated through the discharge to be suppressed to a low level, and the short-circuiting-failure between adjacent wirings to be suppressed or prevented.

Abstract: A semiconductor component has at least one organic semiconductor layer. The component also includes at least one protective layer for at least partially covering the at least one organic semiconductor layer to protect against environmental influences. The at least one protective layer contains a proportion of an alkane with CnH2n+1 and n greater than or equal to 15 or consists entirely of an alkane of this type, or of a mixture of alkanes of this type. In one example, the protective layer is a paraffin wax. This creates a high resistance to moisture.

Abstract: A method for impregnating the pores of a zeolite low-k dielectric layer with a polymer, and forming an interconnect structure therein, thus mechanically strengthening the dielectric layer and preventing metal deposits within the pores.

Abstract: A method for forming a zeolite-carbon doped oxide (CDO) composite dielectric material is herein described. Zeolite particles may be dispersed in a solvent. The zeolite solvent solution may then be deposited on an underlying layer, such as a wafer of other dielectric layer. At least some solvent may then be removed to form a zeolite film. A CDO may then be deposited in the zeolite film to form a zeolite-CDO composite film/dielectric. The zeolite-CDO composite film/dielectric may then be calcinated to form a solid phase zeolite-CDO composite dilectric.

Abstract: A two-step high density plasma-CVD process is described wherein the argon content in the film is controlled by using two different argon concentrations in the argon/silane/oxygen gas mixture used for generating the high density plasma. The first step deposition uses high argon concentration and low sputter etch-to-deposition (E/D) ratio. High E/D ratio maintains the gap openings without necking. In the second step, a lower argon concentration and lower E/D ratio are used. Since observed metal defects are caused by argon diffusion in the top 200-300 nm of the HDP-CVD film, by controlling argon concentration in the top part of the film (i.e. second step deposition) to a low value, a reduced number of metal defects are achieved.

Abstract: A method of fabricating a via and a trench is disclosed. A disclosed method comprises: forming a via hole and a trench in a interlayer dielectric layer on a semiconductor substrate where a predetermined device is formed; depositing a thin Hf layer on the substrate; performing a thermal treatment of the substrate to getter oxygen and forming a barrier layer; and filling copper into the via hole and the trench.

Abstract: The present invention relates to a method for forming a contact opening. First, a substrate having at least a dielectric layer formed thereon is provided. Then, a photoresist layer having a first opening is formed on the dielectric layer. A plasma etching operation is performed to form a second opening in the dielectric layer, and the first opening is located above the second opening. The bottom part of the first opening has a diameter smaller than that of the top part of the second opening. Thereafter, the photoresist layer is removed from the dielectric layer. Accordingly, at least a portion of the exposed contact opening will not be oxidized to prevent an increase in the resistance between the conductive pattern and the conductive layer that fills in the contact opening.

Abstract: The interlayer dielectric film made of a three-dimensionally polymerized polymer is formed by polymerizing: first cross-linking molecules having three or more sets of functional groups in one molecule providing a three-dimensional structure; and a second cross-linking molecule having two sets of functional groups in one molecule providing a two-dimensional structure. In the three-dimensionally polymerized polymer, dispersed are a number of molecular level pores formed by the polymerization of the first and second cross-linking molecules.

Abstract: A method for forming a dual damascene with improved profiles including providing a semiconductor process wafer including a dielectric insulating layer and an overlying hardmask layer; forming an uppermost layer of amorphous carbon substantially conformally over the hardmask layer; forming a trench line opening through at least the thickness of the amorphous carbon layer; forming a dual damascene opening comprising forming the trench line opening overlying a via opening pattern through a thickness of the hardmask layer and partially through a thickness of the dielectric insulating layer; and, filling the dual damascene opening with metal.

Abstract: The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO2. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO2, SiCOH, or doped silicate glass.

Abstract: A method for forming a dielectric layer is disclosed herein. In accordance with the method, a first material is provided (303) which comprises a suspension of nanoparticles in a liquid medium. A dielectric layer is then formed (305) on the substrate from the suspension through an evaporative process.

Abstract: Disclosed is a reinforced bond pad structure having nonplanar dielectric structures and a metallic bond layer conformally formed over the nonplanar dielectric structures. The nonplanar dielectric structures are substantially reproduced in the metallic bond layer so as to form nonplanar metallic structures. Surrounding each of the nonplanar metallic structures is a ring of dielectric material which provides a hard stop during probing of the bond pad so as to limit the amount of bond pad that can be removed during probing.

Abstract: A method of forming an interconnect for a semiconductor device using triple hard layers, comprises: forming a first hard layer serving as an etch stop layer on a metal interconnect-formed dielectric layer; forming a second hard layer on the first hard layer; forming a dielectric layer on the second hard layer; forming a third hard layer on the dielectric layer; forming a hole through the third and second hard layers, the dielectric layer, and the first hard layer; and filling the hole with metal to establish an interconnect. The second and third hard layers are each made of carbon-doped silicon oxide formed from a source gas and a redox gas, while controlling the carbon content in the second hard layer as a function of a flow rate of the redox gas.

Abstract: The present invention provides a method for forming a void-free copper damascene structure comprising a substrate having a conductive structure, a first dielectric layer on the substrate, a diffusion barrier layer on the first dielectric layer, and a second dielectric layer on the barrier layer. The method comprises forming via and trench openings developing a photoresist through a first and second hard mask. The first hard mask is laterally etched such that it is eroded to a greater extent from the trench opening with respect to the underlying second dielectric layer. Remaining gap fill layer is removed and the diffusion barrier layer within the via opening is etched to expose the conductive structure. The via and trench openings are plated with a barrier metal and a copper seed layer to obtain copper features that fill the openings and form a void-free copper damascene structure.

Abstract: Semiconductor devices having a via hole and methods for forming a via hole in a semiconductor device are disclosed. A disclosed method comprises performing a first etching process on an insulating layer to form a via hole, and performing a second etching process to enlarge a bottom of the via hole.

Abstract: A semiconductor device manufacturing method includes the steps of: forming first and second insulation films on a substrate provided with a first wiring; sequentially forming first to third mask layers on the second insulation film; forming a wiring groove pattern in the third mask layer; selectively processing the third mask layer, formed to project into the inside of the wiring groove pattern, into a tapered shape; forming a contact hole pattern in the second and first mask layer, and removing the tapered shape portions of the third mask layer; and forming wiring grooves in the second insulation film by etching using the third mask layer, and forming contact holes in the insulation film by etching using the second and first mask layers.