Abstract: A method is disclosed for forming insulative inter metal dielectric (IMD) layers without the attendant problems of having voids, key-holes and air gaps. This is accomplished by reducing the aspect ratio of the gaps between metal lines through a judicious two-step dielectric filling process and through the use of two-step removal of the photoresist. That is, the gap is filled with photoresist first, and then partially removed, thereby leaving a portion in the gap to reduce the aspect ratio of the gap. When a second insulative layer is formed over the substrate, the gap between the metal lines is filled without the conventional attendant problem of forming voids or key-holes. Hence, void free IMD integration with improved IMD gap filling is achieved along with improved IMD thermal conductivity through the use of a metal liner.

Abstract: Low k dielectrics such as black diamond have a tendency to delaminate from the edges of a silicon wafer, causing multiple problems, including blinding of the alignment mark. This problem has been overcome by inserting a layer of silicon nitride between the low k layer and the substrate. A key requirement is that said layer of silicon nitride be under substantial compressive stress (at least 5×109 dynes/cm2). In the case of a layer of black diamond, on which material the invention is particularly focused, a nucleating layer is also inserted between the silicon nitride and the black diamond. A process for laying down the required layers is described together with an example of applying the invention to a dual damascene structure.

Abstract: A damascene interconnect containing a dual etch stop/diffusion barrier. The conductive material of the damascene interconnect is capped with a conductive metal diffusion barrier cap, typically using electroless deposition, and, optionally, with a dielectric etch-stop layer. An optional chemical mechanical polish-stop layer may also be present. The different methods of the invention allow the CMP stop, reactive-ion etch stop, and metal diffusion barrier requirements of the different layers to be decoupled. A preferred conductive material is copper.

Abstract: A method is provided for forming a copper interconnect, the method including forming a sacrificial dielectric layer above a structure layer, forming an opening in the sacrificial dielectric layer and forming a copper layer above the sacrificial dielectric layer and in the opening. The method also includes forming the copper interconnect by removing portions of the copper layer above the sacrificial dielectric layer, leaving the copper interconnect in the opening. The method further includes removing the sacrificial dielectric layer above the structure and adjacent the copper interconnect, and forming a low dielectric constant dielectric layer above the structure and adjacent the copper interconnect.

Abstract: A method to integrate low dielectric constant dielectric materials with copper metallization is described. A metal line is provided overlying a semiconductor substrate and having a nitride capping layer thereover. A polysilicon layer is deposited over the nitride layer and patterned to form dummy vias. A dielectric liner layer is conformally deposited overlying the nitride layer and dummy vias. A dielectric layer having a low dielectric constant is spun-on overlying the liner layer and covering the dummy vias. The dielectric layer is polished down whereby the dummy vias are exposed. Thereafter, the dielectric layer is cured whereby a cross-linked surface layer is formed. The dummy vias are removed thereby exposing a portion of the nitride layer within the via openings. The exposed nitride layer is removed. The via openings are filled with a copper layer which is planarized to complete copper metallization in the fabrication of an integrated circuit device.

Abstract: An improved MOSFET transistor is disclosed having a high dielectric constant gate dielectric and a metal gate electrode. With such a procedure, the known problems with polysilicon gate electrodes on very thin gate oxide transistors are greatly improved, resulting in improved gate threshold voltage control and improved transistor electrical properties, without loss of the benefit of self aligned source and drain electrodes available with polysilicon gates. Dual metal gate electrodes are also disclosed and exhibit improved CMOS transistor function compared to polysilicon gates, resulting in better and more controlled transistor properties. Thus the metal Damascene gate process results in faster and more consistent MOS and CMOS transistors and improved IC fabrication.

Abstract: A method is provided for forming silicided source/drain electrodes in active devices in which the electrodes have very thin junction regions. In the process, adjacent active areas are separated by isolation regions, typically by LOCOS isolation, trench isolation or SOI/SIMOX isolation. A contact material, preferably silicide, is deposited over the wafer and the underling structures, including gate and interconnect electrodes. The silicide is then planed away using CMP, or another suitable planing process, to a height approximate the height of the highest structure. The silicide is then electrically isolated from the electrodes, using an etch back process, or other suitable process, to lower the silicide to a height below the height of the gate or interconnect electrode. The wafer is then patterned and etched to remove unwanted silicide.

Abstract: A new method of forming metal interconnect levels containing damascene interconnects and via plugs in the manufacture of an integrated circuit device has been achieved. The method creates a reversed dual damascene structure. A first dielectric layer is provided overlying a semiconductor substrate. The dielectric layer is patterned to form trenches for planned damascene interconnects. Insulating spacers may optionally be formed on the trench sidewalls. A conductive barrier layer is deposited overlying the dielectric layer and lining the trenches. A metal layer, preferably comprising copper, is deposited overlying the conductive barrier layer and filling the trenches. The metal layer and the conductive barrier layer are polished down to thereby form the damascene interconnects. A passivation layer may optionally be deposited. The damascene interconnects are patterned to form via plugs overlying the damascene interconnects.

Abstract: A new anneal procedure is provided that is applied to copper damascene via interconnects after copper ECP deposition and prior to copper planarization.

Abstract: A method of fabricating dual damascene structure. A substrate having devices and a defined conductive layer is provided. A dielectric layer and a hard mask material layer are formed respectively over the substrate. An opening is defined within the hard mask material layer. Because of the different selectivity of the hard mask material layer and the dielectric layer, a trench is formed within the dielectric layer by defining the hard material mask layer and a portion of dielectric layer until the conductive layer is exposed. The cross shape of the trench has a wider opening and a narrower bottom. A metal layer is then formed and the trench is filled up with the metal layer. The process of dual damascene structure is accomplished..

Abstract: A method for realizing alignment marks on a semiconductor device employs a thicker dielectric layer than in the prior art. The method is used during a manufacturing process including at least a Chemical Mechanical Polishing process step, and includes forming alignment marks on a portion of a semiconductor substrate; masking the marks portion during a further deposition step of a first conductive layer covered by a first dielectric layer; depositing a first conformal metal layer over the first dielectric layer and over the marks portion; depositing a second dielectric layer over the first metal layer; and performing a CMP process step to planarize the second dielectric layer; wherein the thickness of the first dielectric layer is high enough that the second dielectric layer covers the alignment marks portion under the level of the first dielectric top surface thereby preventing the CMP process step to planarize the marks portion.

Abstract: A method and apparatus for mechanical and/or chemical-mechanical planarization of microelectronic substrates. In one embodiment, a conditioning device for removing waste matter from a microelectronic planarizing medium has a support assembly with a support member and a conditioning head attached to the support member. The support member may be a pivoting arm or gantry assembly that carries the condition head over the planarizing medium. The conditioning head may have a non-contact conditioning element that transmits a form of non-contact energy to waste matter on the planarizing medium. The non-contact conditioning element, for example, may be an emitter that transmits a selected waveform capable of penetrating the planarizing medium and the waste matter on the planarizing medium. In operation, the selected non-contact energy may impart energy to the waste matter that weakens or breaks bonds in the waste matter and/or bonds between the planarizing medium and the waste matter.

Abstract: A method for manufacturing an integrated circuit using damascene processes is provided in which planar surfaces of contacting conductive metal channels and vias are subjected to chemical-mechanical polishing under a pressure which avoids cold working and to two steps of chemical-mechanical polishing in which the first step is performed using a slurry with a first sized abrasive to expose a first dielectric layer in which the conductive metal channel is embedded and to provide a planar polished surface of the conductive material, and a second step is performed using a second slurry with a second sized abrasive larger than said first sized abrasive to provide a planar rough-polished surface of the conductive material. The second polishing also performed at a pressure which avoids cold working, which causes a highly polycrystalline structure and a high dislocation density, in the conductive material at its planar polished surface.

Abstract: Metal CMP with reduced dishing and overpolish insensitivity is achieved with an abrasive-free polishing composition having a pH and oxidation-reduction potential in the domain of passivation of the metal and, therefore, a low static etching rate at high temperatures, e.g., higher than 50° C. Embodiments of the present invention comprise CMP of Cu film without any abrasive using a composition comprising one or more chelating agents, one or more oxidizers, one or more corrosion inhibitors, one or more agents to achieve a pH of about 3 to about 10 and deionized water.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. After planarization of the conductor core and the barrier layer, a plasma treatment is performed at 300° C. to reduce the conductor core material. A portion of a cap layer is deposited at 300° C. and the remainder is deposited at 400° C.

Abstract: There is provided a method for forming fine metal patterns of semiconductor devices using damascene technique. In the method, a glue layer and a diffusion barrier film are formed on a lower layer, in turn. An insulating film is then deposited on the barrier film and etched to form contact holes or via holes. A metal film is then deposited within the hole to form a fine metal pattern. Therefore, the method can increase the width of the metal film of the fine pattern, thereby enhancing the operation speed of the device. The method can also easily control the processes by separating the etching process of the metal film from those of the glue layer and the barrier film.

Abstract: This invention discloses a planarization method for semiconductor device. The planarization method includes the steps of: providing a semiconductor substrate in which metal patterns are formed with various pattern densities; depositing a porous oxide layer over the semiconductor substrate so as to cover the metal patterns; plasma-treating surface of the porous oxide layer; and polishing the plasma-treated porous oxide layer by chemical mechanical polishing.

Abstract: The present invention provides a method for manufacturing a semiconductor device with an anti-reflective coating (ARC) that does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. A dielectric layer is then deposited over the electrical devices and the semiconductor substrate, upon which an optically transparent ARC layer of low dielectric constant is then deposited. Photoresist is then deposited on top of the ARC layer and is then photolithographically processed and subsequently developed. The dielectric layer is then etched down to the semiconductor substrate to form contacts or local interconnects. The ARC layer can subsequently be used as a hard mask and does not require removal.

Abstract: A method for the fabrication of a semiconductor device which prevents the occurrence of a defective die and an erroneous alignment otherwise invoked by a difference in polishing level between an edge and a central portion of a wafer. The method comprises steps of forming a group of dummy patterns around an alignment key of edges of a wafer, wherein the wafer is obtained by forming the capacitor on the cell region, and the dummy pattern has the same elevation as the capacitor formed on the cell region; disposing an interlayer insulating film on a resulting structure obtained after the forming process; and performing a chemical-mechanical polishing on the interlayer insulating film. Further, the process of forming the group of dummy patterns may be performed while forming the capacitor on the cell region.

Abstract: A process for creating a dual damascene structure without needing an etch stop is disclosed.

Abstract: The invention relates to an abrasive containing a slurry of the following cerium oxide grains as dispersed in water:

Abstract: A method and apparatus is provided for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer wherein the circuitry on the chips on the wafer are either designed to be within a defined high metal density circuit range and low density metal circuit range and/or to provide dummy circuitry in the damascene process to provide a substantially uniform circuit density over the chip and the wafer surface. It is preferred that each chip on the surface of the wafer be divided into a plurality of regions and that each region be provided with dummy metallization, if necessary, to provide a relatively uniform circuit density in that region and consequently on the wafer surface. The invention also contemplates adding dummy circuitry to the periphery of the wafer in areas which are not formed into chips (chip fragments). The invention also provides semiconductor wafers made using the method and/or apparatus of the invention.

Abstract: A method for improving non-uniformity of chemical mechanical polishing by over coating layer is disclosed. The essential point of the invention is that an over coating layer is formed over a surface before the surface is planarized by a chemical mechanical polishing process. Note that polishing rate of the over coating layer must be less than the polishing rate of the surface, where the ratio of polishing rate is called as selectivity. Because the topography of the surface is not uniform, the topography of the over coating layer also is non-uniform and then the polishing probability in different parts of the over coating layer is different. Obviously, when the over coating layer on the higher area part of the surface is totally consumed, these are residual over coating layer on the lower area part of the surface. Thus, over polishing in the lower area part is prevented by residual over coating layer.

Abstract: A novel dielectric composition is provided that is useful in the manufacture of electronic devices such as integrated circuit devices and integrated circuit packaging devices. The dielectric composition is prepared by crosslinking a thermally decomposable porogen to a host polymer via a coupling agent, followed by heating to a temperature suitable to decompose the porogen. The porous materials that result have dielectric constants less than about 3.0, with some materials having dielectric constants less than about 2.5. Integrated circuit devices, integrated circuit packaging devices, and methods of manufacture are provided as well.

Abstract: A method for forming a multilayer interconnection structure on a wafer by using a damascene technique includes the steps of separating the area of the wafer into a peripheral area, an intermediate area and a central area as viewed from the outer periphery toward the center of the wafer The lower-level interconnections having a smaller width are formed in the intermediate and central areas, whereas the upper-level interconnections having a larger width are formed in the central area.

Abstract: A method for forming a metal line in a semiconductor device, in which a resolution is improved for securing a design rule and minimizing a difference of critical dimensions, including the steps of (1) forming a first insulating film and a second insulating film on a substrate, (2) etching the second insulating film to form a second insulating film pattern, (3) depositing a third insulating film on the second insulating film pattern, (4) removing the second insulating film pattern, and (5) forming a metal line layer in a region having the second insulating film pattern removed therefrom.

Abstract: A method for forming a passivation layer on at least one copper conductive element in a semiconductor structure and the devices formed are described. In the method, after a top surface of a semiconductor device that contains copper conductors embedded in an insulating layer is first planarized by a chemical mechanical polishing method, an etching process is conducted to create a stepped or corrugated surface between the surface of the copper conductor and the surface of the insulating layer, so that when a passivation layer is later deposited on top of the semiconductor structure, the same stepped or corrugated surface is reproduced in the passivation layer and thus providing a mechanical interlock between the passivation layer and the copper conductor for preventing adhesion failure or peeling of the passivation layer from the surface of the semiconductor structure.

Abstract: A method of reworking copper metallurgy on semiconductor devices which includes selective removal of insulator, selective removal of copper, non-selective removal of copper and insulator followed by the redeposition of an insulating copper barrier layer and at least one metallurgical interconnect layer.

Abstract: The dual damascene method having steps of; after a first insulating film, a first organic insulating film, a second insulating film, and a metal film are formed in sequence, a first opening having a wiring pattern is formed in the metal film, then a second opening having a via pattern is formed in the second insulating film, then the first organic insulating film is etched using the second insulating film as a mask, then the first insulating film and the second insulating film are etched simultaneously while using the metal film and the first organic insulating film as a mask, and then the first organic insulating film is etched while using the metal film as a mask, at this stage, a wiring recess is formed in the first organic insulating film and the second insulating film, and a via-hole is formed in the first insulating film.

Abstract: The present invention relates to a method of integrating a low dielectric material such as DLC into a dual or single damascene wiring structure which contains a dielectric material having a dielectric constant of 4.0 or above. This integration is achieved in the present invention by employing a step of etchingback the high dielectric constant material to expose regions of in-laid wiring present in the single or dual damascene structure. Damascene wiring structures, single or dual, prepared using the method of the present invention are also provided herein.

Abstract: An insulating layer is formed on a semiconductor element fabricated in a semiconductor substrate. A groove, with a connecting hole at the bottom part thereof when required, is formed in the insulating layer. A barrier layer is formed on the inner surface of the groove, and the connecting hole, and on the insulating layer. A conductive layer is formed in the groove and on the insulating layer, and is buried into the groove by applying high temperature and high pressure. Then, the conductive layer on the insulating layer is polished to leave the conductive layer in the groove by a CMP method to form an electrodes wire composed of the conductive layer material.

Abstract: In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.

Abstract: An integrated circuit manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. The conductor core and barrier layer are chemical-mechanical polished. The dielectric layer is then chemically-mechanically polished using a slurry containing ceria, a Ce(IV) oxide. Residual ceria on the conductor core and dielectric layer is then removed using a reducing agent to react the Ce(IV) oxide to the Ce(III) oxide for removal in an aqueous solution.

Abstract: A method is described for cleaning freshly etched dual damascene via openings and preparing them for copper fill without damage or contamination of exposed organic or other porous low-k insulative layers. The method is entirely dry and does not expose the porous materials to contamination from moisture or solvents. The method is effective for removing all traces of residual polymer deposits from an in-process substrate wafers after via or damascene trench etching. The method employs an in-situ three-step treatment comprising a first step of exposing the electrically biased substrate wafer to a O2/N2 ashing plasma to remove photoresist and polymers, a second step immediately following the first step of remove silicon nitride etch stop layers, and a final step of treating the wafer with H2/N2 to remove copper polymer deposits formed during nitride removal. The H2/N2 plasma is capable of removing the difficult polymer residues which are otherwise only removable by wet stripping procedures.

Abstract: A fabrication method for a dual damascene structure is described wherein a substrate covered by a HSQ layer is provided. An E-beam curing is conducted on the HSQ layer where the via hole is to be formed. Photolithography and etching are further conducted on the HSQ layer to form a trench. Since the E-beam cured HSQ layer and the thermally cured HSQ layer have a high etching selectively ratio, the HSQ layer that has not been E-beam cured can be wet etched to from a via hole. A dual damascene structure is formed after filling the trench and the via hole with a conductive material, wherein either the via hole or the trench can be first formed.

Abstract: A method is used to form a borderless via in a semiconductor device. A conductive layer, a borophosphosilicate glass (BPSG) layer and a patterned first mask layer are formed on a dielectric layer in sequence. The BPSG layer is patterned into a BPSG plug while using the patterned first mask layer as a mask. A second mask layer is formed to cover the patterned first mask layer and the metal layer. The conductive layer is defined to form a conductive line beneath the BPSG plug and the second mask layer. The first and second photoresist mask layers are removed. An inter-metal dielectric layer is formed around the BPSG plug and the conductive line. A via is formed in the inter-metal dielectric layer by removing the BPSG plug. A barrier layer and a metal layer fill the via to form a metal plug.

Abstract: The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized metallization patterns, e.g., of copper, in-laid in the exposed upper surface of a layer of dielectric material, are enhanced by a process comprising blanket-depositing on the planarized, exposed upper surfaces of the metallization features and the dielectric layer at least one thin layer comprising at least one passivant element for the metal of the features, reacting the at least one passivant element to chemically reduce any deleterious oxide layer present at the upper surfaces of the metallization features, and diffusing the at least one passivant element for a distance below the upper surface to form passivated top interfaces. The passivated top interfaces advantageously exhibit reduced electromigration and improved adhesion to overlying metallization with lower ohmic contact resistance.

Abstract: The formation and/or growth of dendrites emanating from Cu or Cu alloy lines into a bordering open dielectric field are prevented or substantially reduced by chemically removing a portion of the surface from the dielectric field and from between the lines after CMP by spraying the wafer with a chemical agent. Embodiments include removing up to 60Å of silicon oxide by spraying the wafer with an acidic solution, such as a solution comprising acetic acid and ammonium fluoride.

Abstract: A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of metal alloy which contains alloy dopant precipitates, and performing a first anneal of the integrated circuit to drive the alloy dopants into solid solution. The metal is quenched to prevent the alloy dopants from coming out of solution prior to removing excess metal alloy with a polish process. To improve conductivity after polishing, the dopants are allowed to come out of solution. The metal alloy is described as aluminum with alloy dopants of silicon and copper where the first anneal is performed at 400 to 500° C. This process is particularly applicable to fabrication of interconnects formed using a dual damascene process. The integrated circuit is described as any circuit, but can be a memory device such as a DRAM.

Abstract: In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.

Abstract: The present invention relates to semiconductor devices. More specifically, the invention discloses the use of dummy structures to improve thermal conductivity, reduce dishing and strengthen layers formed with low dielectric constant materials.

Abstract: An interconnect opening of an integrated circuit is filled with a conductive fill with the interconnect opening being within an insulating layer on a semiconductor wafer. A seed layer of a first conductive material is deposited conformally onto sidewalls and a bottom wall of the interconnect opening. The interconnect opening is further filled with a second conductive material by growing the second conductive material from the seed layer to form a conductive fill of the first conductive material and the second conductive material within the interconnect opening. The first conductive material and the second conductive material are comprised of a bulk metal, and at least one of the first conductive material and the second conductive material is a metal alloy having an alloy dopant in the bulk metal. In addition, a plasma treatment process is performed to remove any metal oxide or metal hydroxide from a top surface of the conductive fill.

Abstract: A method for forming a damascene structure over tungsten plugs using nitridation of said tungsten plugs to provide better oxidation resistance, better adhesion properties and better copper diffusion barrier proerties. The process begins by providing a substrate structure having at least one device layer thereon and having a first dielectric layer overlying the device layer. The dielectric layer has tungsten plugs therein providing a conductive path between the surface of the dielectric layer and the device layer. The tungsten plugs are nitriduzed to form a WNx layer on top of the tungsten plugs. A second dielectric layer is deposited over the WNx layer and the first dielectric layer. The second dielectric layer is patterned to form a trench in the second dielectric layer; whereby the WNx layer is exposed in the trench. A barrier layer is formed in the trench. A metal layer is formed over the barrier layer. The metal layer and the second dielectric layer are planarized to form a damascene structure.

Abstract: A method of polishing a metal film which is used for forming damascene wirings or conductors by polishing a metal film formed on an insulating film having trenches thereon by using a CMP, in which excess polishing, that is, dishing, of buried conductors having large area occurring when the metal film is polished by the CMP method can be restrained. The method comprises: providing a substrate on which an insulating film is formed; forming a trench in the insulating film; forming a buried metal film portion in the trench whose width is equal to or larger than 1 micrometer; forming a first metal film on the insulating film such that the buried metal film portion is covered by the first metal film; and polishing a surface of the first metal film by using a CMP method.

Abstract: According to an example embodiment, the present invention is directed to a method for manufacturing a semiconductor device. The device includes a conductive underlayer. A sub-micron via or contact path and a dummy via or dummy contact path are dry etched. The endpoint of the dry etching process is optically detected, and the etching process is stopped responsive to the detection of the endpoint. By etching a dummy via or contact in addition to the submicron via or contact, this example embodiment facilitates endpoint detection for dry etching sub-micron features in semiconductor devices, which is otherwise difficult or even impossible in the submicron regime.

Abstract: A method for creating metal layers in a microelectronic device where air is the primary dielectric separating adjacent metal features within a layer. A temporary structural solid, such as a photoresist, is deposited on a substrate with exposed metal features. The photoresist is etched back to expose at least the top surfaces of the metal features. A porous dielectric is then deposited on the substrate and cured to stabilize the structure. The substrate is then treated with a supercritical fluid, such as supercritical CO2, to extract the photoresist through the pores of the porous dielectric layer.

Abstract: Capping layer adhesion to a Cu or Cu alloy interconnect member is enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with a hydrogen plasma to substantially reduce oxides thereon, forming a thin layer of copper silicide on the treated surface and depositing the capping layer thereon. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric layer, chemical-mechianiical polishing, hydrogen plasma treatment, reacting the treated surface with silane or dichlorosilane to form a layer of copper silicide on the treated surface and depositing a silicon nitride capping layer on the thin copper silicide layer.

Abstract: A cleaning solution for cleaning a semiconductor substrate is formed by mixing an amount of citric acid and an amount of ammonia in deionized water. In one embodiment, the amount of citric acid is in a range from about 0.18% by weight to about 0.22% by weight and the amount of ammonia is in a range from about 0.0225% by weight to about 0.0275% by weight, and the cleaning solution has a pH of about 4. A method for cleaning a semiconductor substrate having a polished copper layer in which a concentrated cleaning solution is mixed with deionized water proximate to a scrubbing apparatus also is described.

Abstract: A method of fabricating a dummy pattern is proposed. A semiconductor substrate is divided into a dense region and a sparse region. Conducting patterns are formed on the dense region. A dielectric layer is formed over the substrate and the conducting patterns. Photoresist patterns are formed on the dielectric layer above the sparse region. The dielectric layer is etched back to form a plurality of spacers on the sidewall of the conducting patterns, and simultaneously, a plurality of dummy patterns are formed on the sparse region.

Abstract: A method of fabricating bit lines is described. A semiconductor substrate has isolation structures formed therein. Gate structures are formed over the semiconductor substrate. Each gate structure comprises a conducting gate layer and a cap layer on the conducting gate layer. A common source and a drain is formed in the semiconductor substrate. A spacer is formed on the sidewall of each gate structure. A dielectric layer is formed over the semiconductor substrate. The dielectric layer is patterned to form bit line contact holes and bit line trenches, wherein the bit line contact holes expose the common sources, and the bit line trenches expose a part of the cap layer and a part of the isolation structures. The bit line contact holes and the bit line trenches are filled with a conducting layer; consequently, bit line contacts and patterned bit lines are formed.