Abstract: A dielectric barrier sidewall protected via in combination with a conventional metal barrier is integrated in a dual damascene process. Via reliability, copper filling ability and copper CMP uniformity will be significantly improved according to this invention.

Abstract: Disclosed is a multilayer integrated circuit structure joined to a chip carrier, and a process of making, in which the area normally occupied by a solid dielectric material in the IC is at least partially hollow. The hollow area can be filled with a gas, such as air, or placed under vacuum, minimizing the dielectric constant. Several embodiments and processing variants are disclosed. In one embodiment of the invention, the wiring layers, which are embedded in a temporary dielectric, alternate with via layers, also embedded in a temporary dielectric, in which the vias, besides establishing electrical communication between the wiring layers, also provide mechanical support for after the temporary dielectric is removed. Additional support is optionally provided by support structures though the interior levels and at the periphery of the chip. The temporary dielectric is removed subsequent to joining by dissolution or by ashing in an oxygen-containing plasma.

Abstract: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting an oxidizable silicon containing compound or mixture comprising an oxidizable silicon component and an oxidizable non-silicon component having thermally liable groups with nitrous oxide, oxygen, ozone, or other source of reactive oxygen in gas-phase plasma-enhanced reaction. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a low-density structure. The nano-porous silicon oxide based films are useful for forming layers between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures.

Abstract: The present invention provides a method of manufacturing an integrated circuit including planarizing a semiconductor wafer surface. In one embodiment, the method comprises forming a dielectric layer over a first level having an irregular topography, depositing a sacrificial material over the dielectric layer, and then planarizing the semiconductor wafer surface to a planar surface. More specifically, the dielectric layer forms such that it substantially conforms to the irregular topography of the first level. The sacrificial material is formed to a substantially planar surface over the dielectric layer. Thus, the sacrificial material provides a substantially uniform chemical/mechanical planarization (CMP) process removal rate across the semiconductor wafer surface. In the ensuing step, planarizing the semiconductor wafer surface to a planar surface removes the sacrificial material and a portion of the dielectric layer with a CMP process.

Abstract: Metal/metal contacts are formed as part of a multilayer metallization in an integrated circuit on a semiconductor wafer. The application of an insulation layer on a metal level is followed by a lithography step using a photoresist mask to define contact holes on the insulation layer, followed by anisotropic etching of the insulation layer in order to produce the contact holes. Then, a chemical dry etch that removes the photoresist mask and a chemical-physical dry etch that removes organic impurities which accumulate during the chemical dry etch are successively carried out in a vacuum. Subsequently, a metal deposition step is carried out in order to fill the contact holes.

Abstract: A method for forming a wire in a semiconductor device, in forming a titanium film and a titanium nitride film as a barrier metal layer, which can deposit a titanium film and a titanium nitride film each in a different chamber by removing a titanium oxide film used as an insulating film made of upper titanium bonding with oxygen in air as the upper portion of a titanium film is exposed to air by a plasma process and then depositing a titanium nitride film, and as a result can reduce the throughput time of chamber equipment since the partial utilization of the system of the chamber equipment is enabled by driving another chamber even in case one of the chambers breaks down.

Abstract: A metal-containing layer is formed on a substrate. A mask layer is formed on the metal-containing layer. The mask layer is patterned by way of a lithographically fabricated mask. The metal-containing layer is patterned with the patterned mask layer, to thereby form an electrode out of the metal-containing layer. A protective layer is deposited on the mask layer and on the substrate. The protective layer undergoes chemical mechanical polishing, during which the protective layer is removed and the electrode is uncovered.

Abstract: A method of forming a cooper damascene interconnect. First, a metal and a dielectric layer are formed on a substrate in sequence. Next, a damascene opening is formed in the dielectric layer. A metal barrier/Cu seed layer is then formed on the dielectric layer conformally. CMP is performed to remove parts of the metal barrier/Cu seed layer covering on the surface of the dielectric layer. A chemical electroplating is performed to form a Cu layer filling the damascene opening on the metal barrier/Cu seed layer. Finally, CMP is performed.

Abstract: A planarization method includes providing a second and/or third Group VIII metal-containing surface (preferably, a platinum-containing surface) and positioning it for contact with a polishing surface in the presence of a planarization composition that includes an oxidizing gas.

Abstract: A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.

Abstract: The present invention relates to methods for repairing defects on a semiconductor substrate. This is accomplished by selectively depositing the conductive material in defective portions in the cavities while removing residual portions from the field regions of the substrate. Another method according to the present invention includes forming a uniform conductive material overburden on a top surface of the substrate. The present invention also discloses a method for depositing a second conductive material on the first conductive material of the substrate.

Abstract: In a dual-gate MOSFET process, the first gate oxide is covered by a protective layer of poly that will become the transistor gate while the second gate oxide thickness is formed and, in turn, covered by a second protective layer of poly that will become the second transistor gate, the two protective layers being patterned simultaneously to form first and second sets of gates having first and second gate dielectric thicknesses, respectively.

Abstract: A process of removing excess conductive material from the exposed surface of a dielectric layer, the process comprising the steps of forming a shield layer on the dielectric layer, forming a sacrificial layer on top of the shield layer, depositing the conductive material on top of the sacrificial layer so that the conductive material is positioned within cavities in the dielectric material, and then using chemical mechanical planarization to remove the excess conductive material and the sacrificial layer. The use of a sacrificial layer interposed between the shield layer and the excess conductive material allows for chemical mechanical planarization to fully remove the sacrificial layer to facilitate more uniform removal of excess conductive material.

Abstract: In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type A—X—Y, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.

Abstract: A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.

Abstract: Before polishing an insulating interlayer film by a CMP process, conductor plugs as erosion-inducing portions are formed on a convex surface of the film. Erosion occurs in the convex surface upon the CMP process, and the residual-free flat surface of insulating interlayer film can be obtained.

Abstract: A method for fabricating a via openings, comprising the following steps. A semiconductor structure is provided. A low-k layer is formed upon the semiconductor structure. A via opening is formed within the low-k layer. An inert polymer liner layer is formed upon the low-k layer and within the via opening. A photoresist layer is formed upon the inert polymer liner layer, filling the inert polymer lined via opening. The inert polymer liner layer preventing adverse chemical reactions between the photoresist layer and portions of the low-k layer. The photoresist layer is patterned to expose the inert polymer lined via opening and portions of the inert polymer lined low-k layer adjacent the via opening. The exposed inert polymer lined via opening and portions of the inert polymer lined low-k layer adjacent the via opening and the portions of the inert polymer liner layer upon the via opening and portions of the inert polymer lined low-k layer adjacent the via opening are etched to form a structure opening.

Abstract: A method of forming a dual damascene structure. A substrate has a conductive line thereon. A first dielectric layer, a second dielectric layer, a base anti-reflection coating and a spin-on dielectric layer are sequentially formed over the substrate. The spin-on dielectric layer, the base anti-reflection coating and the second dielectric layer are patterned to form an opening in the second dielectric layer and a first trench in the spin-on dielectric layer and the base anti-reflection coating. Using the spin-on dielectric layer and the base anti-reflection coating as a mask, the exposed first dielectric layer within the opening is removed to form a via opening that exposes a portion of the substrate. The exposed second dielectric layer within the first trench is also removed to form a second trench that exposes a portion of the first dielectric layer. Thereafter, the spin-on dielectric layer and the base anti-reflection coating are removed.

Abstract: A method for fabricating metal interconnects, in which a dielectric layer is formed over a substrate and then an opening is formed in the dielectric layer, is described. A metal layer is formed to fill the opening and then a protective layer is form on the surface of the metal layer by an electrochemical method. Thereafter, the protective layer and the metal layer outside the opening are removed to complete the metal interconnect process. Since the protective layer is more stable than the metal layer so that oxidation of the metal layer can be prevented, the queue time (Q-time) between the metal deposition process and the chemical mechanical polishing (CMP) process can be increased with more flexibility.

Abstract: The present invention generally provides an improved process for depositing silicon carbide, using a silane-based material with certain process parameters, onto an electronic device, such as a semiconductor, that is useful for forming a suitable barrier layer, an etch stop, and a passivation layer for IC applications. As a barrier layer, in the preferred embodiment, the particular silicon carbide material is used to reduce the diffusion of copper and may also used to minimize the contribution of the barrier layer to the capacitive coupling between interconnect lines. It may also be used as an etch stop, for instance, below an intermetal dielectric (IMD) and especially if the IMD is a low k, silane-based IMD. In another embodiment, it may be used to provide a passivation layer, resistant to moisture and other adverse ambient conditions. Each of these aspects may be used in a dual damascene structure.

Abstract: A method for fabricating a semiconductor device in which a wiring having a thickness with a high uniformity can be formed in the process of wiring formation using a dual damascene technology. In the method, an insulating film being patterned is formed on a semiconductor wafer, followed by forming a Cu film on both a wiring formation area which the insulating film is not formed and said insulating film. Then, the Cu film is mechanically polished until a step caused by a wiring layout is disappeared. After that, the Cu film on the insulating film is polished using chemical and mechanical polishing procedures to form a wiring made of the Cu film in the wiring formation area.

Abstract: The invention relates to the formation of structures in microelectronic devices such as integrated circuit devices by means of borderless via architectures in intermetal dielectrics. An integrated circuit structure has a substrate, a layer of a second dielectric material positioned on the substrate and spaced apart metal contacts are on the layer of the second dielectric material. The metal contacts have side walls, and a lining of a first dielectric on the side walls; a space between the linings on adjacent metal contact side walls filled with the second dielectric material, a top surface of each of the metal contacts, the linings and the spaces are at a common level. An additional layer of the second dielectric material is on some of the metal contacts, linings and filled spaces. At least one via extends through the additional layer of the second dielectric material and extends to the top surface of at least one metal contact and optionally at least one of the linings.

Abstract: A method for forming contacts in a semiconductor device including a plurality of active devices formed over a substrate that includes depositing a first layer of dielectric material over the substrate and plurality of active devices, forming a first opening in the first layer of dielectric material, depositing a second layer of dielectric material over the first layer of dielectric material and in the first opening, providing a mask over the second layer of dielectric material, wherein the mask material is distinguishable over silicon oxides, and forming a second opening and a third opening in the second layer of dielectric material, wherein the second opening is aligned with the first opening and exposes a first silicide of a first active device, and the third opening exposes one of diffused regions of a second active device.

Abstract: A method for forming a uniform damascene profile is provided. A wet etching process using a mixture containing ionized water, hydrochloric acid and hydrofluoric acid as an etching solution is applied on a substrate having a single/dual damascene structure formed thereon. The etching solution of the mixture containing ionized water, hydrochloric acid and hydrofluoric acid creates an etch selectivity between various layers of the single/dual damascene structure approximately 1:1. Thus, a damascene structure with a good profile is obtained.

Abstract: A method of chemical mechanical polishing of a metal damascene structure which includes an insulation layer having trenches on a wafer and a metal layer having a lower portion located in trenches of the insulation layer and an upper portion overlying the lower portion and the insulation layer is provided. The method comprises a first step of planarizing the upper portion of the metal layer and a second step of polishing the insulation layer and the lower portion of the metal layer. In the first step of planarizing the upper portion of the metal layer, the wafer and a polishing pad is urged at an applied pressure p and a relative velocity v in a contact mode between the wafer and the polishing pad to promote an increased metal removal rate. In the second, the insulation layer and the lower portion of the metal layer are polished in a steady-state mode to form individual metal lines in the trenches with minimal dishing of the metal lines and overpolishing of the insulation layer.

Abstract: An inter-level insulator structure is provided having an effective insulator dielectric constant approaching 1. An embodiment of the inter-level insulator comprises a first metal layer comprising a first plurality of metal lines; a second metal layer comprising a second plurality of metal lines, and at least one via connected to the first metal layer; and an air gap interposed between the first metal layer and the second metal layer. In one embodiment, the air gap is also present between metal lines on either metal layer, such that air gaps act as intra-level as well as inter-level insulators. A method is also provided to deposit and pattern a sacrificial polymer, and form metal layers. The sacrificial polymer is capable of being decomposed to become air gaps during annealing.

Abstract: A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

Abstract: A semiconductor substrate has features extending above the surface. In one use, these features are gate stacks in which the gate is polysilicon to be replaced by metal. A dielectric is deposited over the substrate and the gate stacks having contours corresponding to the features. The desired structure prior to replacing the polysilicon gates is for the dielectric to be planar and even with the top of the gate stack. This is difficult to achieve with conventional CMP procedures because of varying polish rates based on the area and density of these features. The desired planarity is achieved by first depositing a conformal sacrificial layer. A CMP step using light downforce results in exposing and planarizing the underlying contours of the dielectric layer. A subsequent CMP step using higher downforce achieves the desired planar structure by providing a greater polish rate for the dielectric layer than for the sacrificial layer.

Abstract: A process for fabricating a semiconductor device having a multilayer wiring, comprising steps of: forming a first wiring or electrode on a substrate; forming an insulating film which covers the first wiring or electrode; forming a contact hole to the first wiring or electrode through the insulating film; forming a wiring for contacting the first wiring or electrode inside the contact hole; and removing the protruded portion of the contact wiring and flattening the insulating film at the same time in an electrolytic solution by means of chemical mechanical polishing using the contact wiring as the anode. Also claimed is an apparatus for polishing the surface of a semiconductor device during its fabricating the device, comprising: means for performing chemicomechanical polishing; and means for supplying electric current to the electrode of the semiconductor device.

Abstract: A semiconductor device includes first and second conductive layers which are electrically connected to each other through a contact plug. A first insulating film is formed on the first conductive layer and has a first opening which reaches the surface of the first conductive layer. A second insulating film is formed on the first insulating film and has a second opening at the same position as the first opening. The contact plug is filled in the first and second openings and has the surface which is substantially flush with the surface of the second insulating film and also contains a metal having a high melting point. The second conductive layer is formed on the second insulating film and on the contact plug.

Abstract: A first layer metal wire, an SiOF film and an F diffusion prevention film are formed on a surface of a base layer including a substrate, elements formed on the substrate and an insulator layer formed to cover the substrate and the elements. The F diffusion prevention film may be prepared from a silicon oxynitride film or a silicon oxide film containing Si—H bonds. A spacer film is formed on a surface of the F diffusion prevention film and its surface is flattened. A second layer metal wire is formed on a surface of the spacer film. Thus implemented is a semiconductor device comprising an F diffusion prevention film preventing F atoms contained in an SiOF film from diffusing into an upper metal wire with the F diffusion prevention film not etched in formation of the upper metal wire and a method of manufacturing a semiconductor device not directly polishing an SiOF film by CMP.

Abstract: Within a damascene method for forming a patterned conductor layer within an aperture defined by a patterned dielectric layer within a microelectronic fabrication, at least one of: (1) the patterned dielectric layer is thermally annealed at a temperature of from about 300 to about 450 degrees centigrade prior to forming within the aperture the patterned conductor layer; and (2) the aperture is etched with a plasma employing an etchant gas composition comprising hydrogen to form a laterally enlarged aperture prior to forming within the laterally enlarged aperture the patterned conductor layer. In accord with the method, the microelectronic fabrication is formed with decreased contact resistance and enhanced structural integrity.

Abstract: A method for making a semiconductor device is described. That method comprises forming a carbon doped oxide containing layer and a dielectric layer on a substrate, such that at least part of the dielectric layer is located above at least part of the carbon doped oxide containing layer. A chemical mechanical polishing process is then applied to remove the part of the dielectric layer that is located above the part of the carbon doped oxide containing layer, such that it removes the dielectric layer at a significantly faster rate than it can remove the carbon doped oxide containing layer.

Abstract: A method of copper metallization wherein copper flaking and metal bridging problems are eliminated by an annealing process is described. A first metal line is provided on an insulating layer overlying a semiconductor substrate. A dielectric stop layer is deposited overlying the first metal line. A dielectric layer is deposited overlying the dielectric stop layer. An opening is etched through the dielectric layer and the dielectric stop layer to the first metal line. A barrier metal layer is deposited over the surface of the dielectric layer and within the opening. A copper layer is deposited over the surface of the barrier metal layer. The copper layer and barrier metal layer not within the opening are polished away wherein after a time period, copper flakes form on the surface of the copper and dielectric layers.

Abstract: A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.

Abstract: A damascene structure, and a method of fabricating same, containing relatively low dielectric constant materials (e.g., k less than 3.8). A silicon-based, photosensitive material, such as plasma polymerized methylsilane (PPMS), is used to form both single and dual damascene structures containing low k materials. During the manufacturing process that forms the damascene structures, the silicon-based photosensitive material is used as both a hard mask and/or an etch stop.

Abstract: A simple to manufacture conductor structure is described which requires only a small number of process steps. The conductor structure contains a structured, first insulating layer to which a first passivation layer is applied. A layer of conductive material is applied thereto and in turn a second passivation layer is applied to the layer of conductive material. A hard mask is applied to the second passivation layer. The layer of conductive material is removed in regions defined by the hard mask. The first passivation layer is removed in the regions defined by the hard mask by sputtering and is at least partially deposited again on the side wall of the layer of conductive material.

Abstract: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting an oxidizable silicon containing compound or mixture comprising an oxidizable silicon component and an oxidizable non-silicon component having thermally labile groups with nitrous oxide, oxygen, ozone, or other source of reactive oxygen in gas-phase plasma-enhanced reaction. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a low-density structure. The nano-porous silicon oxide based films are useful for forming layers between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures.

Abstract: A method of manufacturing a trench conductor line. An etching stop layer, a dielectric layer and a polishing stop layer are sequentially formed over a substrate. The polishing stop layer and the dielectric layer are patterned to form a trench that exposes a portion of the etching stop layer. A conformal dielectric layer is formed over the polishing stop layer and the interior surface of the trench. A portion of the conformal dielectric layer is removed to expose the polishing stop layer and the etching stop layer within the trench. A conductive layer is formed over the polishing stop layer filling the trench. The conductive layer is planarized using the polishing stop layer as a polishing stop.

Abstract: A method for making a semiconductor device is described. That method includes forming a dielectric layer on a substrate, then etching a trench into the dielectric layer. After filling the trench with copper, a portion of the copper is removed to form a recessed copper plug within the dielectric layer. A capping layer that comprises aluminum is then formed on the recessed copper plug.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen.

Abstract: Recesses between gate layer stacks are filled with a first electrically insulating material. Cavities or voids are opened up during the removal of a portion of the first insulating material. These voids are filled during the application of a conductive layer and can then lead to short circuits. Inventively, a layer for closing up voids is produced before the conductive material is applied, as a result of growing a second electrically insulating material onto the surface of the remaining first insulating material. This second insulating layer closes up voids that have formed in the first insulating material so that they can no longer lead to short circuits. In particular, voids that are difficult to gain access to and open out into side walls of contact holes can in this way be closed up in a simple manner.

Abstract: A method for making electrical contacts to device regions in a semiconductor substrate, and the resulting structure, is presented. A first set of borderless contacts is initially formed. This first set of contacts is then contacted by a second series of smaller, upper-level contacts. The second set of contacts also contact the gate of the device. The structure which results has a form wherein there are stacked contacts to the diffusion layer, and a single level contact to the device gate. The structure further provides local interconnectability over gate structures.

Abstract: Deleterious poisoning of patterned photoresist masking layers accompanying plasma ashing/etching of photoresist and/or low-k dielectric layers is eliminated, or at least substantially reduced, by pretreating exposed surfaces of the low-k dielectric layer(s) with hydrogen, e.g., by contact with a hydrogen plasma prior to plasma ashing/etching. The invention enjoys particular utility in the formation of dual damascene openings in dielectric layers as part of metallization processing of semiconductor IC devices.

Abstract: A method of manufacturing a semiconductor apparatus includes the step (a) to the step (f). In the step (a), an insulation film is formed on a semiconductor substrate. In the step (b), a wiring trench is formed which extends to the insulation film. In the step (c), a first conductive film is formed which covers an inner surface of the wiring trench and covers the insulation film. In the step (d), a second conductive film is formed which fills the wiring trench and covers the first conductive film. In the step (e), the second conductive film is removed by chemical mechanical polishing (CMP) until a surface of the first conductive film is exposed. In the step (f), a surface of the second conductive film is polished by using a first solution such that a first protective film for protecting the second conductive film is formed. In the step (g), the first conductive film and the second conductive film is removed by CMP until a surface of the insulation film is exposed.

Abstract: In fabrication of integrated circuits, trenches (184) are formed in a dielectric (170), then a metal (e.g. tungsten or copper) is deposited. The metal (194) is removed from the top surface of the dielectric by a polishing process (e.g. CMP). The metal remains in the trenches. The inventor has discovered that the erosion of the structure in the polishing process does not strongly depend on the size of the structure. Therefore, the erosion of a large structure (440) can be estimated by measuring the erosion of a smaller test structure (450). The erosion of the test structure is measured by a probe instrument (230), e.g. a stylus profilometer or a scanning probe microscope. Use of the test structure reduces the probability of damaging the larger structure by the probe. Other embodiments are also provided.

Abstract: A method for fabricating a semiconductor device is disclosed, which reduces defects of a device by improving the process to improve the production yield.

Abstract: Compositions and methods for processing (e.g., cleaning) substrates, such as semiconductor-based substrates, as well as processing equipment, include one or more compounds of Formula (I): wherein each R1, R2, R3, and R4 is independently H or an organic group.

Abstract: A process produces at a predetermined metallization level at least one metal track (7) within an intertrack dielectric material (1). The process includes the steps of etching the intertrack dielectric material (1) so as to form a cavity (4) at the position of the track, depositing a conducting barrier layer (5) in the cavity (4), filling the cavity (4) with copper, and depositing a silicon nitride layer (8) on the predetermined metallization level. Between the barrier layer deposition step and the copper filling step, titanium is deposited on at least part of the barrier layer. This titanium will be transformed into TiSi2 (60) during the diffusion of the silicon from the silicon nitride layer (8).

Abstract: An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked container capacitor. The present invention develops the container capacitor by etching an opening (or contact opening) into a low etch rate oxide. The contact opening is used as a form for deposited polysilicon that conforms to the sides of the opening walls. Within the thin poly lining of the oxide container a high etch-rate oxide, such as ozone TEOS, is deposited over the entire structure thereby bridging across the top of the oxide container. The high etch-rate oxide is planarized back to the thin poly and the resulting exposed poly is then removed to separate neighboring containers. The two oxides, having different etch rates, are then etched thereby leaving a free-standing poly container cell with 100% (or all) of the higher etch rate oxide removed and a pre-determined oxide surrounding the container still intact.