Abstract: The reliability of in-laid metallization patterns, e.g., of copper or copper alloy, is significantly enhanced by voidlessly filling recesses in a substrate by an electroplating process, wherein “pinching-off” of the recess opening due to formation of overhanging metal deposits as a result of increased rate of electrodeposition thereat is prevented. Embodiments include preliminarily selectively rendering the recess opening surface non-conductive. The inventive method also enables a reduction in electrodeposition over non-recessed areas, thereby reducing the time required for planarization, as by CMP.

Abstract: An SiO2 layer and an SiN layer are alternately stacked in regions 1 and 2 where the wiring film must be thin and thick, respectively, in such a manner that the stacked SiO2 and SiN layers constitute first through sixth interlayer insulating films. The SiN layer may be replaced with a layer of another material having an etching selection ratio with reference to SiO2. Then, resist having a cutout pattern is formed. The cutout pattern has a first via pattern in the first region and a first wiring pattern in the second region. With this resist used as a mask, the sixth, fifth, fourth and third insulating films are etched. Further, second resist having a cutout pattern is formed. The cutout pattern of the second resist has a second wiring pattern in the first region and a second via pattern in the second region. With the second resist used as a mask, the sixth and fifth insulating films are etched in the first region, and the second and first insulating films are etched in the second region.

Abstract: A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A seed layer is deposited over the barrier layer and a conductor core is deposited over the seed layer, filling the opening of in the channel dielectric layer. The seed and barrier layers are then removed above the dielectric layer. A conductive layer is then deposited, filling any voids or depressions in the conductor core, and is subsequently removed above the dielectric layer resulting in a conductive channel of uniform thickness.

Abstract: A method of producing a dual damascene structure. A substrate is provided and an insulation layer is formed over the substrate. A dual damascene opening is formed in the insulation layer. A liner layer is formed over the exposed surface of the dual damascene opening. Metallic material is deposited over the substrate filling the dual damascene opening to form a metallic layer. A cap layer is formed over the metallic layer. A chemical-mechanical polishing operation is carried out to polish the cap layer using a metal-reactive solution or a cap-layer-reactive solution. The polishing operation continues until the cap layer outside the dual damascene opening is completely removed and the metallic layer is exposed. A portion of the cap layer remains above the dual damascene opening. Using the retained cap layer as a protective layer for the metallic layer, the metallic layer outside the dual damascene opening is removed by polishing until the liner layer is exposed.

Abstract: A method is disclosed to improve copper barrier and adhesion properties of copper interconnections in integrated circuits. It is shown that combining ion metal plasma (IMP) deposition along with in-situ chemical vapor deposition (CVD) of barrier and adhesion materials provides the desired adhesion of and barrier to diffusion of copper in damascene structures. IMP deposition is performed with tantalum or tantalum nitride while CVD deposition is performed with a binary or a ternary compound from a group consisting of titanium nitride, tungsten nitride, tungsten silicon nitride, tantalum silicon nitride, titanium silicon nitride. IMP deposition provides good adhesion of copper to insulator materials, while CVD deposition provides good sidewall coverage in a copper filled trench and a copper seed layer provides good adhesion of bulk copper to adhesion/barrier layer. The IMP/CVD deposited adhesion/barrier layer is thin, thus providing low via resistance.

Abstract: A method for forming a self-aligned mask read only memory by dual damascene trenches is disclosed. In the method, a thickness difference is formed between the gate area and periphery to be formed with a dual damascene trench so as to be formed with a condition of self-alignment of read only memory code. Thus, the manufacturing range in the lithography is enlarged, and an ion implantation process with self-aligned ability complete. Therefore, self-aligned read only memory codes and metal word lines are formed. The defect of disalignment in the read only memory code is resolved and the difficulty in the manufacturing process is reduced.

Abstract: Disclosed herein is a method for forming an embedded metal wiring comprising the steps of: forming a wiring trench, a barrier metal film and a conductive metal film; exposing the barrier metal film by polishing the conductive metal film by use of a polishing liquid and an oxidizing agent having a first concentration; and forming a wiring by polishing and removing the exposed barrier metal film by use of a polishing liquid and an oxidizing agent having a second concentration lower than the first concentration. The excessive polishing of the conductive metal occurs when an oxidizing agent having a relatively large concentration while such an oxidizing agent is needed when the barrier metal film is polished and removed. In order to attain the smooth removal of the barrier metal film and to prevent the excessive removal of the conductive metal, the oxidizing agent having a lower concentration is employed in the polishing of the conductive metal.

Abstract: A fabrication method for a dual damascene structure includes forming a first dielectric layer on a substrate already comprises a first conductive layer formed therein. The first dielectric layer is then patterned to form a via opening, exposing the first conductive layer. After this, a second dielectric layer is formed on the first dielectric layer by hot filament chemical vapor deposition, wherein the second dielectric layer does not fill the via opening. The second dielectric layer is then patterned to form a trench. The trench and the via opening together form a dual damascene opening. A second conductive layer is further filled the damascene opening to complete the fabrication of a dual damascene structure.

Abstract: A method for planarizing a microelectronic substrate. In one embodiment, the microelectronic substrate includes an insulating portion having at least one aperture that is empty or at least partially filled with a sacrificial material. The method can include pressing a planarizing medium having small abrasive elements against the microelectronic substrate and moving at least one of the microelectronic substrate and the planarizing medium relative to the other to remove material from the microelectronic substrate. In one aspect of the invention, the abrasive elements can include fumed silica particles having a mean cross-sectional dimension of less than about 200 nanometers and/or colloidal particles having a mean cross-sectional dimension of less than about fifty nanometers. The smaller abrasive elements can reduce the formation of cracks or other defects in the insulating material during planarization to improve the reliability and performance of the microelectronic device.

Abstract: An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer.

Abstract: The present invention discloses an interconnection structure for providing electrical communication with an electronic device which includes a body that is formed substantially of copper and a seed layer of either a copper alloy or a metal that does not contain copper sandwiched between the copper conductor body and the electronic device for improving the electromigration resistance, the adhesion property and other surface properties of the interconnection structure. The present invention also discloses methods for forming an interconnection structure for providing electrical connections to an electronic device by first depositing a seed layer of copper alloy or other metal that does not contain copper on an electronic device, and then forming a copper conductor body on the seed layer intimately bonding to the layer such that electromigration resistance, adhesion and other surface properties of the interconnection structure are improved.

Abstract: A method of forming amorphous silicon spacers followed by the forming of metal nitride over the spacers in a copper damascene structure—single, dual, or multi-structure—is disclosed in order to prevent the formation of fluorides in copper. In a first embodiment, the interconnection between the copper damascene and an underlying copper metal layer is made by forming an opening from the dual damascene structure to the underlying copper layer after the formation of the metal nitride layer over the amorphous silicon spacers formed on the inside walls of the dual damascene structure. In the second embodiment, the interconnection between the dual damascene structure and the underlying copper line is made from the dual damascene structure by etching into the underlying copper layer after the forming of the amorphous silicon spacers and before the forming of the metal nitride layer.

Abstract: The present invention provides a method of manufacturing an interconnect structure within a substrate. The method includes forming an opening in a substrate, which may be a dielectric layer having a low k; for example, one where the dielectric constant ranges from about 3.9 to about 1.9. This method further includes forming a passivation layer within the opening and a photoresist within the opening and over the passivation layer. The passivation layer substantially or completely inhibits the diffusion of elements from the substrate that can deactivate a photo acid generator (PAG) within the photoresist, which prevents the photoresist from developing properly.

Abstract: A method for forming a planar surface over low density fields on a semiconductor wafer that has a contoured front face with a low region between high points. In accordance with one embodiment of the method, a fill layer is deposited over the front face to conform to the contour of the front face and form a depression in the fill layer positioned above the low region. A cover layer is then deposited over the fill layer to fill at least a portion of the depression. The cover and fill layers are selectively removable from the wafer using suitable etching and planarization processes. A portion of the cover layer is then selectively removed from the fill layer to an intermediate endpoint at which the upper portions of the fill layer are exposed, and the only remaining portion of the cover layer is positioned in the depression of the fill layer.

Abstract: A method for forming, within a low dielectric constant dielectric layer formed upon a substrate employed within a microelectronics fabrication, a conductor pattern employing a hard mask cap layer. There is first provided a substrate having conductor regions formed therein upon which is formed a low dielectric constant dielectric layer. There is then formed over the substrate a silicon containing hard mask cap layer. There is then formed over the hard mask cap layer a patterned photoresist etch mask layer. There is then subtractively etched employing the patterned photoresist etch mask layer and a first subtractive etching environment the pattern into the hard mask layer. There is then subtractively etched employing the patterned hard mask layer and a second etching environment the pattern into the low dielectric constant dielectric layer, simultaneously stripping the photoresist etch mask layer.

Abstract: A dual damascene process is disclosed, in which a contact via and trench pattern is etched into insulating layer(s). The via is first partially filled by selective metal (e.g., tungsten) deposition, thereby forming a partial plug that raises the floor and reduces the effective aspect ratio of the trench and via structure. The remaining portion of the contact via is then filled with a more conductive material (e.g., aluminum). This deposition also at least partially fills the overlying trench to form metal runners. In the illustrated embodiment, hot aluminum deposition fills the portion of the contact via left unoccupied by the selective deposition and overfills into the trench. A further, cold aluminum deposition then follows, topping off the trench prior to planarization.

Abstract: The present invention discloses a method for forming an overlay vernier that can prevents deformation of the mother vernier. The method comprises the steps of: forming a planarization film on a wafer where a predetermined basic substructure has been formed; etching the planarization film to expose a predetermined region of a scribe line of the wafer where the overlay vernier will be formed; depositing a first polysilicon layer on the planarization film and the exposed wafer region; polishing the first polysilicon layer until the surface of the planarization film is exposed; forming an interlayer insulating film on the planarization film and the remained first polysilicon layer; etching the interlayer insulating film to expose a region of the first polysilicon layer where the mother vernier of the overlay vernier will be formed; depositing a second polysilicon layer on the interlayer insulating film and the exposed first polysilicon layer; and patterning the second polysilicon layer to form the mother vernier.

Abstract: A process-is disclosed for planarizing an integrated circuit structure by chemical mechanical polishing (CMP) after filling, with at least one metal, a plurality of trenches and/or vias formed in a silicon oxide layer on the integrated circuit structure. The process, which is capable of inhibiting formation of concave surface portions on the silicon oxide surface, during the CMP process, in regions where said trenches and/or vias are closely spaced apart, comprises forming, over a layer of silicon oxide of an integrated circuit structure, an antireflective coating (ARC) layer of dielectric material capable of functioning as a stop layer in a CMP process to remove metal; and using this ARC layer as a stop layer to assist in removal of excess metal used to fill trenches and/or vias formed in the oxide layer. The particular material chosen for the ARC layer should have a lower etch rate, in a CMP process to remove metal, than does the underlying oxide dielectric layer.

Abstract: A method of manufacturing semiconductors is provided which avoids metal deposition in voids formed in the dielectric between interconnects. In a preferred embodiment, an etch stop recess portion is provided over the dielectric which encloses the interconnects to prevent via openings from extending into the voids during the etching of the via openings. Accordingly, metal deposition of the voids during metal deposition of the vias is avoided. As a result, the semiconductors so formed has reduced capacitance between the interconnects and improved reliability since the voids are cleared of any metal deposition.

Abstract: An improved thin-film capacitor and methods for forming the same on a surface of a substrate are disclosed. The capacitor includes a bottom conducting plate formed by depositing conductive material within a trench of an insulating layer and planarizing the conducting and insulating layers. A dielectric film is then deposited on the substrate surface, such that at least a portion of the dielectric material remains over the bottom conducting plate. A second conductive layer is then deposited over the surface of the substrate, patterned and etched such that at least a portion of the second conducting material resides over at least a portion of the dielectric material.

Abstract: A method for manufacturing microscopic canals within a semiconductor is disclosed. A shallow trench is initially formed on a substrate using a patterned photoresist. After the patterned photoresist has been removed from the substrate, a separation layer, such as a Titanium layer, is deposited on the substrate. Subsequently, a cap layer, such as a Titanium nitride layer, is deposited on the separation layer. Both the separation layer and the cap layer are then polished off from the surface of the substrate. Finally, a Tungsten layer is deposited on the substrate and in the trench such that a microcanal will be formed within the trench as a result.

Abstract: Chemical mechanical polishing (CMP) is known to cause dishing when the surface being planarized includes a wide trench partially filled with metal. This problem has been overcome by first filling the trench with a material whose polishing rate under CMP is similar to that of the metal in the trench. Spin-coating is used for this so that only the trench gets filled. After CMP, any residue of this material is removed, leaving behind a surface that has been planarized to the intended extent without the introduction of significant dishing and with minimum erosion of the metal.

Abstract: A method for manufacturing an interconnect structure of a semiconductor device includes forming a bottom interconnect layer underlying a dielectric layer and overlying a silicon substrate; forming a through-hole in the dielectric layer to expose the bottom interconnect later; depositing a first barrier metal layer overlying the dielectric layer and on an inner wall of the through-hole; depositing a metal layer on the first barrier metal layer for filling the through-hole; etching the metal layer and the first barrier metal layer until the dielectric film is exposed to thereby form a via plug of the metal layer and the barrier metal layer; depositing a second barrier metal layer on the dielectric film and the via plug; and depositing an interconnect layer of which a main component is aluminum on the second barrier metal layer.

Abstract: The invention provides a method for forming a dielectric layer in a semiconductor device by using etch stop layers, and a semiconductor structure formed by the method. The method in accordance with the invention comprises: providing a semiconductor substrate having raised portions and recessed portions; forming a first etch stop layer covering the raised portions and the recessed portions; forming a dielectric layer covering an upper surface of the first etch stop layer, wherein the dielectric layer has a thickness substantially smaller than that of each of the raised portions; forming a second etch stop layer covering the dielectric layer; and performing a planarizing step for polishing the second etch stop layer and the dielectric layer until exposing the first etch stop layer on an upper surface of the raised portions, and remaining a plurality of remaining portions of the second etch stop layer on the planarized surface, and remaining the dielectric layer between raised portions.

Abstract: A non-contact post CMP clean-up process. A corrosion inhibitor is used to protect the copper (118) surface to prevent an electrochemical reaction between the p-well and n-well areas. A multi-step wet chemistry is used to clean all exposed surfaces without etching more than 100 Å of the dielectric (110), copper (118), or liner (116). The first step uses a basic solution and a surfactant (124). The second step uses a diluted HF solution (126) and the third step uses an organic acid solution (128).

Abstract: A new method is provided that affects the polishing rate of the surface of a layer of copper, that has been deposited over the surface of a layer of dielectric. Copper damascene structures have been created in the surface of the layer of dielectric, the layer of dielectric also overlies an alignment mark. The surface of the layer of dielectric that is aligned with the alignment mark is provided with dummy damascene structures, assuring equal polishing rates for active damascene structures and the surface region of the layer of dielectric overlying an alignment mark.

Abstract: A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 Å can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2C12) as the main reactive agent.

Abstract: A method for the shrink-hole-free filling of trenches in semiconductor circuits which utilizes selective growth of a layer to be applied is described. In the method, a layer of a selective growing material is applied simultaneously to a growth-promoting layer and to a growth-inhibiting layer. Wherein raised portions which, before the layer of selective growing material is applied, are covered by the growth-inhibiting layer at least on their sides. After the growth-inhibiting layer has been applied, the growth-promoting layer is generated by anisotropic treatment on surfaces parallel to the substrate on and between the raised portions and the layer is then removed again on surfaces parallel to the substrate on the raised portions. The method makes it possible to produce in a particularly simple manner a pattern on the raised portions of which are covered by the growth-inhibiting layer on their sides and on their top whereas the bottom of trenches is covered with a growth-promoting layer.

Abstract: A semiconductor interconnect barrier between channels and vias is provided which made of a metallic barrier material. In one embodiment, a first channel is conventionally formed in the semiconductor dielectric, lined with a first barrier material, and filled with a first conductive material. A layer of titanium nitride is formed atop the first channel of the first conductive material. Thereafter, a second channel is conventional formed in a second channel oxide, lined with a second barrier material. The second barrier material is selected from metals such as tantalum, titanium, tungsten, compounds thereof, alloys thereof, and combinations thereof. The combination of the titanium nitride layer and the second barrier material provide a superior barrier for conductive material layers, such as, copper/copper layers, and copper/aluminum layers.

Abstract: A method of fabricating a semiconductor device, which forms dielectric sidewalls reliably at each side of a first wiring structure to protect its conductive line in the etching process for forming a via hole in an interlayer dielectric layer to cover the first wiring structure. In this method, the first wiring structure is formed on a first dielectric layer. A second dielectric layer is formed on the first dielectric layer to cover the first wiring structure. A third dielectric layer serving as an interlayer dielectric layer is formed on the second dielectric layer. The third and second dielectric layers are polished using the CMP technique until the dielectric of the first wiring structure is exposed, thereby leaving part of the second dielectric layer that extends along each side of the first wiring structure and the surface of the first dielectric layer. The dielectric layer is etched using a mask to form a via hole. The hole is then filled with a conductive plug.

Abstract: A method of removing the micro-scratches on a metal layer is described, wherein the metal layer is formed on a barrier layer conformally onto a dielectric layer having a hole thereon, and wherein the metal layer over-fills the hole. The method comprises three chemical-mechanical polishing steps as described hereinbelow. The first chemical-mechanical polishing step is that oxidizing and polishing away the metal layer outside the hole, with a first slurry, wherein the first slurry has a chemical solution and has a plurality of abrasive particles. The second chemical-mechanical polishing step is that polishing away the barrier layer outside the hole, with a second slurry, whereby a plurality of micro-scratches are formed on the metal layer after the barrier layer is chemical-mechanically polished. The third chemical-mechanical polishing step is that buffing the metal layer, with the first slurry, thereby removing the micro-scratches on the metal layer.

Abstract: A semiconductor device having good electrical properties, and a method of manufacturing this semiconductor device by forming an insulation layer on a first wiring layer and then, in this insulation layer, simultaneously forming a second wiring layer and a contact layer for connecting the first wiring layer and the second wiring layer. A first mask having an opening over a wiring trench in which the second wiring layer will be formed is formed on the insulation layer. A second mask having an opening for a through-hole where the contact layer is to be formed is then formed over the insulation layer and first mask. The insulation layer is then etched using the second mask as a mask. Then the insulation layer is again etched using the first mask as a mask to form wiring trench and through-hole. The wiring trench and through-hole are then filled with a conductive material to form the second wiring layer and contact layer.

Abstract: A method of removing excess metal, particularly copper, in the fabrication of interconnects has been achieved. In accordance with the objects of this invention, a new method of removing excess metal in the formation of an interconnect has been achieved. A semiconductor substrate is provided. A dielectric layer is provided overlying the semiconductor substrate. Trenches are formed in this dielectric layer for planned damascene or dual damascene interconnects. A barrier layer is provided overlying the dielectric layer and lining the trenches. A metal layer is provided overlying the barrier layer and completely filling the trenches. A masking layer is deposited overlying the metal layer. The masking layer is patterned to form a mask that only overlies the trenches. The metal layer is etched down where not covered by the mask. This etching down is partial so that the barrier layer is not exposed. This etching down leaves the metal layer underlying the mask thicker than the metal layer not underlying the mask.

Abstract: In a wafer edge neighboring region 26, the circumference end part of a silicon oxide film 8 is set in an outer position than the circumference end part of a silicon oxide film 3 and thereby a structure in which polishing remains 21 generated in forming a copper interconnection comprising a copper film 6 and the like are covered with the silicon oxide film 8 is attained.

Abstract: A method of producing a semiconductor device having a connecting thin film for connection to a bonding wire on a bonding pad formed on a surface of a surface protective film. A recess is formed in the surface of the surface protective film. Thereafter, a metal deposited layer composed of a material for the bonding pad is formed, and a metal thin film composed of a material for the connecting thin film is further formed thereon. After the metal thin film is formed, unnecessary parts of the metal deposited layer and the metal thin film are removed by chemical mechanical polishing, for example.

Abstract: A semiconductor device and a method of making it involve the semiconductor device (10, 71, 101, 121, 151, 201) having a substrate (11, 73, 153) with spaced source and drain regions (13-14, 76-78, 154). A gate section (21, 81-82, 123, 203) projects upwardly from between an adjacent pair of the regions, into an insulating layer (31, 83, 103, 122, 157). In order to create local interconnects to the source and drain regions through the insulating layer, a patterned etch is carried out using an etch region (36, 87, 126), which extends over one of the gate sections from a location above one of the regions to a location above another of the regions. Etching in this etch region produces recesses (41-42, 91-93, 107-108, 138-139, 158) on opposite sides of and immediately adjacent the gate section. A conductive layer (51, 96, 111, 161, 171) is deposited to fill the recesses, and then is planarized back to the upper ends of the gate sections.

Abstract: An insulating layer can be formed on first and second adjacent regions of an integrated circuit having a first step difference therebetween, the first and second regions having first and second respective etch rates associated therewith. A recess can be formed in the insulating layer on the second region having a second step difference with the first region that is less than the first step difference to provide a portion of the insulating layer between the first and second adjacent regions having a third step difference with the first region that is greater than the second step difference. A width of the portion is selected based on a difference between the first and second etch rates.

Abstract: A semiconductor device includes first and second conductive layers which are electrically connected to each other through a contact plug. A first insulating film is formed on the first conductive layer and has a first opening which reaches the surface of the first conductive layer. A second insulating film is formed on the first insulating film and has a second opening at the same position as the first opening. The contact plug is filled in the first and second openings and has the surface which is substantially flush with the surface of the second insulating film and also contains a metal having a high melting point. The second conductive layer is formed on the second insulating film and on the contact plug.

Abstract: A method for forming void free tungsten plug contacts (56a-56c) begins by etching a contact opening (55a-55c) using a C2F6 and CHF3 chemistry. The etch chemistry is then changed to an O2 and CH3F chemistry in order to insitu remove the contact photoresist while tapering an upper portion of the contact opening. A tungsten deposition process is then performed whereby the tapered portion of the contact reduces the effects of nonconformal and step-coverage-inconsistent tungsten deposition wherein voids in the contact are either substantially reduced or totally avoided within the contact structure. The reduction of or total elimination of voids (22) within the tungsten contact will increase yield, increase reliability, and reduce electromigration failures within integrated circuit devices.

Abstract: Chemical mechanical polishing slurry with functionalized silica abrasive particles, the functionalization permits high pH slurry without rapid degradation of silica particles and also permits the modification of surface properties of abrasive particles to modify slurry behavior. One example of modified behavior would be to enhance selectivity by controlling particle interaction with different surfaces on the wafer.

Abstract: On a silicon oxide film covering a gate electrode portion, a reflowed and polished BPSG film is formed. A second interconnection layer is formed on the BPSG film. To cover the second interconnection layer, a silicon oxide film having a thickness of at least the substantial thickness of the second interconnection layer is formed on a silicon oxide film. Thus, the planarity of the base of the interconnection layer is ensured and displacement of the interconnection layer is suppressed. Accordingly, a semiconductor device having a high degree of integration is obtained.

Abstract: The present invention is a method for removing a portion of a liner film and a metallization layer superimposed over the liner film to expose an underlying dielectric layer on a semiconductor wafer. Specifically, at least a portion of the metallization layer is removed by chemical mechanical polishing the metallization layer using a first polishing slurry having a plurality of first abrasive particles and at least a portion of the liner film is removed by chemical mechanical polishing the liner film using a second polishing slurry having a plurality of second abrasive particles. The first abrasive particles and the second abrasive particles used in the polishing steps have different bulk densities.

Abstract: A buried wiring line is formed without dishing using damascene and chemical mechanical polishing (CMP) processes. A key feature is the use of a first and a second pressure unit. The first pressure unit (15) has an airbag (18). The bag (18) is large in elastic deformation, and used to urge a copper film (5) of a silicon substrate (1) against a polishing pad (12) onto which a polishing liquid is supplied while the pad (12) is rotated, so that the copper film (5) is polished. The copper film (5) has been formed on the surface of the silicon substrate (1) through a barrier metal film (4). After polishing of the copper film (5), the silicon substrate (1) is transferred to the second pressure unit (25). The unit (25) has a metal plate (20).

Abstract: A method of forming a HDPCVD oxide layer over metal lines, the metal lines having gaps between the metal lines having an aspect ratio of two or more. The method comprises the steps of: forming a liner oxide layer over the metal lines; and forming an HDPCVD oxide layer over the liner oxide layer, the formation of the HDPCVD oxide layer being done such that the deposition-to-sputter ratio is increasing as the gaps are being filled.

Abstract: This invention relates to a process for forming a metal interconnect comprising the steps of forming a concave in an insulating film formed on a substrate, forming a copper-containing metal film over the whole surface such that the concave is filled with the metal and then polishing the copper-containing metal film by chemical mechanical polishing, characterized in that the polishing step is conducted using a chemical mechanical polishing slurry comprising a polishing material, an oxidizing agent and an adhesion inhibitor preventing adhesion of a polishing product to a polishing pad, while contacting the polishing pad to a polished surface with a pressure of at least 27 kPa. This invention allows us to prevent adhesion of a polishing product to a polishing pad and to form a uniform interconnect layer with an improved throughput, even when polishing a large amount of copper-containing metal during a polishing step.

Abstract: A planarization method is used in a dual damascene structure. At the stage that a dual damascene structure is semi-formed on a semiconductor substrate but before a planarization process, the planarization method starts by forming a dielectric layer on a metal layer, which is to be polished. A portion of the dielectric layer other than the dual damascene structure is removed by etching. A CMP process is performed to planarize the substrate and exposes an inter-metal dielectric layer.

Abstract: A method for forming through a microelectronic layer a via contiguous with a trench. There is first provided a substrate. There is then formed over the substrate a first microelectronic layer. There is then formed upon the first microelectronic layer an etch stop layer. There is then formed upon the etch stop layer a second microelectronic layer. There is then formed over the second microelectronic layer a first patterned photoresist layer which defines the location of a via to be formed through the second microelectronic layer, the etch stop layer and the first microelectronic layer. There is then etched, while employing a first etch method which employs the first patterned photoresist layer as a first etch mask layer, the second microelectronic layer, the etch stop layer and the first microelectronic layer to form a corresponding patterned second microelectronic layer, patterned etch stop layer and patterned first microelectronic layer which define the via.

Abstract: The semiconductor device includes a semiconductor substrate and, in an element isolating region in the semiconductor substrate, a first active area A/A dummy pattern and a second A/A dummy pattern having a pitch smaller than that of the first A/A dummy pattern. Placement of the first A/A dummy pattern and placement of the second A/A dummy pattern are carried out in separate steps. The semiconductor substrate may be divided into a plurality of mesh regions, and a dummy pattern may be placed in each mesh region according to an area of the mesh region being occupied by an element pattern located therein.

Abstract: An improved and new process for fabricating a planarized structure of copper or other conductive material embedded in low dielectric constant HSQ insulator has been developed. The planarizing method comprises the key step of forming a protective layer on the surface of a cured HSQ layer by treatment of the cured HSQ layer in either an NH3 plasma or a N2 plasma. The NH3 plasma or a N2 plasma treatment may be applied to the cured HSQ prior to or subsequent to etching holes in the cured HSQ. Following deposition of copper or other conductive material into holes etched in the HSQ layer, CMP is used to remove the copper or other conductive material from the surface of the cured and treated HSQ. The NH3 plasma or a N2 plasma treatment reduces the CMP removal rate of HSQ by a factor of 3 when using a CMP slurry designed to polish copper.

Abstract: A new method of forming a damascene interconnect in the manufacture of an integrated circuit device has been achieved. The damascene interconnect may be a single damascene or a dual damascene. Copper conductors are provided overlying a semiconductor substrate. A first passivation layer is provided overlying the copper conductors. A low dielectric constant layer is deposited overlying the first passivation layer. An optional capping layer is deposited overlying the low dielectric constant layer. A photoresist layer is deposited overlying the capping layer. The capping layer and the low dielectric constant layer are etched through to form via openings. The photoresist layer is simultaneously stripped away while forming a sidewall passivation layer on the sidewalls of the via openings using a sulfur-containing gas. Sidewall bowing and via poisoning are thereby prevented. The first passivation layer is etched through to expose the underlying copper conductors.