Abstract: A technique is described for providing cavities between the conducting paths of an integrated semiconductor circuit. These cavities can have air or a gas trapped therein to decrease the dielectric constant between two conducting paths. After forming the conducting paths, an etchable fill material formed between and over the conducting paths. An oxide cap is formed over the fill material. Conducting plugs, extending through the fill material and the oxide cap, and electrically coupled to the conducting paths are formed. A photo-resist layer applied over the conducting plugs and the oxide cap. The photo-resist layer is structured to permit access to the oxide cap between the conducting plugs. A “pin-hole” is fabricated through the oxide cap and the fill material exposed by the “pin-hole” is etched away. The “pin-hole” is plugged with additional oxide cap material and a surface is then formed on the oxide cap exposing the conducting plugs.

Abstract: A manufacturing method of a semiconductor device which includes wiring dense part and wiring isolated part enables occurrence of ‘Erosion’ to be prevented, as well as it is capable of being prevented occurrence of ‘micro-scratch’ on surface of oxide layer. The manufacturing method sets a plurality of trench-parts on insulation layer, before forming metal plating layer consisting of copper so as to embed trench-parts. Manufacturing process implements annealing in such a way that grain-size of the metal plating layer in the wiring dense part becomes smaller than the grain-size in the wiring isolated part. The annealing, for instance, is implemented with substrate temperature of 70 to 200° C. Subsequently, the manufacturing step perfects the semiconductor device while polishing the metal plating layer to cause the surface of the substrate to be flat.

Abstract: A method of dual damascene structure formation suitable for wiring on semiconductors. The method of forming a dual damascene structure includes the steps of forming an organic dielectric film and a metal oxide film on an inorganic dielectric film, forming a pattern on the resulting multilayer structure, and then etching the structure.

Abstract: Cleaning solutions and methods for removing residuals from the surface of an integrated circuit device. Such solutions and methods find particular application in the fabrication of a dual damascene structure following removal of excess portions of a silver-containing metal layer from a device surface. The cleaning solutions and methods facilitate removal of particulate residuals as well as unremoved portions of the metal layer in a single cleaning process. The cleaning solutions are dilute aqueous solutions containing hydrogen peroxide and at least one acidic component and are substantially free of particulate material. Acidic components include carboxylic acids and their salts.

Abstract: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting a mixture comprising an oxidizable silicon component and an oxidizable component having thermally labile groups with an oxidizing gas in gas-phase plasma-enhanced reaction. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a low-density structure. The nano-porous silicon oxide based films are useful for forming layers between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures.

Abstract: A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a dielectric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.

Abstract: A method for forming a multilayer interconnection structure on a wafer by using a damascene technique includes the steps of separating the area of the wafer into a peripheral area, an intermediate area and a central area as viewed from the outer periphery toward the center of the wafer. The lower-level interconnections having a smaller width are formed in the intermediate and central areas, whereas the upper-level interconnections having a larger width are formed in the central area.

Abstract: A method for manufacturing integrated circuits; particularly, a method for fabricating a copper interconnect system and a copper interconnect system, having a layer of CrO, fabricated by the method.

Abstract: The present invention provides a method of preventing the build-up of polishing material within low areas of a substrate during polishing. Following the blanket deposition of a first layer, a selectively removable material is deposited over the first layer, wherein the selectively removable material fills the low areas. A surface of the substrate is polished removing the excess first layer and selectively removable material from the surface, leaving the first layer and selectively removable material within the low area. Following polishing, the selectively removable material is removed from the low areas prior to the deposition of a second layer.

Abstract: The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer comprising at least one passivant element for the metal of the features, reacting the at least one passivant element to chemically reduce any deleterious oxide layer present at the upper surfaces of the metallization features, and diffusing the at least one passivant element for a distance below the upper surface to form a passivated top interface. The passivated top interfaces advantageously exhibit reduced electromigration and improved adhesion to overlying metallization with lower ohmic contact resistance. Planarization, as by CMP, may be performed subsequent to reaction/diffusion to remove any elevated, reacted and/or unreacted portions of the at least one thin layer.

Abstract: A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics.

Abstract: A thin nitride film having a low resistance is formed at a low film-forming temperature.

Abstract: The reliability and elecrtromigration resistance of planarized metallization patterns, e.g., of copper, in-laid in the surface of a layer of dielectric material, are enhanced by a process comprising blanket-depositing on the planarized, upper surfaces of the metallization features and the dielectric layer at least one thin layer comprising at least one alloying element for the metal of the features, and then uniformly diffusing at least a minimum amount of the at least one thin layer for a minimum depth below the upper surfaces of the metallization features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer.

Abstract: Conductive layers are formed in the trenches made in an insulating film in the following manner. First, an amorphous silicon film 26A is deposited in the trenches 25 made in a silicon oxide film 24. A photoresist film 30 is then formed on the amorphous silicon film 26A by means of spin coating. Then, exposure light is applied to the entire surface of the photoresist film 30, thereby exposing to light those parts of the photoresist film 30 which lie outside the trenches 25. The other parts of the photoresist film 30, which lie in the trenches 25 are not exposed to light because the light reaching them is inadequate. Further, the photoresist film 30 is developed thereby removing those parts of the film 30 which lie outside the trenches 25 and which have been exposed to light. Thereafter, those parts of the amorphous silicon film 26A, which lie outside the trenches 25, are removed by means of dry etching using, as a mask, the unexposed parts of the photoresist film 30 which remain in the trenches 25.

Abstract: An interconnect structure and method of forming the same in which a first inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a slot via in the first dielectric layer. The slot via is longer than the width of a subsequently formed trench. A second low k dielectric material is deposited within the slot via and over the etch stop layer, to form a second dielectric layer over the slot via and the etch stop layer. The re-filled slot via is simultaneously etched with the second dielectric layer in which a trench is formed. The entire width of the trench is over the via that is etched. The re-opened via and the trench are filled with a conductive material.

Abstract: A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.

Abstract: A semiconductor wafer comprises a substrate, and a conductive area positioned on a predetermined area of the substrate. A sacrificial layer is formed on the surface of the substrate. A patterned first photoresist layer is formed on the surface of the sacrificial layer, covering the conductive area, followed by removal of the sacrificial layer not covered by the first photoresist layer. A dielectric layer is formed on the surface of the substrate, and a second photoresist layer is formed on the surface of the dielectric layer. A line-shaped opening is formed in the second photoresist layer, followed by etching portions of the dielectric layer through the line-shaped opening for forming a line-shaped recess. The second photoresist layer and the remaining sacrificial layer are completely removed for forming a plug hole in the bottom of the line-shaped recess.

Abstract: A method is disclosed for removing metal from semiconductor substrates, optionally with or without the use of an abrasive slurry, and the attendant problems of defects caused by mechanical scratches, chemical corrosion and oxidation of components as is normally encountered with the well-known chemical-mechanical polishing (CMP) techniques. The metal removal is accomplished by placing a substrate having the metal layer in an electrolytic system in a tank, and rotating a pad against the substrate while passing current through the system including a cathode and the anodic metal layer. Preferably, the pad size is smaller than that of the substrate. The action of the pad against the metal layer moves an additive in the electrolytic solution from high regions to low regions on the metal layer, thus exposing the high regions to be polished away until all the regions are planarized to molecular height of the additive across the whole metal layer.

Abstract: The current invention teaches the use of e-beam patterning techniques for forming contact and via holes of diameter less than about 0.15 microns down to 0.05 microns. E-beam lithography has higher resolution (down to 30-50 nanometers) as compared to 130-150 nanometer when using deep ultra violet (DUV) photolithography patterning techniques. In addition the invention uses a mix and match approach by employing a conventional I-line, or deep UV, resist to form the trench pattern and e-beam lithography tools to form the contact and vial hole patterns. A simplified process scheme is developed where contact/via holes are formed first on solvent developable e-beam resist and the trench pattern is formed on aqueous developable photoresist coated on top of the e-beam resist.

Abstract: This invention relates to a process for forming a metal interconnect comprising the steps of forming a concave in an insulating film formed on a substrate, forming a copper-containing metal film over the whole surface such that the concave is filled with the metal and then polishing the copper-containing metal film by chemical mechanical polishing, characterized in that the polishing step is conducted using a chemical mechanical polishing slurry comprising a polishing material, an oxidizing agent and an adhesion inhibitor preventing adhesion of a polishing product to a polishing pad, while contacting the polishing pad to a polished surface with a pressure of at least 27 kPa. This invention allows us to prevent adhesion of a polishing product to a polishing pad and to form a uniform interconnect layer with an improved throughput, even when polishing a large amount of copper-containing metal during a polishing step.

Abstract: The present invention discloses a planarization method of inter-layer dielectrics (ILD) and inter-metal dielectrics (IMD). The key point of the present invention is that after the planarization process of the ILD and the IMD is performed by means of the chemical mechanical polishing (CMP), a cap layer is formed thereon. The cap layer can be a silicon nitride layer, a silicon nitrogen-oxide layer, or a silicon rich oxide layer having a refractive index not less than 1.6. The cap layer can be transmitted by UV light. The effects of the cap layer are to fill micro scratches generated by the CMP and to enhance the functions of anti-reflection and preventing the diffusion of hydrogen atoms. Thereby, the tolerance of subsequent exposition process can be increased. Moreover, the capabilities of data retention of device and device passivation can be enhanced.

Abstract: The invention relates to a DRAM integration method that does away with the alignment margins inherent to the photoetching step of the upper electrode of the capacitance for inserting the bit line contact. The removal of the upper electrode is self-aligned on the lower electrode of the capacitance. This is accomplished by forming a difference in topography at the point where the opening of the upper electrode is to be made, and depositing a non-doped polysilicon layer on the upper electrode. An implantation of dopants is performed on this layer, and the part of the non-doped layer located in the lower part of the zone showing the difference in topography is selectively etched. The remainder of the polysilicon layer and the part of the upper electrode located in the lower layer are also etched.

Abstract: Embedded interconnections of copper are formed by forming an insulating layer, forming embedded interconnections of copper in the insulating layer, making an exposed upper surface of the insulating layer and an exposed surface of the embedded interconnections of copper coplanar according to chemical mechanical polishing, and forming a protective silver film on the exposed surface of the embedded interconnections of copper. These steps are repeated on the existing insulating layer thereby to produce multiple layers of embedded interconnections of copper. The exposed surface of the embedded interconnections of copper is plated with silver according to immersion plating.

Abstract: Highly porous, low-k dielectric materials are mechanically reinforced to enable the use of these low-k materials as intralayer and interlayer dielectrics in advanced integrated circuits such as those which incorporate highly porous materials in a Cu damascene interconnect technology. An integrated circuit, embodying such a mechanically reinforced dielectric layer generally includes a substrate having interconnected electrical elements therein, a copper-diffusion barrier or etch stop layer disposed over the substrate, the copper-diffusion barrier or etch stop layer being patterned so as to provide a plurality of electrically insulating structures, and a low-k dielectric layer disposed around the plurality of structures.

Abstract: A semiconductor manufacturing process is used to develop capacitors in compact areas such as at or near the interconnect level. According to one example embodiment, a substrate having a first and second conductor is separated by a dielectric, once the dielectric is removed a trench is formed, and a first material including silicon nitride is deposited over the substrate so that it covers the trench. A second material, including metal, is then deposited over the first material, covering it and the first and second conductors. CMP is then used to remove the metal over the field and isolate the filled metal from adjacent metals causing the silicon nitride to act as a natural CMP etch-stopper and protecting other areas of the interconnect from damage by the CMP.

Abstract: The present invention is a level of an integrated circuit. The level of integrated circuit has a first area having a plurality of features having a first density and the level of the integrated circuit has a second area adjacent to the first area wherein the second area has a plurality of dummy features having a density substantially similar to the first density.

Abstract: An improved and new process, used for the elimination of copper line damage in damacene processing, is disclosed. By depositing copper by physical vapor deposition (PVD), sputtering, preferably by an ion metal plasma (IMP) scheme or chemical vapor deposition (CVD), the deposited copper fills pinholes or intra-cracks (micro-cracks), caused by poor gap filling of purely electrochemical deposition of copper plating. By this process or method, chemical attack on copper lines, by chemicals in the subsequent chemical mechanical polish (CMP) back and post-cleaning steps, is prevented.

Abstract: A method of manufacturing a semiconductor device is provided. A TEOS film (1) is formed, and then an FSG film (2) is formed on the TEOS film (1) by a CVD or PVD process. The CVD or PVD of the FSG film (2) is continued so that noble gas atoms are introduced into the FSG film (2) to form a noble gas atom containing layer (3). Next, using a photoresist (4) formed on the noble gas atom containing layer (3) as a mask, the noble gas atom containing layer (3) and the FSG film (2) are etched in the order named. After the photoresist (4) is removed, a barrier metal (6) and a copper film (7) are formed on an entire surface of a resultant structure. The copper film (7) and the barrier metal (6) are polished away in the order named by a CMP process until an upper surface of the noble gas atom containing layer (3) is exposed. Parts of the copper film (7) which are left unpolished become copper interconnect lines (9) filling trenches (5). The method can reduce a wiring capacitance between the adjacent interconnect lines.

Abstract: Using this special dual damascene process, interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of thin etch stop or etch barrier layers. The key process steps of this invention are a special partial via hole etch and a special via hole liner. The Prior Art dual damascene processes are generally composed of a thick via etch stop layer to avoid damaging underlying Cu during via patterning, as well as, a thick trench etch stop layer to avoid via hole facet during trench patterning. Thick etch stop layers are undesirably due to high dielectric constant values compared with silicon oxide, the intermetal dielectric (IMD). Therefore, the thickness of stop-layer should be reduced to minimize the circuit (RC) time constant delay. In general, there are two main approaches for dual damascene etching.

Abstract: A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

Abstract: The present invention provides a method to form a copper interconnect and avoid a dishing phenomenon on the copper interconnect in the manufacturing process which will cause the metal line thinning and high resistance. By using a cap layer selectively positioned over the dual damascene structure, the method can balance the difference of polishing rate between the copper and the surrounding material. Such we can get a plane surface of interconnect in a chemical mechanical polishing process.

Abstract: A method of fabricating integrated circuitry comprises forming a conductive line having opposing sidewalls over a semiconductor substrate. An insulating layer is then deposited. The insulating layer is etched proximate the line along at least a portion of at least one sidewall of the line. An insulating spacer forming layer is then deposited over the substrate and the line. It is anisotropically etched to form an insulating sidewall spacer. A method of forming a local interconnect comprises forming at least two transistor gates over a semiconductor substrate. A local interconnect layer is deposited to overlie at least one of the transistor gates and interconnect at least one source/drain region of one of the gates with semiconductor substrate material proximate another of the transistor gates.

Abstract: A method is provided for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor wafer and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening and a conductor core is deposited to fill the channel opening over the barrier layer. The semiconductor wafer is then subjected to chemical-mechanical polishing using a differential pressure between the center of the semiconductor wafer and its periphery.

Abstract: The invention relates generally to improved silicon carbide deposition during dual damascene processing. In one aspect of the invention, copper oxide present on a substrate is reduced at least partially to copper prior to deposition of a silicon carbide or silicon oxycarbide layer thereon. In the preferred embodiment the reduction is accomplished by contacting the substrate with one or more organic reducing agents. The reduction process may be carried out in situ, in the same reaction chamber as subsequent processing steps. Alternatively, it may be carried out in a module of a cluster tool.

Abstract: The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing.

Abstract: Within a series of chemical mechanical polish (CMP) planarizing methods for forming a series of damascene structures within a series of microelectronic fabrications, there is employed at least one lateral offset width between: (1) a sidewall of a patterned dielectric layer and an edge of a substrate; (2) a sidewall of a patterned conductor layer and a sidewall of a patterned dielectric layer; and (3) a sidewall of a patterned second dielectric layer and a sidewall of a first dielectric layer. By employing the at least one lateral offset, there is provided the series of damascene structures with inhibited physical degradation of a patterned dielectric layer when forming within an aperture defined by the patterned dielectric layer a chemical mechanical polish (CMP) planarized patterned conductor layer.

Abstract: Metal CMP with reduced dishing and overpolish insensitivity is achieved with an abrasive-free polishing composition having a pH and oxidation-reduction potential in the domain of passivation of the metal and, therefore, a low static etching rate at high temperatures, e.g., higher than 50° C. Embodiments of the present invention comprise CMP of Cu film without any abrasive using a composition comprising one or more chelating agents, one or more oxidizers, one or more corrosion inhibitors, one or more agents to achieve a pH of about 3 to about 10 and deionized water.

Abstract: Low k dielectrics such as black diamond have a tendency to delaminate from the edges of a silicon wafer, causing multiple problems, including blinding of the alignment mark. This problem has been overcome by inserting a layer of silicon nitride between the low k layer and the substrate. A key requirement is that said layer of silicon nitride be under substantial compressive stress (at least 5×109dynes/cm2). In the case of a layer of black diamond, on which material the invention is particularly focused, a nucleating layer is also inserted between the silicon nitride and the black diamond. A process for laying down the required layers is described together with an example of applying the invention to a dual damascene structure.

Abstract: The invention relates to an abrasive containing a slurry of the cerium oxide grains dispersed in water. The Cerium oxide grains are obtained by adding hydrogen peroxide to an aqueous dispersion of cerium carbonate. The Cerium oxide grains are obtained by oxidizing a precipitate, which is formed through addition of ammonium hydrogencarbonate to an aqueous solution of cerium nitrate, with hydrogen peroxide. The Cerium oxide grains are obtained by neutralizing or alkallfying an aqueous solution of cerium ammonium nitrate.

Abstract: Planarizing solutions, and their methods of use, for removing titanium nitride from the surface of a substrate using a fixed-abrasive planarizing pad. The planarizing solutions take the form of an etchant solution or an oxidizing solution. The etchant solutions are aqueous solutions containing an etchant and a buffer. The etchant contains one or more etching agents selective to titanium nitride. The oxidizing solutions are aqueous solutions containing an oxidizer and a buffer. The oxidizer contains one or more oxidizing agents selective to titanium nitride. In either solution, i.e., etchant or oxidizing solution, the buffer contains one or more buffering agents. Titanium nitride layers planarized in accordance with the invention may be utilized in the production of integrated circuits, and various apparatus utilizing such integrated circuits.

Abstract: A improved method is provided for forming self-aligned integrated circuit structures, particularly self-aligned contact structures, by providing, on a substrate, raised structures each including an outermost protective layer, and each having a horizontal upper surface extending between substantially vertical lateral surfaces, said horizontal upper surface being horizontal over the entire area therebetween. An etchable layer is formed over and between said raised structures. A photoresist layer is formed on said etchable layer and patterned. Said etchable layer is then anisotropically etched selective to said protective layer to remove said etchable layer from between selected of said raised structures, said horizontal upper surfaces substantially preventing etching at top outer edges of said raised structures and preserving thereby the integrity of the protective layers.

Abstract: The dual damascene method having steps of; after a first insulating film, a first organic insulating film, a second insulating film, and a metal film are formed in sequence, a first opening having a wiring pattern is formed in the metal film, then a second opening having a via pattern is formed in the second insulating film, then the first organic insulating film is etched using the second insulating film as a mask, then the first insulating film and the second insulating film are etched simultaneously while using the metal film and the first organic insulating film as a mask, and then the first organic insulating film is etched while using the metal film as a mask, at this stage, a wiring recess is formed in the first organic insulating film and the second insulating film, and a via-hole is formed in the first insulating film.

Abstract: A novel and improved method of fabricating an integrated circuit, in which special copper films are formed by a combination of physical vapor deposition (PVD), chemical mechanical polish (CMP) and electrochemical copper deposition (ECD) techniques. The methods of the present invention make efficient use of several process steps resulting in less processing time, lower costs and higher device reliability. By these techniques, high aspect ratio trenches can be filled with copper without the problem of dishing. A special, selective electrochemical deposition (ECD) of copper metal is utilized taking place only on the seed layer in the trench. This auto-plating or “plate-up” occurs only in the trench and provides good sealing around the trench perimeter and fine copper metal coverage of the trench for subsequent robust interconnects.

Abstract: A semiconductor device having an STI structure is provided by eliminating an insufficient polishing problem of an insulating film on chips adjacent to a marking region by making an equal polishing pressure to be applied to entire chips at polishing. A method for fabricating a semiconductor device having an isolation structure of the present invention includes: processing a marking region of a wafer having a device region, a grid line region and the marking region in order to enable a substantially equal polishing pressure to be applied to chips adjacent to the marking region of the wafer and to other chips, for example, tapering or recessing; marking in the marking region; forming a nitride film and an oxide film on a surface of the wafer; removing the oxide film by polishing; and removing the nitride film.

Abstract: An interconnect fabrication process and structure provides barrier enhancement at the via sidewalls and improved capability to fabricate high aspect ratio dual damascene interconnects. A via structure is patterned into the via dielectric first, then a dielectric barrier (for example, anisotropically etched silicon nitride) is formed only along the via sidewalls in the dual damascene structure prior to deposition of a metal barrier (for example, Ta/TaN). In this way, the effective barrier thickness along the bottom of the via is increased, eliminating the structure's susceptibility to metal migration. The absence of dielectric barrier along the interconnect trench sidewalls leads to low interconnect resistance and low interconnect capacitance. The present invention also provides an improved fabrication method for obtaining high aspect ratio dual damascene interconnect structures.

Abstract: A fabrication method for a dual damascene structure is provided. A barrier layer and a copper seed layer are formed on a substrate comprising a dual damascene opening, wherein the barrier layer and the copper seed layer cover the dual damascene opening. A sacrificial layer is then formed on the copper seed layer, filling the dual damascene opening. Using the copper seed layer as an etch stop layer, the sacrificial layer is etch back. The exposed copper seed layer is then removed, followed by completely removing the sacrificial layer. A metal copper layer is formed in the dual damascene opening by plating, filling the opening of the dual damascene opening.

Abstract: A process for forming an integrated circuit structure wherein trenches and/or vias are formed in a predetermined pattern in a dielectric layer, lined with a barrier layer of a first electrically conductive material, and then filled with a second electrically conductive material, and the structure is then planarized to remove the first and second electrically conductive material from the upper surface of the dielectric layer, wherein the improvements comprise: a) before the planarizing step, forming over the second electrically conductive material a layer of a planarizable material capable of being planarized at about the same rate as the first electrically conductive material; and b) then planarizing the structure to remove: i) the planarizable material; ii) the second electrically conductive material; and iii) the first electrically conductive material; above the upper surface of the dielectric material; whereby the planarizable material above the second electrically conductive material in the trenche

Abstract: A method for manufacturing integrated circuits; particularly, a method for fabricating a copper interconnect system and a copper interconnect system, having a layer of CrO, fabricated by the method.

Abstract: Disclosed is a copper-based metal polishing solution which hardly dissolves a Cu film or a Cu alloy film when the film is dipped into the solution, and has a dissolution velocity during polishing several times higher than that during dipping. This copper-based metal polishing solution contains at least one organic acid selected from aminoacetic acid and amidosulfuric aminosulfuric acid, an oxidizer, and water.

Abstract: A semiconductor metallization processing method for multi-level electrical interconnection includes: a) providing a base insulating layer atop a semiconductor wafer; b) etching a groove pathway into the base layer; c) providing a first contact through the base layer to the area to which electrical connection is to be made; d) the groove pathway being etched and the first contact being provided in a combined manner which has the groove pathway and the first contact communicating with one another; e) providing metal within the first contact and within the groove pathway, the metal provided within the first contact and groove pathway in combination defining a first metal layer, the first metal layer having an overall thickness which is sufficient to fill the first contact and groove pathway; f) planarizing the first metal layer back to the uppermost region to form a conductive metal runner within the groove pathway; g) providing an overlying layer of insulating material which is different in composition from the