Abstract: A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.

Abstract: A method for fabricating a semiconductor device to minimize a terminal effect in an ECP process is disclosed. The method for fabricating a semiconductor device to minimize a terminal effect in an ECP process, comprises depositing a barrier metallic layer on the top of a damascene pattern formed through an etching process, forming an Ag seed layer by employing a heating process for the reaction of the surface of the barrier metallic layer and a NH3 solution of AgNO3 and reductive materials in a reactor, plating a Cu layer by using the Ag seed layer through an ECP process and forming a Cu interconnect through an annealing process and a Cu CMP process. The method for fabricating a semiconductor device according to the present invention provides the improvement of uniformity by forming a seed layer with low-resistivity regardless of a thin thickness in order to avoid a terminal effect in an ECP process.

Abstract: Methods of forming a roughened surface through diffusion-enhanced crystallization of an amorphous material are disclosed. In one aspect, conductive hemispherical grain silicon can be formed through dopant diffusion-enhanced crystallization of one or more layers of amorphous silicon. To further enhance uniformity in the formation of the hemispherical grain silicon, the exposed surface of the amorphous silicon can be seeded before crystallization to further enhance uniformity of the surface structures formed in the hemispherical grain silicon.

Abstract: A metal salicide layer is formed by sequentially depositing a physical vapor deposition (PVD) metal layer and a chemical vapor deposition (CVD) metal layer on a semiconductor device having an exposed silicon surface so as to form a double metal layer. The semiconductor device is annealed to react the double metal layer with the silicon surface. At least a portion of the double layer that has not reacted with the silicon surface is stripped. The semiconductor device is annealed after stripping at least the portion of the double metal layer.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer over the semiconductor substrate and the gate electrode. An insulating layer may have a via hole connected to the semiconductor substrate or the gate electrode and a trench connected to the via hole. A first barrier layer and a second barrier layer may be formed. The first barrier layer and the second barrier layer may be annealed to form a silicide and combine the first barrier layer and the second barrier layer to form a metal compound.

Abstract: Provided are exemplary methods for forming a semiconductor devices incorporating silicide layers formed at temperatures below about 700° C., such as nickel silicides, that are formed after completion of a silicide blocking layer (SBL). The formation of the SBL tends to deactivate dopant species in the gate, lightly-doped drain and/or source/drain regions. The exemplary methods include a post-SBL activation anneal either in place of or in addition to the traditional post-implant activation anneal. The use of the post-SBL anneal produces CMOS transistors having properties that reflect reactivation of sufficient dopant to overcome the SBL process effects, while allowing the use of lower temperature silicides, including nickel silicides and, in particular, nickel silicides incorporating a minor portion of an alloying metal, such as tantalum, the exhibits reduced agglomeration and improved temperature stability.

Abstract: A semiconductor device having a random grained polysilicon layer and a method for its manufacture are provided. In one example, the device includes a semiconductor substrate and an insulator layer on the substrate. A first polysilicon layer having a random grained structure is positioned above the insulator layer, a semiconductor alloy layer is positioned above the first polysilicon layer, and a second polysilicon layer is positioned above the semiconductor alloy layer.

Abstract: A process for forming a pattern contains steps of: forming a first mask pattern on a film to be etched on a substrate; forming a first pattern of the film to be etched by using the first mask pattern as a mask; forming a second mask pattern having a plane shape different from that of the first mask pattern by deforming the first mask pattern; and forming a second pattern of the film to be etched different from the first pattern by using the second mask pattern. By applying the process for forming a pattern, for example, to the formation of a semiconductor layer and source and drain electrodes of a TFT substrate of a liquid crystal display apparatus, the above-stated formation requiring two photoresist process steps in a conventional manufacturing method of a liquid crystal display apparatus can be carried out by only one process step, thereby reducing manufacturing cost thereof.

Abstract: The invention provides a semiconductor device, and a manufacturing method, comprising a semiconductor substrate, a gate insulating film, a gate electrode, and a source-drain diffusion layer. A silicide film is formed on the gate electrode and the source-drain diffusion layer. The silicide film is thicker on the gate electrode than on the source-drain diffusion layer. The manufacturing method comprises forming a gate electrode on a gate insulating film, followed by forming a source-drain diffusion layer. Then, atoms inhibiting a silicidation are selectively introduced into the source-drain diffusion layer, and a high melting point metal film is formed on the gate electrode and the source-drain diffusion layer. The high melting point metal film is converted into silicide films selectively on the gate electrode and the source-drain diffusion layer.

Abstract: The present invention is directed to a method of manufacturing silicide used to reduce a contact resistance at a contact of a semiconductor device and a semiconductor device with the silicide manufactured by the same method. The method comprises the steps of: (a) cleaning a semiconductor substrate with a transistor formed thereon, the transistor including a source electrode, a drain electrode and a gate electrode; (b) placing the cleaned semiconductor substrate into a sputter chamber in a deposition equipment, and forming silicide at the same time of depositing a metal film under a state where the semiconductor substrate is heated at a temperature of 450-600° C.; (c) removing residual metal film not used for the formation of silicide; and (d) annealing the semiconductor substrate.

Abstract: A phase-change memory cell may be formed by selectively depositing the lower electrode in the phase-change memory pore. Thereafter, an adhesion-promoting material may be selectively deposited on the selectively deposited lower electrode and the upper surface surrounding the pore. Through the use of selective deposition techniques, the adhesion-promoting material can be positioned where needed and the lower electrode may be defined in a fashion that may reduce shunting current, reduce device current requirements, and increase dynamic range in some embodiments.

Abstract: A method of forming a conductive structure is disclosed. The method includes forming an interconnect in a substrate, and forming a layer of iridium on the interconnect. The layer of iridium has a thickness of less than six hundred angstroms. The method further includes annealing the layer of iridium, forming a dielectric layer on the layer of iridium, and forming a conductive layer on the dielectric layer.

Abstract: A process for manufacturing a wiring board comprising a substrate made of an insulation material and having first and second surfaces, first and second conductor patterns formed on the first and second surfaces, respectively, and a via conductor penetrating the substrate to electrically connect the first conductor pattern with the second conductor pattern; the process comprising the following steps of: forming the substrate with a through-hole penetrating thereto and defining openings at the first and second surfaces, respectively; plating the substrate with a metal so that a metal layer having a predetermined thickness is formed on the respective first and second surfaces of the substrate and the through-hole is substantially filled with the metal to be the via conductor; irradiating a laser beam, as a plurality of spots, around a metal-less portion of the plated metal, such as a dimple or seam, at positions corresponding to the openings of the through-hole, so that the a part of the plated metal melts to fi

Abstract: A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics are to be disposed. An oxide is formed over the surfaces. A silicon layer is formed over the oxide layer. A nitridation process is performed. An optional high temperature annealing step may be performed.

Abstract: A method by which a silicon wafer is prevented from increasing boron concentration near the surface and difference in the boron concentration does not arise between the surface of the annealed wafer and the silicon bulk to eliminate boron contamination in the silicon wafer caused by an annealing treatment is provided. The method includes, when annealing a silicon wafer having a surface on which a native oxide film has formed and boron of environmental origin or from chemical treatment prior to annealing has deposited, steps of carrying out temperature heat-up in a mixed gas atmosphere having a mixing ratio of hydrogen gas to inert gas of 5% to 100% so as to remove the boron-containing native oxide film, followed by annealing in an inert gas atmosphere.

Abstract: Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing process to form a copper wiring within a damascene pattern. At this time, the chemical mechanical polishing process is overly performed so that the top surface of the copper wiring is concaved and is lower than the surface of the interlayer insulating film of the low dielectric constant neighboring it. Furthermore, an annealing process is performed so that the top surface of the copper wiring is changed from the concaved shape to a convex shape while stabilizing the copper wiring. A copper anti-diffusion insulating film is then formed on the entire structure including the top surface of the copper wiring having the convex shape.

Abstract: The present teachings and illustrations describe a process for forming a plurality of conductive structures in or on a substrate. In one embodiment, the process comprises forming a plurality of recesses in or on the substrate, wherein the plurality of recesses include recesses having different dimensions. In addition, the process further comprises (i) forming a conductive layer which at least partially fills the plurality of recesses and (ii) treating the conductive layer to improve the conductive properties of the conductive layer. Moreover, the process still further comprises (iii) sequentially repeating acts (i) and (ii) until each of the recesses of the plurality of recesses are filled to a desired dimension and such that the conductive material in the recesses of smaller dimension are more uniformly adhered to the bottom surfaces of the recesses.

Abstract: A method of making a matrix type piezoelectric/electrostrictive device having a plurality of pillar shaped piezoelectric/electrostrictive elements, each having a piezoelectric/electrostrictive substance and at least a pair of electrodes being formed on the sides of the substance, are vertically provided on a thick ceramic substrate, such that the device is driven by displacement of the piezoelectric/electrostrictive substance. In this device, the piezoelectric/electrostrictive elements are integrally bonded to the ceramic substrate and independently arranged in two dimensions. The percentage of transgranularly fractured crystal grains on at least the sides of the piezoelectric/electrostrictive substance on which the electrodes are formed is 10% or less. The unit forms a curved surface near a joined section between the substance and the substrate.

Abstract: The disclosure relates to a method and apparatus for enhancing copper film quality with a two-step deposition. The two step deposition may include depositing a first copper film by electrochemical plating, annealing the first copper film at a desired temperature for a duration of time to remove any impurities, depositing a second copper film and annealing the second copper film for a duration of time to remove impurities. The second copper film can be deposited by electrochemical plating without HCl/C-based additive. The second copper film can also be deposited by sputtering to avoid impurities including C, Cl and S.

Abstract: A magnetic tunnel junction device with a compositionally modulated electrode and a method of fabricating a magnetic tunnel junction device with a compositionally modulated electrode are disclosed. An electrode in electrical communication with a data layer of the magnetic tunnel junction device includes a high resistivity region that has a higher resistivity than the electrode. As a result, a current flowing through the electrode generates joule heating in the high resistivity region and that joule heating increases a temperature of the data layer and reduces a coercivity of the data layer. Consequently, a magnitude of a switching field required to rotate an alterable orientation of magnetization of the data layer is reduced. The high resistivity region can be fabricated using a plasma oxidation, a plasma nitridation, a plasma carburization, or an alloying process.

Abstract: A multilayer interconnection board is disclosed that allows reliable electrical connection between an interconnection having a large width and a large area and a via provided in a via hole formed by pressing a tool against resin. A projecting portion for electrical connection is formed integrally with the insulating member and in a second interconnection groove having a width and an area greater than those of a first interconnection groove. While a first interconnection is being deposited in the first interconnection groove and a second interconnection is being deposited in the second interconnection groove, the projecting portion is formed in the second interconnection groove and a metal plating film is provided on the projecting portion at the same time, so as to electrically connect the second interconnection with the via.

Abstract: On a substrate are sequentially formed a first interconnection 203, a diffusion barrier film 205 and a second insulating film 207, and on the upper surface of the second insulating film 207 is then formed a sacrificial film 213. Next, a via hole 211 and an interconnection trench 217 are formed, and on the sacrificial film 213 are then formed a barrier metal film 219 and a copper film 221. CMP for removing the extraneous copper film 221 and barrier metal film 219 are conducted in a two-step process, i. e., the first polishing where polishing is stopped on the surface of the barrier metal film 219 and the second polishing where the remaining barrier metal film 219 and the tapered sacrificial film 213 are polished.

Abstract: A multi-layer piezoelectric component includes a plurality of piezoelectric layers, a first inner electrode sheet, a second inner electrode sheet, a first outer electrode, and a second outer electrode. The piezoelectric layers are wound around an axis to form a laminar roll having first and second end faces transverse to the axis. The piezoelectric layers include at least one first layer and at least one second layer. Each of the first and second layers has opposite first and second edges respectively at the first and second end faces, and opposite inner and outer circumferential surfaces. The first and second inner electrode sheets respectively overlie the inner circumferential surfaces of the first and second layers. The first and second outer electrodes are respectively and electrically connected to the first and second inner electrode sheets.

Abstract: A method of making a semiconductor device is described. That method includes forming a copper containing layer on a substrate, and forming an alloying layer that includes an alloying element on the copper containing layer. After applying heat to cause an intermetallic layer that includes copper and the alloying element to form on the surface of the copper containing layer, a barrier layer is formed on the intermetallic layer.

Abstract: A device for thermally treating semiconductor wafers having at least one silicon layer to be oxidized and a metal layer, preferably a tungsten layer, which is not to be oxidized. The inventive device comprises the following: at least one radiation source; a treatment chamber receiving the substrate, with at least one wall part located adjacent to the radiation sources and which is substantially transparent for the radiation of said radiation source; and at least one cover plate between the substrate and the wall part of the treatment chamber located adjacent to the radiation sources, the dimensions of said cover plate being selected such that it fully covers the transparent wall part of the treatment chamber in relation to the substrate in order to prevent material, comprising a metal, metal oxide or metal hydroxide such as tungsten, tungsten oxide or tungsten hydroxide, from said substrate from becoming deposited on or evaporating onto the transparent wall part of the treatment chamber.

Abstract: An Al3Ti film having a large amount of dissolved Si is deposited on a semiconductor substrate to form a laminate with an Al wiring film, and heat treatment is performed at a temperature of at least 400° C., to thereby absorb excessive Si into the Al3Ti film and so prevent the occurrence of Si nodules. By depositing Al film at a temperature of at least 400° C. at the time of depositing the Al wiring film on the Al3Ti film, excessive Si is caused to be absorbed in the Al3Ti film. Further, at the time of depositing a Ti film on the semiconductor substrate and depositing the Al wiring film, the Al film is deposited at a temperature of a least 400° C., there is reaction between the Ti film within the laminate, causing an Al3Ti film to be produced, and excessive Si is absorbed in the Al3 Ti film produced.

Abstract: An embodiment of the invention is a method of manufacturing copper interconnects 30 on a semiconductor wafer 10 where an electroplating process is used to deposit a first layer of copper grains 30d having an initial grain size and a second layer of copper grains 30e having a different initial grain size.

Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved

Abstract: A novel method for preventing the formation of voids in metal interconnects fabricated on a wafer, particularly during a thermal anneal process, is disclosed. The method includes fabricating metal interconnects between metal lines on a wafer. During a thermal anneal process carried out to reduce electrical resistance of the interconnects, the wafer is positioned in spaced-apart relationship to a wafer heater. This spacing configuration facilitates enhanced stabilility and uniformity in heating of the wafer by reducing the presence of particles on and providing a uniform flow of heated air or gas against and the wafer backside. This eliminates or at least substantially reduces the formation of voids in the interconnects during the anneal process.

Abstract: A method is provided wherein a gate dielectric film that is plasma nitrided in a chamber of one system is subsequently heated or “annealed” in another chamber of the same system. Processing delay can be controlled so that all wafers processed in the system experience similar nitrogen content.

Abstract: A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided. In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used.

Abstract: The resist film is provided on the surface of the substrate having electrodes, and openings are provided in the resist film at positions of the electrodes on the substrate. The first metal is supplied into the openings. The first metal is then heated to melt and coagulate it. The second metal is then supplied into the openings on the first metal. The first metal and the second metal are heated to melt and coagulate them. The resist film is finally removed. By this method, excellent solder bumps can be formed on the substrate without remnants of the resist film being left on the substrate.

Abstract: A method and apparatus for processing a thin metal layer on a substrate to control the grain size, grain shape, and grain boundary location and orientation in the metal layer by irradiating the metal layer with a first excimer laser pulse having an intensity pattern defined by a mask to have shadow regions and beamlets. Each region of the metal layer overlapped by a beamlet is melted throughout its entire thickness, and each region of the metal layer overlapped by a shadow region remains at least partially unmelted. Each at least partially unmelted region adjoins adjacent melted regions. After irradiation by the first excimer laser pulse, the melted regions of the metal layer are pemitted to resolidify. During resolidification, the at least partially unmelted regions seed growth of grains in adjoining melted regions to produce larger grains.

Abstract: An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed portion of the surface of the first layer and a second layer of conductive material is formed on the conductive binding layer. The binding layer can be an oxide and the second layer a conductive material that is diffusible into an oxide. The electrode structure can be annealed to cause conductive material from the second layer to be chemisorbed into the binding layer to improve adhesion between the first and second layers. A programmable cell can be formed by forming a doped glass layer in the electrode structure.

Abstract: A method of annealing a metal layer on a substrate in a chamber is provided. The method comprises positioning a substrate with a metal layer thereon in a chamber, removing atmospheric gases from the chamber, providing process gas to the chamber, and annealing the metal layer at a temperature greater than about 80 degrees Celsius. Also provided is a method of forming a feature on a substrate. The method comprises depositing a dielectric layer on the substrate, forming at least one opening within the dielectric layer, depositing a metal layer in the opening, positioning the substrate in an annealing chamber, removing atmospheric gases from the annealing chamber, providing process gas to the annealing chamber, and annealing the metal layer at temperature greater than about 80 degrees Celsius.

Abstract: A copper filled semiconductor feature and method of forming the same having improved bulk properties the method including providing a semiconductor process wafer having a process surface including an opening for forming a semiconductor feature; depositing at least one metal dopant containing layer over the opening to form a thermally diffusive relationship to a subsequently deposited copper layer; depositing said copper layer to substantially fill the opening; and, thermally treating the semiconductor process wafer for a time period sufficient to distribute at least a portion of the metal dopants to collect along at least a portion of the periphery of said copper layer including a portion of said copper layer grain boundaries.

Abstract: A system and method is disclosed for minimizing increases in via resistance by applying a nitrogen plasma after a titanium liner deposition. A via in a semiconductor device is formed by placing a metal layer on a substrate and placing a layer of anti-reflective coating (ARC) titanium nitride (TiN) over the metal layer. A layer of dielectric material is placed over the ARC TiN layer and a via passage is etched through the dielectric and partially through the ARC TiN layer. A titanium layer is then deposited and subjected to a nitrogen plasma process. The nitrogen plasma converts the titanium layer to a first layer of titanium nitride. The first layer of titanium nitride does not react with fluorine to form a high resistance compound. Therefore the electrical resistance of the first layer of titanium nitride does not significantly increase during subsequent thermal cycles.

Abstract: After a p-seat electrode-forming layer is laminated onto a light-transmissive electrode-forming layer, a first heating step and a second heating step are carried out for alloying the two layers. In the first heating step, heat treatment is performed at a relatively low temperature in an atmosphere containing oxygen. In the second heating step, heat treatment is performed at a relatively high temperature in an atmosphere not containing oxygen.

Abstract: A method of forming a tantalum nitride layer for integrated circuit fabrication is disclosed. In one embodiment, the method includes forming a tantalum nitride layer by chemisorbing a tantalum precursor and a nitrogen precursor on a substrate disposed in a process chamber. A nitrogen concentration of the tantalum nitride layer is reduced by exposing the substrate to a plasma annealing process. A metal-containing layer is then deposited on the tantalum nitride layer by a deposition process.

Abstract: The present invention relates to a method of forming a copper wiring in a semiconductor device. A copper wiring is formed within a damascene pattern. Before a copper anti-diffusion insulating film is formed on the entire structure, a specific metal element is doped into the surface of the copper wiring and the surface of its surrounding insulating film to form a metal element-doping layer. The doped specific metal element reacts with surrounding other elements, due to heat upon depositing the copper anti-diffusion insulating film and a low dielectric constant interlayer insulating film and additional annealing process. For this reason, a copper alloy layer and a metal oxide layer are stacked at the interface of the copper wiring and the copper anti-diffusion insulating film and the metal oxide layer is formed at the interface of the insulating film and the copper anti-diffusion insulating film.

Abstract: A porous, flexible, resilient heat transfer material which comprises network of metal flakes. Such heat transfer materials are preferably produced by first forming a conductive paste comprising a volatile organic solvent and conductive metal flakes. The conductive paste is heated to a temperature below the melting point of the metal flakes, thereby evaporating the solvent and sintering the flakes only at their edges. The edges of the flakes are fused to the edges of adjacent flakes such that open pores are defined between at least some of the adjacent flakes, thereby forming a network of metal flakes. This network structure allows the heat transfer material to have a low storage modulus of less than about 10 GPa, while having good electrical resistance properties.

Abstract: The invention provides methods which can be used to structure even precious metal electrodes with conventional CMP steps, in particular with the aid of conventional slurries such as are already used to structure non-precious metals. Owing to the formation of an alloy, the chemically active components of the slurry are capable of attacking the additive to the precious metal in the alloy, as a result of which the surface of the alloy layer is roughened and the mechanical removal of the precious metal is increased.

Abstract: Apparatus and method for treating a surface of a substrate for electrolytic or electroless plating of metals in integrated circuit manufacturing. In one embodiment the method includes forming a barrier layer on a substrate. A metal-seed layer is then formed on the barrier layer. The method continues by performing in situ surface treatment of the metal-seed layer to form a passivation layer on the metal-seed layer. In another embodiment of a method of this invention, a substrate is provided into an electroplating tool chamber. The substrate has a barrier layer formed thereon, a metal seed layer formed on the barrier layer and a passivation layer formed over the metal seed layer. The method continues by annealing the substrate in forming gas to reduce the passivation layer. A conductive material is deposited on the substrate using an electrolytic plating or electroless plating process.

Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The method comprises depositing a conductive material over a substrate to fill a contact opening, removing excess material from the substrate leaving the contact within the opening, and then heating treating the contact at a high temperature, preferably with a rapid thermal anneal process, in a reactive gas to remove an undesirable component from the contact, for example, thermal annealing a TiCl4-based titanium nitride in ammonia to remove chlorine from the contact, which can be corrosive to an overlying aluminum interconnect at a high concentration. The contacts are useful for providing electrical connection to active components in integrated circuits such as memory devices. In an embodiment of the invention, the contacts comprise boron-doped and/or undoped TiCl4-based titanium nitride having a low concentration of chlorine.

Abstract: A method for manufacturing an electronic device for signal transmission includes winding a wire of at least one electronic element onto a winding portion of an inner terminal of a lead of a packaging casing, displacing the at least one electronic element away from the inner terminal to a side of the packaging casing that is distal to the inner terminal, immersing the winding portion of the inner terminal and the wire in a bath of molten solder, and removing the inner terminal and the wire from the bath of the molten solder so that the winding portion of the inner terminal forms a welded portion for reliably and electrically connecting the inner terminal to the wire. Preferably, electrical connection between the inner terminal and the wire is tested after the step of removing the inner terminal and the wire from the bath of the molten solder.

Abstract: A method of fabricating a resistor in which the resistance value of the resistor is measured and adjusted after silicidation is provided. The method of the present invention begins with first providing at least one resistor, e.g., polysilicon, having a resistance value on a surface of a semiconductor substrate. The at least one resistor has been subjected to a silicidation process. Next, the resistance value of the at least one resistor is measured to determine the actual resistance of the resistor after silicidation. After the measuring step, the resistance of the resistor is adjusted to achieve a desired resistance value. The adjusting may include a post silicidation rapid thermal anneal and/or a post silicidation ion implantation and a low temperature rapid thermal anneal step.

Abstract: A contact plug is formed in a semiconductor device having a silicon substrate having a gate electrode, a junction area and an insulating interlayer. A contact hole is formed to expose the junction area. A plasma process is carried out with respect to a resultant substrate, thereby removing natural oxides created on an exposed surface of the junction area. A first silicon layer is deposited on the contact hole and on the insulating interlayer. A heat-treatment process is carried out with respect to the first silicon layer so as to grow the amorphous silicon into the epitaxial silicon. A second silicon layer is deposited on the first silicon layer.

Abstract: A method of the production of a nanoparticle dispersed composite material capable of controlling a particle size and a three dimensional arrangement of the nanoparticles is provided. The method of the production of a nanoparticle dispersed composite material of the present invention includes a step (a) of arranging a plurality of core fine particle-protein complexes having a core fine particle, which comprises an inorganic material, internally included within a protein on the top surface of a substrate, a step (b) of removing the protein, a step (c) of conducting ion implantation from the top surface of the substrate, and a step (d) of forming nanoparticles including the ion implanted by the ion implantation as a raw material, inside of the substrate.

Abstract: A method of production of a multilayer ceramic capacitor or other multilayer ceramic electronic device with few structural defects and improved highly accelerated life, that is, a method of production of a multilayer ceramic electronic device having a firing step of firing a stack comprised of a dielectric layer paste and an internal electrode layer paste including a base metal alternately arranged in a plurality of layers, a first annealing step of annealing, at a temperature T1 of 600 to 900° C., the stack after firing and a second annealing step of annealing, at a temperature T2 of 900 to 1200° C. (however, excluding 900° C.), the stack after said first annealing.

Abstract: A semiconductor device, and a method of fabricating the same, includes cobalt as a capping layer. An interconnection structure of the semiconductor device has an improved via resistance. In the semiconductor device, a single cobalt layer or a composite film including a cobalt layer and a titanium nitride layer is used as the capping layer of a metal layer.