Abstract: The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

Abstract: A semiconductor substrate is inserted into a heat treatment apparatus at a low temperature ranging from room temperature to about 50° C., and organic substances included in a metal on the semiconductor substrate are released without carbonization in an annealing process before CMP. Further, organic substances capable of preventing the corrosion of the metal are decomposed, and the organic substances themselves and chlorine, sulfuric acid, and ammonia which are included in the organic substances are diffused out of the metal film by setting the heat treatment apparatus at a rate of temperature rise of 15° C./min or less until a prescribed heat treatment temperature is reached.

Abstract: An amorphous silicon (Si) film is taken to form a metal silicide of Si—Al(aluminum) under a high temperature. Al atoms is diffused into the amorphous Si film for forming the metal silicide of Si—Al as nucleus site. Then through heating and annealing, a microcrystalline or nano-crystalline silicon thin film is obtained. The whole process is only one process and is done in only one reacting chamber.

Abstract: The present invention prevents the diffusion of an aluminum element into a polysilicon layer in a heating step when an aluminum-based conductive layer is used in a source/drain electrode which is in contact with low-temperature polysilicon whereby the occurrence of defective display can be obviated. An aluminum-based conductive layer is used in a source/drain electrode and a barrier layer made of molybdenum or a molybdenum alloy layer is formed between the aluminum-based conductive layer and a polysilicon layer. Further, a molybdenum oxide nitride film formed by the rapid heat treatment (rapid heat annealing) in a nitrogen atmosphere is formed over a surface of the molybdenum or the molybdenum alloy which constitutes the barrier layer.

Abstract: A method of forming a semiconductor device that includes heating a wafer on which an Al—Cu sputtering thin film is formed before patterning the Al—Cu sputtering thin film. The heating is performed at a temperature no less than a solid solution temperature of copper or at a temperature between 300° C. and 600° C. The process temperature in heating the process wafer is not higher than the flow temperature of aluminum or is the temperature at which a reflow process can be performed.

Abstract: A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.

Abstract: A selective electroless plating operation provides for the selective deposition of a metal film only on exposed silicon surfaces of a semiconductor substrate and not on other surfaces such as dielectric surfaces. The plating solution includes metal ions and advantageously also includes dopant impurity ions. The pure metal or metal alloy film formed on the exposed silicon surfaces is then heat treated to form a metal silicide on the exposed silicon surfaces and to drive the dopant impurities to the interface formed between the exposed silicon surfaces and the metal silicide film.

Abstract: The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing.

Abstract: There is described a method for producing a packaged integrated circuit. The method comprises a first step of building an integrated circuit having a micro-structure suspended above a micro-cavity, and having a heating element on the micro-structure capable of heating itself and its immediate surroundings. A layer of protective material is then deposited on said micro-structure such that at least a top surface of the micro-structure and an opening of the micro-cavity is covered, wherein the protective material is in a solid state at room temperature and can protect the micro-structure during silicon wafer dicing procedures and subsequent packaging. The integrated circuit is packaged and an electric current is passed through the heating element such that a portion of the protective material is removed and an unobstructed volume is provided above and below the micro-structure.

Abstract: A die, comprising a substrate and one or more pillar structures formed over the substrate in a pattern and the method of forming the die.

Abstract: A method of forming a metal silicide layer includes sequentially forming a metal layer and a first capping layer on a substrate, performing a first heat treatment on the substrate to cause the substrate to react to the metal layer, removing the first, capping layer and an unreacted metal layer, forming a second capping layer on the substrate, and performing a second heat treatment on the substrate to form a metal silicide layer on the substrate.

Abstract: The present invention relates to an electrically conductive composition for filling via-holes formed in an electronic circuit substrate containing an electrically conductive metal and a vehicle, wherein the content of the electrically conductive metal is 57 vol % or more, and the composition is a plastic fluid for which fluidity increases when external pressure is applied to the composition.

Abstract: A semiconductor device includes a first insulating film that includes a first opening reaching a substrate and that is provided on the substrate, a second insulating film that includes a second opening reaching the substrate through the first opening of the first insulating film and that covers the first insulating film, and a conductive pattern that is provided on the second insulating film so as to be in contact with the substrate through the second opening of the second insulating film.

Abstract: In a MOSFET, after an element region is formed, a wiring layer is formed subsequently to a barrier metal layer, and hydrogen annealing is performed. However, in the case of an n-channel MOSFET, a threshold voltage is lowered due to an occlusion characteristic of the barrier metal layer. Thus, an increased impurity concentration in a channel layer causes a problem that reduction in an on-resistance is inhibited. According to the present invention, after a barrier metal layer is formed, an opening is provided in the barrier metal layer on an interlayer insulating film, and hydrogen annealing treatment is performed after a wiring layer is formed. Thus, an amount of hydrogen which reaches a substrate is further increased, and lowering of a threshold voltage is suppressed. Moreover, since an impurity concentration in a channel layer can be lowered, an on-resistance is reduced.

Abstract: In some methods of fabricating a silicon-on-insulator substrate, a semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A first insulating film is formed on the defined region of the semiconductor substrate with an opening that exposes a portion of the defined region of the semiconductor substrate having the single crystalline structure. A first non-single crystalline film is formed on the exposed portion of the semiconductor substrate and that at least substantially fills the opening in the first insulating film. A laser beam is generated that heats the first non-single crystalline film to change the first non-single crystalline film into a first single crystalline film having substantially the same single crystalline structure as the defined region of the semiconductor substrate.

Abstract: A first conductive layer is formed, a composition layer over the first conductive layer is formed by discharging a composition in which nanoparticles comprising a conductive material covered with an organic material are dispersed in a solvent, and the composition layer is dried. Subsequently, pretreatment is performed in which the organic material covering the nanoparticles, which are positioned on a surface of the composition layer, is decomposed, and then baking is performed. In this manner, a second conductive layer is formed by sintering nanoparticles which are positioned on a surface of the composition layer. A memory layer is formed between the first conductive layer and the second conductive layer using the nanoparticles covered with the organic materials to which the pretreatment is not performed.

Abstract: A nanostructure includes a nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A nanostructure in another embodiment includes a substrate having an area with a nanofeature; and a nanowire extending from the nanofeature, the nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A method for forming a nanostructure is also presented. A method for reading and writing data is also presented. A method for preparing nanoparticles is also presented.

Abstract: Compositions and methods for depositing elemental metal M(0) films on semiconductor substrates are disclosed. One of the disclosed methods comprises: heating the semiconductor substrate to obtain a heated semiconductor substrate; exposing the heated semiconductor substrate to a composition containing a metal precursor, an excess amount of neutral labile ligands, and a supercritical solvent; exposing the metal precursor to a reducing agent and/or thermal energy at or near the heated semiconductor substrate; reducing the metal precursor to the elemental metal M(0) by using the reducing agent and/or the thermal energy; and depositing the elemental metal M(0) film while minimizing formation of metal oxides.

Abstract: The present invention provides a method for producing thin nickel (Ni) monosilicide or NiSi films (having a thickness on the order of about 30 nm or less), as contacts in CMOS devices wherein an amorphous Ni alloy silicide layer is formed during annealing which eliminates (i.e., completely by-passing) the formation of metal-rich silicide layers. By eliminating the formation of the metal-rich silicide layers, the resultant NiSi film formed has improved surface roughness as compared to a NiSi film formed from a metal-rich silicide phase. The method of the present invention also forms Ni monosilicide films without experiencing any dependence of the dopant type concentration within the Si-containing substrate that exists with the prior art NiSi films.

Abstract: A photoresist pattern is formed on an insulating substrate so that it has a reverse tapered cross section and a reverse pattern of a wiring pattern to be formed. Next, a nanoparticles-containing ink is injected on a wiring region using an inkjet system, followed by a leveling process, a drying process, a resist separation process and a baking process. Thus a wiring pattern is formed.

Abstract: A metallic, semiconductor, dielectric or oxide layer, such as a thin gate oxide, is formed by supplying a wafer in a processing chamber with thermal energy to heat the wafer and light energy, such as laser light at a selected wavelength, to improve the quality of the resulting layer. The laser light may be focused and/or scanned to control the depth and spatial extent of laser processing.

Abstract: A nitride semiconductor device according to the present invention includes a P-type contact layer and a P-type electrode provided on the P-type contact layer. The P-type electrode includes a AuGa film provided on the P-type contact layer, a Au film provided on the AuGa film, a Pt film 4 provided on the Au film, and a Au film provided on the Pt film. The ratio of the thickness of the AuGa film to the total thickness of the AuGa film and the Au film is not less than 12% but not more than 46%.

Abstract: By improving the purity of metal lines and the crystalline structure, the overall performance of metal lines, especially of highly scaled copper-based semiconductor devices, may be enhanced. The modification of the crystalline structure of the metal lines may be performed by a heat treatment generating locally restricted heating zones, which are scanned along the length direction of the metal lines, and/or a heat treatment comprising a heating step in a vacuum ambient followed by a heating step in a reducing ambient.

Abstract: The capacitor in a semiconductor device includes a substrate, a lower electrode formed over the substrate, a diffusion barrier formed over the lower electrode, a plurality of agglomerates formed over the diffusion barrier, a dielectric layer formed over the surface of the agglomerates to form an uneven surface, and an upper electrode formed over the dielectric layer.

Abstract: A serial thermal processing arrangement for treating a wafer of semiconductor material, the steps including: loading the wafer into a chamber at an initial station and purging the chamber with nitrogen gas; introducing formic acid vapor and nitrogen and heating the wafer at ambient; introducing a vacuum and heat onto the wafer; introducing formic acid vapor and nitrogen, heating the wafer at ambient; introducing nitrogen gas, and cooling the wafer at ambient; and lastly, unloading the wafer from its chamber.

Abstract: A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion problem that limits the inversion capacitance in the conventional CMOS gate stack. To integrate the poly-SiGe layer into the gate stack, a thin ?-Si layer is deposited between the gate dielectric layer and the poly-SiGe layer. To ensure proper salicide formation, a poly-Si layer is capped over the poly-SiGe layer. In order to obtain a fined-grained poly-Si over poly-SiGe, a second ?-Si layer is deposited between the poly-Si layer and the poly-SiGe layer.

Abstract: A method of integrated processing is provided for a substrate in the substrate processing tool. The substrate contains an etch feature in a dielectric film and an exposed metal interconnect pattern formed underneath the etch feature. The integrated process includes pretreating exposed surfaces of the etch feature and the exposed metal interconnect pattern with a flow of hydrogen radicals generated by thermal decomposition of H2 gas by a hot filament hydrogen radical source separated from the substrate by a showerhead plate containing gas passages facing the substrate. The integrated process further includes depositing a barrier metal film over the pretreated exposed surfaces, and forming a Cu metal film on the barrier metal film.

Abstract: A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

Abstract: A copper film is annealed at high pressure to enhance grain growth and remove voids. Other films, such as dielectrics, may also be suitable. High pressure can be used in conjunction with temperatures lower than room temperature for annealing or higher temperatures may be used to further enhance grain growth.

Abstract: Cu-based interconnections are fabricated in a semiconductor device by depositing a thin film of Cu or Cu alloy on a dielectric film by sputtering, the dielectric film having trenches and/or via holes at least one groove and being arranged on or above a substrate, and carrying out high temperature and high pressure treatment to thereby embed the Cu or Cu alloy into the trenches and/or via holes, in which the sputtering is carried out at a substrate temperature of ?20° C. to 0° C. using, as a sputtering gas, a gaseous mixture containing hydrogen gas and an inert gas in a ratio in percentage of 5:95 to 20:80.

Abstract: Method for manufacturing a parylene-based electrode array that includes an underlying parylene layer, one or more patterned electrode layers comprising a conductive material such as a metal, and one or more overlying parylene layers. The overlying parylene is etched away or otherwise processed to expose the electrodes where stimulation or recording is to occur. All other conductive material in the device is occluded from the environment by the two layers of parylene surrounding it.

Abstract: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.

Abstract: The object of the disclosure is to measure temperature using pyrometers, in a simple and economic way, enabling precise temperature measurement, even for low temperatures. The disclosure presents an apparatus and method for thermally treating substrates, wherein the substrate is exposed to at least a first and at least a second radiation; the predetermined wavelengths of the first radiation are absorbed between the first radiation source and the substrate; a radiation from the substrate is measured in the predetermined wavelength using a radiation detector arranged on the same side as a second radiation source; the second radiation from the second radiation source is modulated and determined.

Abstract: After carrying an LCD substrate in a reaction container of a heat treatment unit, blowing a previously heated helium gas from a gas supply part, which opposes to the surface of the LCD substrate, over the entire surface of the LCD substrate. The temperature of the LCD substrate is raised by radiation heat of a heater and heat exchange with the helium gas. After performing CVD or annealing in the reaction container, cooling the LCD substrate by blowing a gas for heat exchange having a temperature about a room temperature from the gas supply part over the entire surface of the LCD substrate. Return the cooled LCD substrate to a carrier in the carrier chamber via a conveyance chamber.

Abstract: A method of forming a barrier layer for a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on the surfaces of the high aspect ratio openings including the vertical side walls and depositing a metal barrier layer comprising the barrier metal on the first barrier layer. The method further includes reflowing the metal barrier layer by (a) directing light from an array of continuous wave lasers into a line of light extending at least partially across the thin film structure, and (b) translating the line of light relative to the thin film structure in a direction transverse to the line of light.

Abstract: A control circuit includes a drive circuit which applies a drive voltage to a semiconductor device having an overheating protection function according to an externally supplied signal; and a current detecting circuit which outputs a detection signal when a drive current flowing through the semiconductor device exceeds a predetermined threshold current. The semiconductor device incorporates a semiconductor element, a temperature detecting circuit for detecting temperature increase of a chip, and an interrupting circuit for interrupting an input to the semiconductor element according to a detection output of the temperature detecting circuit.

Abstract: To provide a technology capable of improving reliability and manufacturing yield of a semiconductor device by reducing variations of electrical characteristics in connection hole portions. After a semiconductor wafer is placed over a wafer stage provided in a chamber for dry cleaning treatment of a deposition system, dry cleaning treatment is performed to a principal surface of the semiconductor wafer by supplying reducing gas, sequentially, heat treatment is performed to the semiconductor wafer at a first temperature of 100 to 150° C. by a showerhead which is maintained at 180° C. Next, after the semiconductor wafer is vacuum transferred from the chamber to a chamber for heat treatment, heat treatment is performed to the semiconductor wafer at a second temperature of 150 to 400° C. in the chamber, thereby removing a product remaining over the principal surface of the semiconductor wafer.

Abstract: A Ni2Si-nSiC Ohmic contact is formed by pulsed laser ablation deposition (PLD) of Ni2Si source target deposited on a n-SiC substrate or SiC substrate wafer with SiC epilayer. The Ni2Si Ohmic contact on n-SiC was rapid thermal annealed at 950° C. for 30 s in a N2 ambient. The resultant Ohmic contact is characterized by excellent current-voltage (I-V) characteristics, an abrupt void free contact-SiC interface, retention of the PLD as-deposited contact layer width, smooth surface morphology, and absence of residual carbon within the contact layer or at the interface. The detrimental effects of contact delamination due to stress associated with interfacial voiding; and wire bond failure, non-uniformity of current flow and SiC polytype alteration due to extreme surface roughness; have been eliminated as has electrical instability associated with carbon inclusions at the contact-SiC interface, after prolonged high temperature and power device operation.

Abstract: A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposited upon the semiconductor wafer within the contact hole. A planarizing step isolates the first metal layer within the insulation layer in the form of a contact plug within the contact hole. A second metal layer is then deposited upon the semiconductor wafer over and upon the contact plug. Metallization lines are patterned and etched from the second metal layer. The contact hole may also be lined with a refractory metal nitride layer, with a refractory metal silicide interface being formed at the bottom of the contact hole as an interface between the contact plug and a silicon layer on the semiconductor substrate.

Abstract: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.

Abstract: A method of manufacturing a wiring substrate of the present invention, includes a step of preparing a substrate containing a semi-cured resin layer or a thermo plastic resin layer, a step of forming a through hole that passes through the substrate, a step of inserting a conductive parts in the through hole, a step of curing the semi-resin layer or the thermo plastic resin layer in a state that the resin layer is made to flow by applying a thermal press to the substrate and filling a clearance between the through hole and the conductive parts with the resin layer, and a step of forming a wiring pattern, which is connected mutually via the conductive parts, on both surface sides of the substrate.

Abstract: There is provided a fabrication method for interconnections, capable of embedding a Cu-alloy in recesses in an insulating film, and forming a barrier layer on an interface between the an insulating film and Cu-interconnections, without causing a rise in electric resistivity of the interconnections when fabricating semiconductor interconnections of the Cu-alloy embedded in the recesses provided in the insulating film on a semiconductor substrate. The fabrication method for the interconnections may comprise the steps of forming the respective recesses having a minimum width not more than 0.15 ?m, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1, forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective recesses, and subsequently, annealing the Cu-alloy film to not lower than 200° C.

Abstract: A ruthenium (Ru) film is formed on a substrate as part of a two-stage methodology. During the first stage, the Ru film is formed on the substrate in a manner in which the Ru nucleation rate is greater than the Ru growth rate. During the second stage, the Ru film is formed on the substrate in a manner in which the Ru growth rate is greater than the Ru nucleation rate.

Abstract: Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implanted in the polysilicon layer of the n-MOS transistor region using the photoresist pattern as a mask, and the photoresist pattern is removed. If the polysilicon layer of the n-MOS transistor region is damaged by the implanting of the impurity, the polysilicon layer of the n-MOS transistor region is annealed, and a p-MOS transistor gate and an n-MOS transistor gate are formed by patterning the polysilicon layer. The semiconductor substrate, the p-MOS transistor gate and the n-MOS transistor gate is cleaned with a hydrofluoric acid (HF) solution, without causing a decrease in height of the n-MOS transistor gate.

Abstract: In a semiconductor device, a relatively deep germanium implant and activation thereof precedes deposition of the nickel for nickel silicide formation. The activation of the germanium causes the lattice constant in the region of the implant to be increased over the lattice constant of the background substrate, which is preferably silicon. The effect is that the lattice so altered avoids formation of nickel disilicide. The result is that the nickel silicide spiking is avoided.

Abstract: An apparatus for manufacturing a semiconductor device is disclosed which comprises a chamber which holds a to-be-processed substrate having a film containing at least one kind of metal element which will become a component of a volatile metal compound, a heater which heats the substrate held in the chamber, and an adsorbent which is provided in the chamber and which adsorbs the volatile metal compound generated from the film by heating the substrate.

Abstract: For improving the reliability of a semiconductor device having a stacked structure of a polycrystalline silicon film and a tungsten silicide film, the device is manufactured by forming a polycrystalline silicon film, a tungsten silicide film and an insulating film successively over a gate insulating film disposed over the main surface of a semiconductor substrate, and patterning them to form a gate electrode having a stacked structure consisting of the polycrystalline silicon film and tungsten silicide film. The polycrystalline silicon film has two regions, one region formed by an impurity-doped polycrystalline silicon and the other one formed by non-doped polycrystalline silicon. The tungsten silicide film is deposited so that the resistivity of it upon film formation would exceed 1000 ??cm.

Abstract: The present invention provides a Cu line and method of forming the same, by which reliability (e.g., EM, BTS and the like) can be enhanced by replacing SiN by HfOx, which plays a role as a protective layer and/or an etch stop layer on a Cu line, prevents or inhibits galvanic corrosion due to Cu oxide, and inhibits or reduces additional formation of Cu oxide by gathering or scavenging oxygen atoms from —OH, O2, and H2O. The present method includes the steps of forming a trench in an insulating layer on a substrate, forming a planarized Cu layer in the trench, forming a HfOx layer on the planarized Cu layer, and thermally treating the substrate.

Abstract: In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon from the plug from diffusing into the capacitor's dielectric. The interface can also include an oxygen barrier to prevent the poly plug from oxidizing during processing. Below the interface is a silicide layer to help enhance electrical contact with the poly plug. In a preferred method, the interface is created by selectively depositing a layer of titanium over a recessed poly plug to the exclusion of the surrounding oxide. The deposition process allows for silicidation of the titanium. The top half of the titanium silicide is then nitridized. A conformal ruthenium or ruthenium oxide layer is subsequently deposited, covering the titanium nitride and lining the sides and bottom of the container cell.

Abstract: A conductive layer is formed in or on a substrate. A first metal film is then formed on the substrate including the conductive layer. The substrate is then subjected to heat treatment to allow the first metal film to react with the conductive layer to thereby form a silicide film selectively on the conductive layer. A second metal film is then formed only on the silicide film by selective CVD. An insulating film is then formed over the substrate including the second metal film. A predetermined region of the insulating film is removed to form a contact hole reaching the second metal film. The inside of the contact hole is cleaned to remove a degenerated layer formed on the surface of the second metal film existing on the bottom of the contact hole.