Abstract: A memristive device having a bimetallic electrode includes a memristive matrix, a first electrode and a second electrode. The first electrode is in electrical contact with the memristive matrix and the second electrode is in electrical contact with the memristive matrix and an underlying layer. At least one of the first and second electrodes is a bimetallic electrode which includes a conducting layer and a metallic layer.

Abstract: After a groove is formed in an insulating layer formed on a semiconductor substrate, a barrier metal layer is formed on the insulating layer by an ALD process so as to cover the side walls and bottom of the groove, and an impurity layer is formed in or on the surface of the barrier metal layer by an ion implantation process or by an ALD process. Thereafter, the barrier metal layer and the impurity layer are alloyed, and then an inlaid interconnect layer, which is composed of a Cu seed layer and a Cu plating layer, is formed in the groove. Then, an impurity element in the alloyed barrier metal layer is thermally diffused into the inlaid interconnect layer.

Abstract: A method for fabricating a semiconductor device according to the present invention includes: a step for forming a wiring layer on a semiconductor substrate; a step for patterning the wiring layer; and a step for covering the wiring layer with a protective insulating film. Moreover, after the step for forming the wiring layer, all required heat treatment steps to be performed prior to the step for covering the wiring layer with the protective insulating film are performed at a temperature lower than a temperature for plastic deformation of the wiring layer.

Abstract: A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The second die (50) has a second contact extension (68) connected to the first contact extension and has a containing feature (62) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.

Abstract: The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide the semiconductor device. The method for the fabrication of a silicon carbide semiconductor device includes the steps of performing thermal oxidation on the (000-1) plane of a silicon carbide semiconductor in a gas containing at least oxygen and moisture, thereby forming an insulating film in such a manner as to contact the (000-1) plane of the silicon carbide semiconductor, removing part of the insulating film, thereby forming an opening part therein, depositing contact metal on at least part of the opening part, and performing a heat treatment, thereby forming a reaction layer of the contact metal and silicon carbide, wherein the heat treatment is implemented in a mixed gas of an inert gas and hydrogen.

Abstract: A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the boron-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.

Abstract: The present invention discloses an anodically bonded vacuum cell structure with a glass substrate including a cavity, and a substrate deposited on the glass substrate, thereby enclosing the cavity to form a bonding interface. The bonding interface having silicon such that the substrate includes a layer of silicon or a secondary substrate with silicon layer bonded onto the secondary substrate.

Abstract: An aspect of the present invention, there is provided a method for providing a coating-type film, including, coating a solution including an organic metal compound on a surface of a substrate including a semiconductor substrate to form a coating film, heating the coating film to volatize a solvent in the coating film, and performing a treatment including at least one of a heat treatment, an ozone treatment and a moisture treatment to remove impurities from the coating film.

Abstract: A device comprises a multi-layered thin film having excellent adhesion due to the method of fabricating the same. More particularly, the device includes a multi-layered thin film consisting of a tantalum nitride layer, a tantalum layer formed on the tantalum nitride layer, and a gold thin film formed on the tantalum layer.

Abstract: A nitride-based semiconductor crystal and a second substrate are bonded together. In this state, impact is applied externally to separate the low-dislocation density region of the nitride-based semiconductor crystal along the hydrogen ion-implanted layer, thereby transferring (peeling off) the surface layer part of the low-dislocation density region onto the second substrate. At this time, the lower layer part of the low-dislocation density region stays on the first substrate without being transferred onto the second substrate. The second substrate onto which the surface layer part of the low-dislocation density region has been transferred is defined as a semiconductor substrate available by the manufacturing method of the present invention, and the first substrate on which the lower layer part of the low-dislocation density region stays is reused as a substrate for epitaxial growth.

Abstract: A method of forming an electronic device can include forming a metallic layer by an electrochemical process over a side of a substrate that includes a semiconductor material. The method can also include introducing a separation-enhancing species into the substrate at a distance from the side, and separating a semiconductor layer and the metallic layer from the substrate, wherein the semiconductor layer is a portion of the substrate. In a particular embodiment, the separation-enhancing species can be incorporated into a metallic layer and moved into the substrate, and in particular embodiment, the separation-enhancing species can be implanted into the substrate. In still another embodiment, both the techniques can be used. In a further embodiment, a dual-sided process can be performed.

Abstract: A method for forming a wiring structure includes forming a metal layer on a substrate, and annealing the metal layer by irradiating the metal layer with light emitted from at least one flash tube, thereby growing crystalline grains of the metal layer.

Abstract: Provided is a light emitting device and a method of manufacturing the same. The light emitting device comprises a transparent substrate, an n-type compound semiconductor layer formed on the transparent substrate, an active layer, a p-type compound semiconductor layer, and a p-type electrode sequentially formed on a first region of the n-type compound semiconductor layer, and an n-type electrode formed on a second region separated from the first region of the n-type compound semiconductor layer, wherein the p-type electrode comprises first and second electrodes, each electrode having different resistance and reflectance.

Abstract: An image sensor and a method for manufacturing the same are provided. The image sensor can comprise a substrate, a metal pad, and a sulfur layer. The substrate can include a pixel region and a pad region. The metal pad can be formed of a material containing sulfur and can be disposed in the pad region of the substrate. The sulfur layer can be formed from the sulfur of the metal pad and provided on a top surface of the metal pad.

Abstract: By introducing an additional heat treatment prior to and/or after contacting a sensitive dielectric material with wet chemical agents, such as an electrolyte solution, enhanced performance with respect to leakage currents or dielectric strength may be accomplished during the fabrication of advanced semiconductor devices. For example, metal cap layers for metal lines may be provided on the basis of electroless deposition techniques, wherein the additional heat treatment(s) may provide the required electrical performance.

Abstract: A semiconductor device according to the present invention includes: a silicon carbide substrate (11) that has a principal surface and a back surface; a semiconductor layer (12), which has been formed on the principal surface of the silicon carbide substrate; and a back surface ohmic electrode layer (1d), which has been formed on the back surface of the silicon carbide substrate. The back surface ohmic electrode layer (1d) includes: a reaction layer (1da), which is located closer to the back surface of the silicon carbide substrate and which includes titanium, silicon and carbon; and a titanium nitride layer (1db), which is located more distant from the back surface of the silicon carbide substrate.

Abstract: The invention relates to a method for producing electronic components in a vacuum. The aim of the invention is to create flexible electronic components that have an optimum action, are cost-effective, and easy to produce in a single working cycle. To this end, a carrier film (12) is partially and/or selectively compressed with a blocking liquid, and is subjected to cathodic sputtering. A metallic layer is deposited on the carrier film (12) in the region free of the blocking layer, and the blocking liquid is evaporated during the evaporation process. A semiconductor agent is applied to the coated carrier film (12) during another evaporation process, and a coating with acrylate is then carried out. The carrier liquid is then partially and/or selectively reapplied to the acrylate layer and a cathodic sputtering is carried out. The cited coating processes are optionally repeated, and connections can be established between the individual metallized layers.

Abstract: A semiconductor device and manufacturing method. One embodiment provides at least two semiconductor chips. A dielectric material is applied to the at least two semiconductor chips to attach the at least two semiconductor chips to each other. A portion of the dielectric material is selectively removed between the at least two semiconductor chips to form at least one recess in the dielectric material. Metal particles including paste is applied to the at least one recess in the dielectric material.

Abstract: Embodiments of the present invention provide a method that cools a substrate to a temperature below 10° C. and then implants ions into the substrate while the temperature of the substrate is below 10° C. The implanting causes damage to a first depth of the substrate to create an amorphized region in the substrate. The method forms a layer of metal on the substrate and heats the substrate until the metal reacts with the substrate and forms a silicide region within the amorphized region of the substrate. The depth of the silicide region is at least as deep as the first depth.

Abstract: Ag electrode paste for forming a light-reception-surface-side electrode, with which a solar battery cell having a light-reception-surface-side electrode low in line resistance and achieving high conversion efficiency can be obtained, a solar battery cell having good characteristics manufactured therewith, and a method of manufacturing the same are provided. A silver electrode paste contains (a) Ag particles, (b) an organic vehicle, and (c) lead-free glass fit containing 13 to 17 weight % SiO2, 0 to 6 weight % B2O3, 65 to 75 weight % Bi2O3, 5 weight % Al2O3, 1 to 3 weight % TiO2, and 0.5 to 2 weight % CuO is employed as a Ag electrode paste used for forming a light-reception-surface-side electrode. A Ag electrode paste is used for forming a second electrode of the light-reception-surface-side electrode which includes a first electrode and the second electrode disposed on the first electrode.

Abstract: Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.

Abstract: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.

Abstract: Carbon nanotube apparatus, and methods of carbon nanotube modification, include carbon nanotubes having locally modified properties with the positioning of the modifications being controlled. More specifically, the positioning of nanotubes on a substrate with a deposited substance, and partially vaporizing part of the deposited substance etches the nanotubes. The modifications of the carbon nanotubes determine the electrical properties of the apparatus and applications such as a transistor or Shockley diode. Other applications of the above mentioned apparatus include a nanolaboratory that assists in study of merged quantum states between nanosystems and a macroscopic host system.

Abstract: A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.

Abstract: Methods for patterning a conductor through oxidation are provided. Devices fabricated using the method include organic transistors having a gate electrode and dielectric layer patterned by the method, source and drain electrodes, and an organic semiconducting layer.

Abstract: Methods of forming low resistivity tungsten films with good uniformity and good adhesion to the underlying layer are provided. The methods involve forming a tungsten nucleation layer using a pulsed nucleation layer process at low temperature and then treating the deposited nucleation layer prior to depositing the bulk tungsten fill. The treatment operation lowers resistivity of the deposited tungsten film. In certain embodiments, the depositing the nucleation layer involves a boron-based chemistry in the absence of hydrogen. Also in certain embodiments, the treatment operations involve exposing the nucleation layer to alternating cycles of a reducing agent and a tungsten-containing precursor. The methods are useful for depositing films in high aspect ratio and/or narrow features. The films exhibit low resistivity at narrow line widths and excellent step coverage.

Abstract: The present invention discloses a semiconductor device and a manufacturing method thereof which improves its characteristics even though it is miniaturized. According to one aspect of the present invention, it is provided a semiconductor device comprising a first semiconductor element device including a pair of first diffusion layers formed in the semiconductor substrate with a first gate electrode therebetween, and a first conductor layer formed in the first diffusion layer and having an internal stress in a first direction, and a second semiconductor element device including a pair of second diffusion layers formed in the semiconductor substrate with a second gate electrode therebetween, and a second conductor layer formed in the second diffusion layer, having an internal stress in a second direction opposite to the first direction, and constituted of the same element as that of the first conductor layer.

Abstract: Embodiments of the present invention provide methods of forming and densifying a titanium nitride barrier layer. The densification process is performed at a relatively low RF plasma power and high nitrogen to hydrogen ratio so as to provide a substantially titanium rich titanium nitride barrier layer. In one embodiment, a method for forming a titanium nitride barrier layer on a substrate includes depositing a titanium nitride layer on the substrate by a metal-organic chemical vapor deposition process, and performing a plasma treatment process on the deposited titanium nitride layer, wherein the plasma treatment process operates to densify the deposited titanium nitride layer, resulting in a densified titanium nitride layer, wherein the plasma treatment process further comprises supplying a plasma gas mixture containing a nitrogen gas to hydrogen gas ratio between about 20:1 and about 3:1, and applying less than about 500 Watts RF power to the plasma gas mixture.

Abstract: A method for forming a super contact in a semiconductor device is disclosed. The method enables forming a barrier film selectively on the silicon substrate, leaving the metal contact exposed for perfect isolation of the metal pad from the silicon substrate after formation of the super contact.

Abstract: On a surface of an object to be treated, a Mn-containing thin film or CuMn-containing alloy thin film is formed by heat treatment (CVD or ALD) by using a Mn-containing source gas (or Mn-containing source gas and a Cu-containing gas) and an oxygen-containing gas (for instance, water vapor) as a processing gas. The Mn-containing thin film or the CuMn-containing alloy thin film can be formed with high step coverage in a fine recess formed on the surface of the object to be treated.

Abstract: A method of manufacturing a semiconductor device includes a process of forming a gate electrode having a metallic silicide layer on a semiconductor substrate, a process of decreasing boundaries of grains on the surface of the metallic silicide layer, at least a portion of which is exposed, and a process of forming spacers comprising an oxide film on the side wall of the gate electrode; in this order. Thus, abnormal oxidation of the metallic silicide layer is avoided.

Abstract: A method and device for thermal conduction is provided. A thermal interface device and method of formation is described that includes advantages such as improved interfacial strength, and improved interfacial contact. Embodiments of thermal conduction structures are shown that provide composite thermal conduction and circulated liquid cooling. Embodiments are further shown that require simple, low numbers of manufacturing steps and reduced thermal interface thickness.

Abstract: Methods, devices, and compositions of matter related to high efficiency InGaN-based photovoltaic devices. The disclosed synthesis of semiconductor heterostructures may be exploited to produce higher efficiency, longer lasting, photovoltaic cells.

Abstract: Method and apparatus are provided for treatment of a deposited material layer. In one embodiment, a method is provided for processing a substrate including depositing a metal-containing layer using an atomic layer deposition technique, exposing the metal-containing layer to a plasma treatment process at a temperature of less than about 200° C., and exposing the metal-containing layer to a thermal anneal process at a temperature of about 600° C. or greater. The plasma treatment process and/or the thermal anneal process may use a nitrating gas, which may form a passivating surface or layer with the metal-containing layer.

Abstract: An interlayer insulating film having a concave portion is formed on a semiconductor substrate. A tight adhesion film is formed on the inner surface of the concave portion and the upper surface of the insulating film. The surface of the adhesion layer is covered with an auxiliary film made of Cu alloy containing a first metal element. A conductive member containing a second metal element other than the first metal element is embedded in the concave portion, and deposited on the auxiliary film. Heat treatment is performed to make atoms of the first metal element in the auxiliary film segregate on the inner surface of the concave portion. The adhesion layer contains an element for enhancing tight adhesion of the auxiliary film more than if the auxiliary film is deposited directly on a surface of the interlayer insulating film.

Abstract: A nitride semiconductor device according to the present invention includes a P-type contact layer and a P-type electrode provided on the P-type contact layer. The P-type electrode includes a AuGa film provided on the P-type contact layer, a Au film provided on the AuGa film, a Pt film 4 provided on the Au film, and a Au film provided on the Pt film. The ratio of the thickness of the AuGa film to the total thickness of the AuGa film and the Au film is not less than 12% but not more than 46%.

Abstract: A method and apparatus for processing a thin metal layer on a substrate to control the grain size, grain shape, and grain boundary location and orientation in the metal layer by irradiating the metal layer with a first excimer laser pulse having an intensity pattern defined by a mask to have shadow regions and beamlets. Each region of the metal layer overlapped by a beamlet is melted throughout its entire thickness, and each region of the metal layer overlapped by a shadow region remains at least partially unmelted. After completion of resolidification of the melted regions following irradiation by the first excimer laser pulse, the metal layer is irradiated by a second excimer laser pulse having a shifted intensity pattern so that the shadow regions overlap regions of the metal layer having fewer and larger grains.

Abstract: An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.

Abstract: Disclosed is an apparatus and a method for reducing flash in an injection mold (532 or 542,543) which molds a molded article between a first mold surface and a second mold surface. The apparatus includes an active material actuator (530 or 533a and 533b or 561a and 561b) configured to, in response to application or removal of an electrical actuation signal thereto, change dimension and urge the first mold surface relative to the second mold surface to reduce flash therebetween. The apparatus also includes a transmission structure (533) configured to provide in use, the electrical actuation signal to said active material actuator (530 or 533a and 533b or 561a and 561b) includes a set of active material actuators stacked one against the other to provide a varying sealing force to urge the first mold surface relative to the second mold surface.

Abstract: A non-volatile semiconductor storage device has a memory string including a plurality of electrically rewritable memory cells connected in series. The non-volatile semiconductor storage device also has a protruding layer formed to protrude upward with respect to a substrate. The memory string includes: a plurality of first conductive layers laminated on the substrate; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges. Each of the plurality of first conductive layers includes: a bottom portion extending in parallel to the substrate; and a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion. The protruding layer has a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction.

Abstract: Methods for forming copper interconnects for semiconductor devices are provided. In an exemplary embodiment, a method for forming a copper interconnect comprises depositing copper into a trench formed in a dielectric material overlying a semiconductor material. A force is applied to the semiconductor material and stress is induced within the copper deposited in the trench. Recrystallization and grain growth are effected within the copper and the stress is removed.

Abstract: There are provided an ohmic electrode, which includes a contact layer made of an Al alloy and formed on a nitride-based semiconductor layer functioning as a light emitting layer, a reflective layer made of Ag metal, formed on the contact layer and having some particles in-diffused to the semiconductor layer, and a protective layer formed on the reflective layer to restrain out-diffusion of the reflective layer; a method of forming the ohmic electrode; and a semiconductor light emitting element having the ohmic electrode. The present invention has strong adhesive strength and low contact resistance since the reflective layer and the light emitting layer directly form an ohmic contact due to the interface reaction during heat treatment, and the present invention has high light reflectance and excellent thermal stability since the contact layer and the protective layer restrain out-diffusion of the reflective layer during heat treatment.

Abstract: A dielectric film is formed by depositing an amorphous strontium oxide film to a thickness of one to several atomic layers on a first electrode layer, then depositing an amorphous titanium oxide film to a thickness of one to several atomic layers on the amorphous strontium oxide film, and then heat-treating a laminated film of the amorphous strontium oxide film and the amorphous titanium oxide film at a temperature close to a crystallization start temperature, thereby converting the laminated film to a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein. The laminated film may have a plurality of amorphous strontium oxide films and a plurality of amorphous titanium oxide films that are alternately laminated. A semiconductor device includes a capacitor having as its dielectric film a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein.

Abstract: A semiconductor component, especially a solar cell comprises a semiconductor substrate of a planar design having a first side and a second side lying opposite thereto, at least one contact structure arranged on at least one side of the semiconductor substrate, the at least one contact structure exhibiting a diffusion barrier to prevent the diffusion of ions from the contact structure into the semiconductor substrate.

Abstract: A method comprises forming a gate stack comprising a polysilicon layer, a metal layer and a polysilicon layer over a gate dielectric and substrate. The metal layer is buried inside the gate stack to alloy the silicon and metal at the bottom of the gate. The gate stack is then etched to form a gate. A silicidation is then performed to form a silicide at the bottom of the gate. Optionally, a second metal layer may be formed on top of the gate stack. As such, during silicidation, a silicide may be formed at the top of the gate.

Abstract: A method of forming a semiconductor device that includes heating a wafer on which an Al—Cu sputtering thin film is formed before patterning the Al—Cu sputtering thin film. The heating is performed at a temperature no less than a solid solution temperature of copper or at a temperature between 300° C. and 600° C. The process temperature in heating the process wafer is not higher than the flow temperature of aluminum or is the temperature at which a reflow process can be performed.

Abstract: A method for producing at least one porous layer on a substrate, whereby a suspension, which contains particles from a layer-forming material or molecular precursors of the layer-forming material, as well as at least one organic component, is applied to the substrate, the precursors of the layer-forming material are subsequently reacted to produce the layer-forming material following application to the substrate, in a next step, the particles from the layer-forming material are sintered, and the at least one organic component is subsequently removed. Also, a field-effect transistor having at least one gate electrode, the gate electrode having an electrically conductive, porous coating which was applied in accordance with the method.

Abstract: A substrate on which a pattern is formed by a discharged functional liquid, includes a coating region coated with the functional liquid, and banks formed to enclose the coating region, wherein a difference between a contact angle of the functional liquid with respect to the coating region and a contact angle of the functional liquid with respect to the bank is above 40°.

Abstract: A method for forming a metal interconnection in an image sensor includes forming a first interlayer dielectric (ILD) layer having a contact plug over a substrate, forming a diffusion barrier layer over the first ILD layer, performing a forming gas annealing, forming a second ILD layer over the diffusion barrier layer, etching the second ILD layer and the diffusion barrier layer to form a trench, forming a conductive layer to fill the trench, and planarizing the conductive layer to form a metal interconnection electrically connected to the contact plug.

Abstract: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, a grain growth promotion layer, which promotes the formation of a conductive region within the interconnect structure that has a bamboo microstructure and an average grain size of larger than 0.05 microns is utilized. The inventive structure has improved performance and reliability.