Abstract: Methods for forming copper interconnects for semiconductor devices are provided. In an exemplary embodiment, a method for forming a copper interconnect comprises depositing copper into a trench formed in a dielectric material overlying a semiconductor material. A force is applied to the semiconductor material and stress is induced within the copper deposited in the trench. Recrystallization and grain growth are effected within the copper and the stress is removed.

Abstract: The invention relates to a method of fabricating a CMOS device, comprising providing a semiconductor substrate (101) having therein a layer of insulating material (102), the method comprising providing a layer (106) of a first material over the insulating layer (102), the thickness of the layer (106) of the first material being less in a first region (103) for supporting a first active device than in a second region (104) for supporting a second active device. A layer (107) of a second material is then deposited over the layer (106) of a first material, and the structure is then subjected to a thermal treatment to alloy the first and second materials. The portion of the layers over the first region is entirely alloyed, whereas the portion of the layers over the second region is not, so that a portion (109) of the layer (106) of the first material remains.

Abstract: Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior to the deposition of the second metal layer, the protective layer is exposed to air. This air break step alters the adhesion between the protective cap layer and the second metal layer and thereby, effects the stress imparted upon the first metal layer during silicide formation. The result is a more tensile silicide that is optimal for n-FET performance.

Abstract: A method of fabricating a nitride-based semiconductor device capable of reducing contact resistance between a nitrogen face of a nitride-based semiconductor substrate or the like and an electrode is provided. This method of fabricating a nitride-based semiconductor device comprises steps of etching the back surface of a first semiconductor layer consisting of either an n-type nitride-based semiconductor layer or a nitride-based semiconductor substrate having a wurtzite structure and thereafter forming an n-side electrode on the etched back surface of the first semiconductor layer.

Abstract: A method of forming an interconnect structure of an integrated circuit includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; and forming a copper alloy seed layer in the opening. The copper alloy seed layer physically contacts the dielectric layer. The copper alloy seed layer includes copper and an alloying material. The method further includes filling a metallic material in the opening and over the copper alloy seed layer; performing a planarization to remove excess metallic material over the dielectric layer; and performing a thermal anneal to cause the alloying material in the copper alloy seed layer to be segregated from copper.

Abstract: Provided are a silica nanowire that includes silicon nanodots and a method of preparing the same. The silica nanowire has excellent capacitance characteristics and improved light absorption ability, and thus can be effectively used in a variety of fields, such as various semiconductor devices including CTF memory, image sensors, photodetectors, light emitting diodes, laser diodes, and the like.

Abstract: By introducing an additional heat treatment prior to and/or after contacting a sensitive dielectric material with wet chemical agents, such as an electrolyte solution, enhanced performance with respect to leakage currents or dielectric strength may be accomplished during the fabrication of advanced semiconductor devices. For example, metal cap layers for metal lines may be provided on the basis of electroless deposition techniques, wherein the additional heat treatment(s) may provide the required electrical performance.

Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.

Abstract: A first electrode film containing TiAlN and a main dielectric film containing tantalum oxide are formed over a semiconductor substrate. Anneal is performed in the state that the first electrode film and the main dielectric film are formed, to react aluminum (Al) in the first electrode film with oxygen (O) in the main dielectric film and form a subsidiary dielectric film containing aluminum oxide at an interface between the first electrode film and the main dielectric film. A second electrode film is formed facing the first electrode film via the main dielectric film and the subsidiary dielectric film.

Abstract: The invention relates to glass compositions useful in conductive pastes for silicon semiconductor devices and photovoltaic cells. The thick film conductor compositions include one or more electrically functional powders and one or more glass frits dispersed in an organic medium. The thick film compositions may also include one or more additive(s). Exemplary additives may include metals, metal oxides or any compounds that can generate these metal oxides during firing.

Abstract: The invention relates to glass compositions useful in conductive pastes for silicon semiconductor devices and photovoltaic cells. The thick film conductor compositions include one or more electrically functional powders and one or more glass frits dispersed in an organic medium. The thick film compositions may also include one or more additive(s). Exemplary additives may include metals, metal oxides or any compounds that can generate these metal oxides during firing.

Abstract: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a lower wire, an interlayer insulating film formed on the lower wire and having a via hole exposing the upper surface of the lower wire, a diffusion barrier formed on the inner wall of the via hole, and an upper wire filling the via hole and directly contacting the lower wire, in which a dopant region containing a component of the diffusion barrier is formed in the lower wire in the extension direction of the via hole.

Abstract: Embodiments of the invention relate to a silicon semiconductor device, and a conductive paste for use in the front side of a solar cell device.

Abstract: A core substrate and multilayer printed circuit board using paste bumps and manufacturing method thereof are disclosed. With the method of manufacturing a core substrate using paste bumps comprising: (a) aligning a pair of paste bump boards, each of which has a plurality of paste bumps joined to its surface, such that the paste bumps face each other, and (b) pressing the pair of paste bump boards together, where an insulation element is placed between the pair of paste bump boards, it is easier to implement interlayer electrical interconnection between circuit patterns, the thickness of the core substrate can readily be adjusted by adjusting the thickness of the insulation layer, the stiffness is improved as a pair of paste bump boards are pressed from the top and bottom, and high-density wiring can be formed more easily as the paste bumps are connected in pairs so that the diameters of the paste bumps formed on the paste bump boards can be reduced.

Abstract: Resilient spring contact structures are manufactured by plating the contact structures on a reusable mandrel, as opposed to forming the contact structures on sacrificial layers that are later etched away. In one embodiment, the mandrel includes a form or mold area that is inserted through a plated through hole in a substrate. Plating is then performed to create the spring contact on the mold area of the mandrel as well as to attach the spring contact to the substrate. In a second embodiment, the mandrel includes a form that is initially plated to form the resilient contact structure and then attached to a region of a substrate without being inserted through the substrate. Attachment in the second embodiment can be achieved during the plating process used to form the spring contact, or by using a conductive adhesive or solder either before or after releasing the spring contact from the mandrel.

Abstract: The invention relates to a process for producing at least one air gap in a microstructure, which comprises: 1) the supply of a microstructure comprising at least one gap filled with a sacrificial material that decomposes starting from a temperature ?1, this gap being delimited over at least one part of its surface by a non-porous membrane, composed of a material that forms a matrix and of a pore-forming agent that decomposes at a temperature ?2<?1 by at least 20° C. and that is dispersed in this matrix; 2) the treatment of the microstructure at a temperature ??2 but <?1 in order to selectively decompose the pore-forming agent; then 3) the treatment of the microstructure at a temperature ??1 in order to decompose the sacrificial material. Applications: fabrication of air-gap interconnect structures for integrated circuits and of any other microstructure in the microelectronics and microtechnology industries.

Abstract: In a stacking semiconductor device in which a first-layer and a second-layer semiconductor devices are stacked and bonded with a solder, warpage occurs due to a difference in thermal expansion coefficient of constituent members or a difference in elastic modulus of individual members. Therefore, between the first-layer and the second-layer semiconductor devices are provided an external connection terminal of solder and a thermosetting resin, and the stacking semiconductor device is heated at 150 to 180° C., which are the temperatures of preheating for reflow of the solder, for 30 to 90 seconds. Thereby the warpage of the first-layer semiconductor device is reduced and the thermosetting resin is cured completely in this state. Then, the temperature is raised to a reflow temperature of the solder and solder bonding using the external connection terminal is performed. Thereby, the bonding reliability of a solder-bonded portion of the stacking semiconductor device is considerably improved.

Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.

Abstract: A method of manufacturing a semiconductor device comprises: forming a gate insulator on a substrate, the gate insulator including a high-dielectric film in whole or part; forming a first metal film on the gate insulator; forming a second metal film on the first metal film; and forming a reaction film between the gate insulator and the first metal film by letting the high-dielectric film and the first metal film react with each other through a thermal treatment.

Abstract: A solar cell and a method of manufacturing the same are provided. The solar cell includes a semiconductor unit, an electrode, and a passivation layer between the semiconductor unit and the electrode. The passivation layer includes a first layer containing silicon oxide (SiOx), a second layer containing silicon nitride (SiNx), and a third layer containing silicon oxide (SiOx) or silicon oxynitride (SiOxNy).

Abstract: A method for forming a conductive film, includes: applying a dispersion liquid above a substrate, the dispersion liquid including a plurality of conductive fine-particles made of one conductive material selected from the group consisting of copper, nickel, and an alloy that includes copper or nickel as a main component; and forming the conductive film made from the conductive fine-particles, by heating the dispersion liquid that has been applied above the substrate in an atmosphere including formic acid, by baking the conductive fine-particles so that the conductive fine-particles are mutually fusion bonded.

Abstract: A method for manufacturing a semiconductor device includes forming, on a substrate having a recessed portion on a surface, a plating film which is at least buried in the recessed portion and has a higher impurity concentration in an upper portion than in a lower portion, thermally treating the plating film, and removing the thermally treated plating film except for a portion buried in the recessed portion.

Abstract: The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.

Abstract: Methods of forming dense seed layers and structures thereof are provided. Seed layers including a monolayer of molecules having a density of about 0.5 or greater may be manufactured over a metal layer, resulting in a well-defined interface region between the metal layer and a subsequently formed material layer. A seed layer including a monolayer of atoms is formed over the metal layer, the temperature of the workpiece is lowered, and a physisorbed layer is formed over the seed layer, the physisorbed layer including a weakly bound layer of first molecules. A portion of the first molecules in the physisorbed layer are dissociated by irradiating the physisorbed layer with energy, the dissociated atoms of the first molecules being proximate the seed layer. The workpiece is then heated, causing integration of the dissociated atoms of the first molecules of the physisorbed layer into the seed layer and removing the physisorbed layer.

Abstract: In the case of providing an LDD region for a TFT, it is necessary to form separately an insulating film to be a mask or to contrive the shape of a gate electrode layer in order to have the concentration difference in impurities injected in a semiconductor film; therefore, the number of patterning steps has increased as a matter of course and the step has become complicated. A semiconductor device according to one feature of the invention comprises a semiconductor layer including a channel region, a pair of impurity regions, and a pair of low-concentration impurity regions; and a gate electrode layer having a single layer structure or a laminated structure, of which film thickness is not even, which is formed to be in contact with the semiconductor layer by sandwiching a gate insulating film therebetween.

Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a plasma source to provide an increased reactive species density. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation.

Abstract: Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.

Abstract: A method for manufacturing a metal line embedded in a substrate includes forming a trench in the substrate, bringing a stenciling plate having a through hole corresponding to the trench into contact with the substrate with the through hole being aligned to and exposing the trench, applying a fluidic and solidifiable metallic coating material through the through hole and into the trench, separating the stenciling plate from the substrate and solidifying the metallic coating material in the trench.

Abstract: A method for producing a micromechanical and/or nanomechanical device comprising the steps of: partial etching of at least one sacrificial layer arranged between a first layer and a substrate, forming at least one cavity in which is arranged at least one portion of the sacrificial layer in contact with the first layer and/or the substrate, chemical transformation of at least one wall of the first layer and/or the substrate in the cavity, delimiting at least one stop in the first layer and/or the substrate at the level of the portion of the sacrificial layer, elimination of said portion of the sacrificial layer and the chemically transformed wall of the first layer and/or the substrate.

Abstract: A method of manufacturing a semiconductor device is provided, which can reduce the contact resistance of an ohmic electrode to a p-type nitride semiconductor layer and can achieve long-term stable operation. In forming, in an electrode forming step, a p-type ohmic electrode of a metal film by successive lamination of a Pd film which is a first p-type ohmic electrode and a Ta film which is a second p-type ohmic electrode on a p-type GaN contact layer, the metal film is formed to include an oxygen atom. In the presence of an oxygen atom in the metal film, then in a heat-treatment step, the p-type ohmic electrode of the metal film is heat-treated in an atmosphere that contains no oxygen atom-containing gas.

Abstract: Metallization contact structures and methods for forming a multiple-layer electrode structure on a solar cell include depositing a conductive contact layer on a semiconductor substrate and depositing a metal bearing ink onto a portion of the conductive contact layer, wherein the exposed portions of the conductive contact layer are adjacent to the metal bearing ink. The conductive contact layer is patterned by removing the exposed portions of the conductive contact layer from the semiconductor substrate. The metal bearing ink is aligned with one or more openings in a dielectric layer of the semiconductor substrate and with unexposed portions of the conductive contact layer. The unexposed portions of the conductive contact layer are interposed between the metal bearing ink and the dielectric layer of the semiconductor substrate such that the conductive contact layer pattern is aligned with metal bearing ink.

Abstract: Methods of improving the uniformity and adhesion of low resistivity tungsten films are provided. Low resistivity tungsten films are formed by exposing the tungsten nucleation layer to a reducing agent in a series of pulses before depositing the tungsten bulk layer. According to various embodiments, the methods involve reducing agent pulses with different flow rates, different pulse times and different interval times.

Abstract: An integrated circuit includes a conductive line, the conductive line having a conductive layer made of a metal or a first compound including a metal and a capping layer made of a second compound comprising the metal, the capping layer being in contact with the conductive layer, the first compound being different from the second compound.

Abstract: A light emitting device and a method of manufacturing the same are provided. A light emitting device has a structure wherein a substrate, an n-type clad layer, a light emitting layer, a p-type clad layer, an ohmic contact layer, and a reflective layer are successively stacked. The ohmic contact layer is formed by adding an additional element to an indium oxide. According to the light emitting device and the method of manufacturing the same, the characteristics of ohmic contact with a p-type clad layer is improved, thus increasing the efficiency and yield of wire bonding during packaging FCLEDS. Also, it is possible to increase the light emitting efficiency and life span of light emitting devices due to the low contactless resistance and the excellent electric current and voltage characteristic.

Abstract: An electrode on a semiconductor substrate includes a polysilicon layer, a silicon implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon implanted layer, a tungsten nitride layer on the silicon implanted layer, and a tungsten layer on the tungsten nitride layer. The layer between the polysilicon layer and the tungsten nitride layer may be either a tungsten silicon nitride layer or a silicon-germanium layer.

Abstract: A method of manufacturing a wiring substrate having a wiring layer formation step that includes: a first surface processing step in which surface processing is performed on a film formation area of a substrate; a wiring formation step in which a wiring pattern is formed by placing a first liquid material on the film formation area; a second surface processing step in which surface processing is once again performed on the film formation area; and an insulating film formation step in which an insulating film is formed by placing a second liquid material in gaps in the wiring pattern, wherein an affinity between the second liquid material and the film formation area in the insulating film formation step is greater than an affinity between the first liquid material and the film formation area in the wiring formation step.

Abstract: An integrated circuit includes copper lines, wherein the crystal structure of the copper has a greater than 30% <001 > crystal orientation and a less than 20% <111> crystal orientation.

Abstract: A method for fabricating a semiconductor device is described. A substrate is provided having a patterned dielectric layer disposed thereon. A trench is formed in the dielectric layer. The surfaces of the trench are treated with an ammonia-based plasma process. A metal layer is then formed in the trench.

Abstract: A heat treating apparatus includes a heating plate for heating a substrate coated with a coating liquid, a cooling plate for cooling the substrate and a heat pipe provided in the cooling plate, a cooling chamber being moved together with the cooling plate by the drive mechanism and accommodating a cooling liquid for cooling one end side of the heat pipe. The apparatus further includes a circulation passage provided in the heat treating apparatus to circulate the cooling liquid in the cooling chamber, a circulation pump for circulating the cooling liquid in the circulation passage; and a heat radiating member provided on the circulation passage to radiate the heat received by the cooling chamber to the outside of the heat treating apparatus.

Abstract: The present invention provides, in one embodiment, a process for forming a dual work function metal gate semiconductor device (100). The process includes providing a semiconductor substrate (105) having a gate dielectric layer (110) thereon and a metal layer (205) on the gate dielectric layer. A work function of the metal layer is matched to a conduction band or a valence band of the semiconductor substrate. The process also includes forming a conductive barrier layer (210) on a portion (215) of the metal layer and a material layer (305) on the metal layer. The metal layer and the material layer are annealed to form a metal alloy layer (405) to thereby match a work function of the metal alloy layer to another of the conduction band or the valence band of the substrate. Other embodiments of the invention include a dual work function metal gate semiconductor device (900) and an integrated circuit (1000).

Abstract: The present invention is directed to a thick film conductive composition comprising: (a) electrically conductive silver powder; (c) fluorine-containing glass frit; dispersed in (d) organic vehicle and devices made therefrom.

Abstract: Described herein are a silicon semiconductor device and a conductive lead-free silver paste for use in the front side of a solar cell device.

Abstract: Described herein are a silicon semiconductor device and a conductive paste, including a flux material, for use in the front side of a solar cell device.

Abstract: The present disclosure relates to the fields of microchips with microfluidic optical chambers with enhanced Raman surfaces for multiplexed optical spectroscopy. Embodiments of the present invention allow for ultra small sample volume, as well as high detection speed and throughput, as compared to conventional cuvettes or devices used in optical spectroscopy. Particular embodiments relate to scientific and medical research, the diagnosis of diseases such as cancer, cardiovascular disease, diabetes, etc., and specifically to the detection of biomarkers and determination of protein activity with relevant scientific and medical applications.

Abstract: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a lower wire, an interlayer insulating film formed on the lower wire and having a via hole exposing the upper surface of the lower wire, a diffusion barrier formed on the inner wall of the via hole, and an upper wire filling the via hole and directly contacting the lower wire, in which a dopant region containing a component of the diffusion barrier is formed in the lower wire in the extension direction of the via hole.

Abstract: A die bonding portion is metallically bonded by well-conductive Cu metal powders with a maximum particle diameter of about 15 ?m to 200 ?m and adhesive layers of Ag, and minute holes are evenly dispersed in a joint layer. With this structure, the reflow resistance of about 260° C. and reliability under thermal cycle test can be ensured without using lead.

Abstract: A method of manufacturing a high voltage semiconductor device including forming a P-type region implanted with P-type impurities and an N-type region implanted with N-type impurities in a silicon substrate. The method further includes forming a silicon nitride layer pattern and a pad oxide layer pattern to expose a surface of the silicon substrate, forming a trench by etching the exposed silicon substrate using the silicon nitride layer pattern as an etch mask, forming a trench oxide layer pattern in the trench by removing the silicon nitride layer pattern and the pad oxide layer pattern, and simultaneously forming a deep P-well and a deep N-well by driving P-type impurities in the P-type region and N-type impurities in the N-type region into the silicon substrate, while forming a gate oxide layer on a silicon substrate including the trench oxide layer pattern.

Abstract: The manufacturing method of a substrate having a conductive layer has the steps of: forming an inorganic insulating layer over a substrate; forming an organic resin layer with a desired shape over the inorganic insulating layer; forming a low wettability layer with respect to a composition containing conductive particles on a first exposed portion of the inorganic insulating layer; removing the organic resin layer; and coating a second exposed portion of the inorganic insulating layer with a composition containing conductive particles and baking, thereby forming a conductive layer.

Abstract: The present electronic device includes a dielectric body having an opening therein. A tantalum layer is provided in the opening of the dielectric body, the layer having the characteristic of absorbing hydrogen with decrease in temperature, and releasing hydrogen with increase in temperature. A conductive tungsten plug is provided on the layer in the opening.

Abstract: The present invention provides a method for forming a wiring having a minute shape on a large substrate with a small number of steps, and further a wiring substrate formed by the method. Moreover, the present invention provides a semiconductor device in which cost reduction and throughput improvement are possible due to the small number of steps and reduction of materials and which has a semiconductor element with a minute structure, and further a manufacturing method thereof. According to the present invention, a composition including metal particles and organic resin is irradiated with laser light and a part of the metal particles is baked to form a conductive layer typified by a wiring, an electrode or the like over a substrate. Further, a semiconductor device having the baked conductive layer as a wiring or an electrode is formed.