Abstract: The invention provides a manufacturing method of a substrate having a film pattern including an insulating film, a semiconductor film, a conductive film and the like by simple steps, and also a manufacturing method of a semiconductor device which is low in cost with high throughput and yield. According to the invention, after forming a first protective film which has low wettability on a substrate, a material which has high wettability is applied or discharged on an outer edge of a first mask pattern, thereby a film pattern and a substrate having the film pattern are formed.

Abstract: A wiring pattern forming method which is a method of forming a wiring pattern by using a liquid droplet ejection method on a preset area on a substrate, includes: forming a bank on the preset area on the substrate; ejecting a functional liquid including a wiring pattern material on an area surrounded by the bank and drying the functional liquid to form the wiring pattern; and removing part of the bank so as to make a height of the bank and a thickness of the wiring pattern approximately the same.

Abstract: A method of manufacturing a semiconductor structure. One embodiment produces a substrate having at least two semiconductor chips embedded in a molded body. A layer is applied over at least one main surface of the substrate by using a jet printing process.

Abstract: A method of forming a via hole reaching a bonding pad in a wafer having an insulating film constituting a plurality of devices on the front surface of a substrate and bonding pads on each of the devices by applying a pulse laser beam to the rear surface of the substrate, the method comprising the steps of: forming a non-through hole reaching the insulating film formed on the substrate by applying a pulse laser beam to the rear surface of the substrate; forming an insulating film on the inner wall of the hole which is formed in the substrate by the first step; and forming a via hole reaching a bonding pad by applying a pulse laser beam to the hole having the insulating film which is formed on the inner wall by the insulating film forming step.

Abstract: Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.

Abstract: A metal line substrate and a method of fabricating thereof, the metal line substrate including an insulating layer and a capping layer disposed on an insulating substrate, a trench defined by the insulating layer and the capping layer disposed on the insulating substrate, a seed layer pattern disposed on the insulating substrate, and a low-resistive conductive layer pattern disposed in the trench and contacting the seed layer pattern. The capping layer pattern includes a protrusion region which is in contact with the low-resistive conductive layer pattern.

Abstract: A method for forming a pattern according to the invention comprises the steps of: forming a mask over a substrate having light-transmitting properties; forming a first region having a substance including a light-absorbing material over the substrate and the mask; forming a second region by irradiating the substance with light having a wavelength which is absorbable by the light-absorbing material through the substrate to modify a part of the substance surface; and forming a pattern by discharging a compound including a pattern forming material to the second region.

Abstract: A method for forming metal interconnects on a substrate is described. A substrate with a dielectric layer is positioned within a processing chamber. A first barrier layer is deposited on the dielectric layer and within a plurality of vias of the dielectric layer, wherein the first barrier layer includes beveled edges extending from a field of the substrate to a sidewall surface of each via. The first barrier layer and the dielectric layer are etched to form a recess at each beveled edge. A second barrier layer is deposited over the recess. A metal seed layer deposited over the first barrier layer, the second barrier layer, and within the recess.

Abstract: A process for producing a semiconductor device, comprising the wiring region forming step of forming a wiring region on a semiconductor substrate; the copper wiring layer forming step of forming a copper wiring layer on the formed wiring region by electrolytic plating technique, wherein the copper wiring layer is formed by passing a current of application pattern determined from the relationship between application pattern of current passed at electrolytic plating and impurity content characteristic in the formed copper wiring layer so that the impurity content in the formed copper wiring layer becomes desired one; and the wiring forming step of polishing the formed copper wiring layer into a wiring.

Abstract: To provide a semiconductor device and a display device which can be manufactured through a simplified process and the manufacturing technique. Another object is to provide a technique by which a pattern of wirings or the like which is partially constitutes a semiconductor device or a display device can be formed with a desired shape with controllability.

Abstract: A method for the production of a component structure. On embodiment provides a semiconductor body having a first side. A first trench and a second trench are produced, which extend into the semiconductor body proceeding from the first side and are arranged at a distance from one another in a lateral direction of the semiconductor body. A first material layer in the first trench is produced. A third trench proceeding from the second trench is produced, extending as far as the first material layer in the first lateral direction.

Abstract: Methods of inhibiting background plating on semiconductor substrates using oxidizing agents are disclosed.

Abstract: Disclosed herein is a semiconductor device including: an insulating film configured to be provided on a substrate and be porosified through decomposition and removal of a pore-forming material; a covering insulating film configured to be provided on the insulating film; and conductive layer patterns configured to be provided in the covering insulating film and the insulating film and reach the substrate, wherein the insulating film includes a non-porous region in which the pore-forming material remains.

Abstract: An electroless plating system includes a plating solution, and controlling reducing agents in the plating solution for deposition over outlier features smaller than about five hundred nanometers and isolated by about one thousand nanometers.

Abstract: A semiconductor package and a method for manufacturing the same capable of supplying power easily without an increase in the number of pads for power supply. The semiconductor package includes a semiconductor chip having a plurality of pads including pads for power supply disposed in a center portion and an internal wiring disposed to be exposed to outside; an insulating film formed on the semiconductor to expose the pads for power supply and the internal wirings; and re-distribution lines formed on the insulating film to connect between the exposed portions of the pads for power supply and the internal wiring.

Abstract: One embodiment of the present invention is a method for depositing two or more PVD seed layers for electroplating metallic interconnects over a substrate, the substrate including a patterned insulating layer which includes at least one opening surrounded by a field, the at least one opening having top corners, sidewalls, and bottom, the field and the at least one opening being ready for depositing one or more seed layers, and the method includes: (a) depositing by a PVD technique, in a PVD chamber, a continuous PVD seed layer over the sidewalls and bottom of the at least one opening, using a first set of deposition parameters; and (b) depositing by a PVD technique, in a PVD chamber, another PVD seed layer over the substrate, using a second set of deposition parameters, wherein (i) the second set of deposition parameters includes at least one deposition parameter which is different from any of the parameters in the first set of deposition parameters, or the second set of deposition parameters includes at least

Abstract: A display substrate includes a gate wiring, a data wiring, a switching element, an organic layer, and a pixel electrode. The gate wiring contacts a first transparent conductive layer formed on the gate wiring. The data wiring crosses the gate wiring. The data wiring contacts a second transparent conductive layer formed on the data wiring. The switching element is connected to the gate and data wirings. The organic layer is formed on a base substrate having the switching element formed thereon. The organic layer has first and second trenches corresponding to the first and second transparent conductive layers, respectively. The pixel electrode is formed in a pixel area of the organic layer.

Abstract: The nanostructure-based electronic device comprises a solid support, an organic template layer, a nanostructure and electrodes. The organic template layer is on the surface of the solid support, and has a surface comprising a pair of spaced, electrically-charged regions arranged in tandem in an electrically-neutral background. The nanostructure is elongate, is electrically-conducting, and extends between the charged regions. The electrodes are located the surface of the template layer and are at least co-extensive with the charged regions.

Abstract: A mask layer is applied to a surface of a semiconductor structure or a seed layer deposited on the surface. The mask layer has a submicron width opening with a high aspect ratio that exposes a portion of the surface or seed layer. Conductive material is conformed to the opening, for example by plating, to form a first contact on the surface or seed layer. The mask and the top layer of the semiconductor structure, except for the portion under the first contact, are removed to expose a second layer of the semiconductor structure. An insulating layer is formed along the sidewalls of the first contact and the top layer of the semiconductor structure beneath the first contact. A mask is then applied to the second layer and a second contact is formed by selectively depositing metal only on the portion of the second layer exposed by the opening.

Abstract: A substrate 10 for a semiconductor device includes: a base plate 1, a plurality of external terminal portions 12p, 12q, respectively arranged in a plane on the base plate 1 and having external terminal faces 12pb, 12qb respectively facing the base plate 1; a plurality of internal terminal portions 11, respectively arranged in the plane on the base plate 1 and having internal terminal faces 11a respectively facing an opposite side to the base plate 1. The internal terminal portions 11 are connected with the external terminal portions 12p, 12q, via wiring portions 17, respectively. A part of the external terminal portions 12p are located on the base plate 1 in a predetermined arrangement area A in which a semiconductor element 50 is arranged.

Abstract: Manufacturers encounter limitations in forming low resistance ohmic electrical contact to semiconductor material P-type Gallium Nitride (p-GaN), commonly used in photonic applications, such that the contact is highly transparent to the light emission of the device. Carbon nanotubes (CNTs) can address this problem due to their combined metallic and semiconducting characteristics in conjunction with the fact that a fabric of CNTs has high optical transparency. The physical structure of the contact scheme is broken down into three components, a) the GaN, b) an interface material and c) the metallic conductor. The role of the interface material is to make suitable contact to both the GaN and the metal so that the GaN, in turn, will make good electrical contact to the metallic conductor that interfaces the device to external circuitry. A method of fabricating contact to GaN using CNTs and metal while maintaining protection of the GaN surface is provided.

Abstract: An interlayer insulator includes a first interlayer insulator and a second interlayer insulator formed on the first interlayer insulator and having a property of preventing diffusion of copper. A barrier metal film is formed on an inner wall in the wiring trench except an upper end and operative to prevent copper contained in the Cu wiring from diffusing into the interlayer insulator. The Cu wiring is brought into contact with the second interlayer insulator at the upper end and covered with the barrier metal film at a lower portion below the upper end.

Abstract: A method of fabricating a device, comprising a ink or paste on a silicon based semiconductor material, wherein the ink or paste comprises a mixture of inorganic conductive and additive nanoparticles and wherein the semiconductor material is silicon. An example is a mixture of silver and palladium nanoparticles.

Abstract: A method of forming a film pattern by disposing functional liquid on a substrate includes: forming banks on the substrate; disposing the functional liquid in regions partitioned by the banks; and drying the functional liquid disposed on the substrate. The forming of the banks includes forming a thin film on the substrate, the thin film being made of a material for forming the banks, performing lyophobic treatment on a surface of the thin film, and patterning the thin film into the shapes of the banks.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum lanthanide oxynitride film.

Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines indifferent cell array layers.

Abstract: Initially, an interconnection 5w that contains copper is formed on a semiconductor substrate 1 (step (A)). On the interconnection 5w, an etching stopper film 6es is formed (step (B)). On the etching stopper film 6es, an insulating layer 6 is formed (step (C)). In the insulating layer 6, a via hole 6v that reaches the etching stopper film 6es is formed (step (D)). A surface of each of via hole 6v and the insulating layer 6 is cleaned with an organic solvent C (step (E)). The etching stopper film 6es is removed such that the interconnection 5w is exposed (step (F)). An interconnection 6w that electrically connects to the exposed interconnection 5w is further formed (step (G)). It is thereby possible to obtain a method of manufacturing a semiconductor device, including a cleaning step that can suppress corrosion of an interconnection that contains copper.

Abstract: Provided is a method of fabricating a metal pattern so that an insulation layer between a wafer and the metal pattern can be prevented from being damaged in a planarization procedure when the metal pattern having a trench structure is fabricated on the wafer. The method includes operations of forming a first insulation layer on a surface of the wafer; selectively etching the surface of the wafer and the first insulation layer so as to form a plurality of trenches; forming a second insulation layer on a bottom and side walls of the plurality of trenches by using a thermal oxidation method; filling a metal inside the plurality of trenches; and performing planarization by removing the metal deposited outside the plurality of trenches.

Abstract: As a semiconductor device, specifically, a pixel portion included in a semiconductor device is made to have higher precision and higher aperture ratio, it is required to form a smaller wiring in width. In the case of forming a wiring by using an ink-jet method, a dot spreads on a wiring formation surface, and it is difficult to narrow width of a wiring. In the present invention, a photocatalytic substance typified by TiO2 is formed on a wing formation surface, and a wiring is formed by utilizing photocatalytic activity of the photocatalytic substance. According to the present invention, a narrower wiring, that is, a smaller wiring in width than a diameter of a dot formed by an ink-jet method can be formed.

Abstract: The invention relates to a method for producing an electronic circuit, and to an electronic circuit, having at least one organic electrical functional layer and at least one data storage unit, the data storage unit being configured with two electrically conductive layer contacts. The two electrically conductive layer contacts are arranged alongside one another and are electrically conductively connected to one another either by an electrically conductive dry substance or by an electrically conductive solidified substance.

Abstract: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a pad electrode formed on a semiconductor substrate through a first insulation layer, and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein the via hole includes a first opening of which a diameter in a portion close to the pad electrode is larger than a diameter in a portion close to the back surface of the semiconductor substrate, and a second opening formed in the first insulation layer and continuing from the first opening, of which a diameter in a portion close to the pad electrode is smaller than a diameter in a portion close to the front surface of the semiconductor substrate.

Abstract: A method for manufacturing a multi-level transistor on a substrate. The method includes forming a first transistor on a first active region, forming a first selective epitaxial growth (SEG) layer on the substrate, and forming a preliminary second SEG layer and a dummy layer, wherein the preliminary second SEG layer is formed directly on only the first SEG layer and a portion of the first insulating layer formed on the cell region of the substrate, and wherein the dummy layer is formed on the peripheral region of the substrate. The method further includes planarizing the preliminary second SEG layer using the dummy layer as a stop layer to form a second SEG layer, forming a second active region from the second SEG layer formed on a first insulating layer, and forming a second transistor on the second active region.

Abstract: A method for manufacturing a wiring substrate by an electroless plating method that precipitates metal without using a plating resist is provided. The method includes the steps of: (a) providing a catalyst layer having a predetermined pattern on a substrate; (b) dipping the substrate in an electroless plating solution to thereby precipitate metal on the catalyst layer to provide a first metal layer; (c) washing a top surface of the substrate with water; and (d) dipping the substrate in an electroless plating solution to thereby precipitate metal on the first metal layer to provide a second metal layer.

Abstract: A method for making an interconnect is provided. The method includes depositing a conductive layer on a substrate, depositing a protective layer on the conductive layer, patterning the protective layer to form openings to the conductive layer, depositing contact pads on the conductive layer through the openings in the protective layer, the contact pads comprising a conductive material, and patterning the conductive layer and the protective layer to form electrical traces on the substrate.

Abstract: One embodiment of the present invention is a method for fabricating a nanoscale shift register. In a described embodiment, a nanoimprinting-resist layer applied above a silicon-on-insulator substrate is nanoimprinted to form troughs and trough segments. The silicon layer exposed at the bottom of the troughs and trough segments is then etched, and a conductive material is deposited into the troughs to form nanowires and into the trough segments to form nanowire segments. The exposed surfaces of nanowires are coated with a protective coating, and the conductive material of the nanowire segments is then removed to produce trough segments etched through the nanoimprinting resist and the silicon layer.

Abstract: In a wiring manufacturing process which uses conventional photolithography, most of resist and wiring material, or process gas which is necessary at the time of plasma processing, etc. is wasted. Also, since air discharging means such as a vacuum equipment is necessary, an entire apparatus grows in size, and therefore, it has been a problem that production cost increases with growing in size of a processing substrate. In this invention, applied is such means that droplets are used for resist and wiring material, and they are emitted directly to a necessary place on the substrate in a line form or a dot form, to draw a pattern. Also, applied is means which carries out a gas reaction process such as ashing and etching, under atmospheric pressure or the vicinity of atmospheric pressure.

Abstract: A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of optical features spaced on the lithography mask from one another along a first direction, where the individual optical features have first mask feature dimensions along the first direction that are smaller than a desired first dimension for the openings to be patterned in the etch mask.

Abstract: A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is conformally deposited over the contact points, and a second material layer is deposited. A photoresist layer is applied and patterned to leave remaining portions. The remaining portions are trimmed to produce trimmed remaining portions which overlie eventual contact holes to the contact points. Using the trimmed remaining portions as an etch mask, exposed portions the second material layer are etched away to leave sacrificial plugs. The sacrificial plugs are etched away to form contact holes that reach portions the first material layers. Another etching step is performed to extend the contact holes to produce final contact holes that extend to the contact points.

Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).

Abstract: The present invention relates to a method for manufacturing a backside contact of a semiconductor component, in particular, of a solar cell, comprising a metallic layer on the backside of a substrate in a vacuum treatment chamber, and the use of a vacuum treatment system for performing said method. Through this method and its use, in particular silicon based solar cells, can be provided with a back contact in a simple manner in a continuous process sequence, wherein the process sequence can be provided particularly efficient and economical, since no handling systems for rotating the substrate are required, and in particular silk screening steps can be dispensed with.

Abstract: A semiconductor device manufacturing apparatus includes a substrate holding section that holds a semiconductor wafer substrate, a discharge mechanism that discharges liquid drops of metal paste from a discharge nozzle toward a surface of the semiconductor wafer substrate, and a driving mechanism that moves at least one of the substrate holding section and the discharge nozzle. A control section is provided to control the discharge and driving mechanisms so as to adhere the metal paste to the surface. The semiconductor wafer substrate includes a terminal unit formed from two or more electrically separated terminals connected to a device circuit and an insulation layer having an opening in a formation position of the terminal unit. Further, the control section controls the discharge and driving mechanisms to selectively coat the opening of the semiconductor wafer substrate with the metal paste overlying the terminal unit to be electrically connected.

Abstract: A metal film-forming method of the present invention can form a metal film having different film qualities in the thickness direction, in a continuous manner using a single processing solution. The metal film-forming method including: providing a substrate having embedded interconnects formed in interconnect recesses provided in a surface of the substrate; and forming a metal film, having different film qualities in the thickness direction, on surfaces of the interconnects in a continuous manner by changing the flow state of a processing solution relative to the surface of the substrate while keeping the surface of the substrate in contact with the processing solution.

Abstract: A method, structure and system for forming a through-hole conductor in a semiconductor substrate includes forming a hole having an inner surface from a first side of the semiconductor substrate to a second side of the semiconductor substrate and plating the inner surface of the semiconductor substrate to form a conductive element when a plating solution is forced from the first side of the semiconductor substrate to the second side of the semiconductor substrate through the hole. The hole is plated in a generally planar plating topology from the first side to the second side of the semiconductor substrate. The through-hole conductor may be formed in a plating system where the semiconductor substrate forms at least a partial partition between a higher pressure bath and a lower pressure bath with the plating solution passing through the hole causing plating within the inner surface of the hole.

Abstract: A method, structure and system for forming a through-hole conductor in a semiconductor substrate includes forming a hole having an inner surface from a first side of the semiconductor substrate to a second side of the semiconductor substrate and plating the inner surface of the semiconductor substrate to form a conductive element when a plating solution is forced from the first side of the semiconductor substrate to the second side of the semiconductor substrate through the hole. The hole is plated in a generally planar plating topology from the first side to the second side of the semiconductor substrate. The through-hole conductor may be formed in a plating system where the semiconductor substrate forms at least a partial partition between a higher pressure bath and a lower pressure bath with the plating solution passing through the hole causing plating within the inner surface of the hole.

Abstract: A system for processing a substrate is provided which includes at least one atomic layer deposition (ALD) chamber for depositing a barrier layer containing tantalum and at least one physical vapor deposition (PVD) metal seed chamber for depositing a metal seed layer on the barrier layer. The at least one ALD chamber may be in fluid communication with a first precursor source providing a tantalum-containing compound and a second precursor source. In one example, the tantalum-containing compound is an organometallic tantalum precursor, such as PDMAT. In another example, the second precursor source contains a nitrogen precursor, such as ammonia. The PDMAT may have a chlorine concentration of about 100 ppm or less, preferably, about 30 ppm or less, and more preferably, about 5 ppm or less. In some examples, the PVD metal seed chamber is used to deposit a copper-containing metal seed layer.

Abstract: Method for manufacturing a device having a conductive via includes the following steps. A dielectric material layer including a through hole is formed on a substrate. A seed metallic layer is formed on the dielectric material layer and in the through hole. A metallic layer is formed on the seed metallic layer, and is filled in the through hole. The metallic layer located over the seed metallic layer and outside the through hole is etched by a spin etching process, whereby the metallic layer located in the through hole is formed to a lower portion. An upper portion is formed on the lower portion, and a metallic trace is formed on the seed metallic layer, wherein the upper and lower portions is formed to a conductive via, and the conductive via and the metallic trace expose a part of the seed metallic layer. The exposed seed metallic layer is etched.

Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate comprising immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition comprising a source of copper ions, an organic sulfonic acid or inorganic acid, or one or more organic compounds selected from among polarizers and/or depolarizers, and chloride ions.

Abstract: A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

Abstract: A method for fabricating a semiconductor device includes forming a dielectric film on a semiconductor substrate; forming an opening in the dielectric film; forming a refractory metal film in the opening; performing a nitriding process to the refractory metal film; removing a nitride of the refractory metal film formed on a side wall of the opening; and depositing tungsten (W) in the opening from which the nitride is removed.

Abstract: A method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature and at least one insulating layer covering the metal feature and the substrate. At least one recess is formed in the at least one insulating layer thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature. A plating seed layer of a first metal is formed over the at least one barrier layer. A photoresist layer is deposited over the plating seed layer. Portions of the photoresist layer and portions of the plating seed layer outside of the at least one recess are removed. Photoresist remaining in the at least one recess is removed. A second metal is electroplated to the plating seed layer in the recess, using the barrier layer to conduct electrical current.