Abstract: The semiconductor manufacturing method includes the step (ST.1) of preparing a semiconductor substrate with a copper or copper-containing metal film exposed on a surface, step (ST.2) of depositing on the copper or copper-containing metal film a metal film consisting essentially of any one of CoWB, CoWP, or W; step (ST.3) of introducing Si into the above-described metal film, and step (ST.4) of nitriding the metal film introduced with Si.

Abstract: A chemical treatment apparatus and a method for performing a chemical treatment of a wafer, etc., by supplying a chemical via a cell. The apparatus includes a cylindrical inner cell and a cylindrical outer cell with open ends disposed at an outer circumference of the inner cell. The outer cell is axially movable to vary the width of a slit formed between a bottom end of the outer cell and a top surface of the substrate-holding means by the axial movement, thereby adjusting the discharge rate of the chemical and varying the pressure of the chemical.

Abstract: A capacitor assembly includes a semiconductor substrate having an interlayer insulation film on a first main surface of the semiconductor substrate, and a conductive barrier layer formed on the interlayer insulation film. The capacitor assembly also includes a contact plug electrically connected to the conductive barrier layer through the interlayer insulation film, and a lower electrode formed on the barrier layer. The capacitor assembly also includes a capacitor insulation film formed on the lower electrode, and an upper electrode formed on the capacitor insulation film. The capacitor insulation film is made from a ferroelectric material. The barrier layer is an amorphous film which includes titanium and aluminum.

Abstract: Methods of contact formation and memory arrays formed using such methods, which methods include providing a substrate having a contacting area; forming a plurality of line-shape structures extending in a first direction; forming a hard mask spacer beside the line-shape structure; forming an insulating material layer above the hard mask spacer; forming a contiguous trench in the insulating material layer extending in a second direction different from the first direction and exposing the contacting area; and forming a conductive line in the trench to contact the contacting area.

Abstract: Described is a method for forming a stackable interconnect. The interconnect is formed by depositing a first contact on a substrate; depositing a seed layer (SL) on the substrate; depositing a metal mask layer (MML) on the SL; depositing a bottom anti-reflection coating (BARC) on the MML; forming a photoresist layer (PR) on the BARC; removing a portion of the PR; etching the BARC and the MML to expose the SL; plating the exposed SL to form a first plated plug; removing the layers to expose the SL; removing an unplated portion of the SL; depositing an inter layer dielectric (ILD) on the interconnect; etching back the ILD to expose the first plated plug; and depositing a second contact on the first plated plug. Using the procedures described above, a second plated plug is then formed on the first plated plug to form the stackable plugged via interconnect.

Abstract: Embodiments of the invention relate to efficient formation of improved fuses and fuse arrays, such as can be used in memory devices for example, by use of a printer that transfers material to a flexible substrate. In one embodiment, a fuse is printed using an inkjet printer on a flexible substrate fed therethrough, by depositing droplets of conductive material. The droplets form a weak portion and one or more main portions. In one embodiment, the fuse may comprise a single metal material. In additional embodiments, an array of fuses can be printed by an inkjet printer in layers for use as digital memory. For example, a layer can be printed that forms fuse elements and word address conductors, an insulating layer can be printed over the fuses but leaving a window portion exposed, and a third layer can be printed over the window portions to provide bit address conductors.

Abstract: In a method for manufacturing a semiconductor device, either a nickel layer or a nickel-based metal layer is formed on a semiconductor substrate by using a plating process. Then, either the nickel layer or the nickel-based metal layer is washed with one of an aqueous hydrochloric acid solution and an aqueous sulfuric acid solution.

Abstract: A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin; forming a deposition. structure including a self-arrangement contact insulation film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; forming the multi-functional hard mask composition on the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film, thereby forming a trench having a width wider than that of the via hole; and removing the multi-functional hard mask film.

Abstract: A method for controlling catalyst nanoparticle positioning includes establishing a mask layer on a post such that a portion of a vertical surface of the post remains exposed. The method further includes establishing a catalyst nanoparticle material on the mask layer and directly adjacent at least a portion of the exposed portion of the vertical surface.

Abstract: Systems and methods are disclosed for processing a semiconductor substrate by depositing a conductive layer on the substrate; patterning a set of insulating structures on the substrate; selectively back-biasing the substrate; depositing a layer of material on the substrate; and removing a part of the conductive layer selectively biased to attract cation bombardment.

Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g.

Abstract: A device is disclosed with at least one electrically insulating layer on which at least one conductor structure made of electrically conductive material is placed. In at least one embodiment, the conductor structure on the side facing the insulating layer has at least one elevation that is accommodated in at least one recess in the insulating layer.

Abstract: A method for manufacturing an inductance in a monolithic circuit including a substrate of planar upper surface, including the steps of forming in the substrate a cavity substantially following the contour of the inductance to be formed, the cross-section of the cavity being deep with respect to its width; and filling the cavity with a conductive material.

Abstract: Methods are provided for electrochemically depositing copper on a work piece. One method includes the step of depositing overlying the work piece a barrier layer having a surface and subjecting the barrier layer surface to a surface treatment adapted to facilitate deposition of copper on the barrier layer. Copper then is electrochemically deposited overlying the barrier layer.

Abstract: A circuit package includes a substrate having an opening and a single unitary heat sink adapted to effectively dissipate heat is positioned in the opening to expose top and bottom surfaces which are respectively coplanar with top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.

Abstract: Methods of the present invention provide a high-throughput, low cost, patterning platform that is an alternative to conventional photolithography and direct laser ablation patterning techniques. The present processing methods are useful for making patterns of microsized and/or nanosized structures having accurately selected physical dimensions and spatial orientation that comprise active and passive components of a range of microelectronic devices. Processing provided by the present methods is compatible with large area substrates, such as device substrates for semiconductor integrated circuits, displays, and microelectronic device arrays and systems, and is useful for fabrication applications requiring patterning of layered materials, such as patterning thin film layers in thin film electronic devices.

Abstract: Methods are disclosed for depositing materials selectively and controllably from liquid, near-critical, and/or supercritical fluids to a substrate or surface controlling the location and/or thickness of material(s) deposited to the surface or substrate. In one exemplary process, metals are deposited selectively filling feature patterns (e.g., vias) of substrates. The process can be further used to control deposition of materials on sub-surfaces of composite or structured silicon wafers, e.g., for the deposition of barrier films on silicon wafer surfaces. Materials include, but are not limited to, overburden materials, metals, non-metals, layered materials, organics, polymers, and semiconductor materials. The instant invention finds application in such commercial processes as semiconductor chip manufacturing.

Abstract: In the case where a contact hole is formed by a conventional process of the semiconductor device fabrication, a resist is required to be formed almost entirely over a substrate in order to form the resist over the film where the contact hole is not formed. Accordingly, the throughput is considerably low. Further, when the resist spreads to the area of the contact hole when the amount of the resist to be applied and the surface state of the base are not fully controlled, contact defect would occur. Thus, improvements are required. According to the invention, in forming a semiconductor device, a part to be a contact hole of the semiconductor device may be covered with a first organic film that is liquid repellent. Subsequently, a second organic film serving as an insulating film is formed on the area where the first organic film is not formed, and the first organic film is removed thereafter to form a contact hole.

Abstract: In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second metal interconnect are recessed to form recesses. A second insulating film filling the recesses is then formed above a substrate, and the upper portion of the second insulating film is planarized. Next, a hole and a trench are formed to extend halfway through the second insulating film, and ashing and polymer removal are performed. Subsequently to this, the hole and the trench are allowed to reach the first metal interconnect and the second metal interconnect.

Abstract: A method for producing at least one local coating on a substrate is provided, as well as a combinatory substrate having such a local coating, a mask that is removable in a non-destructive manner being arranged on the substrate in a first step; the mask having at least one perforation, the perforation being at least partially filled with a reactive solution in a second step; and a coating reaction of the reactive solution with the substrate surface being induced in a third step to form the local coating.

Abstract: A method, structure and system for forming a through-hole conductor in a semiconductor substrate includes forming a hole having an inner surface from a first side of the semiconductor substrate to a second side of the semiconductor substrate and plating the inner surface of the semiconductor substrate to form a conductive element when a plating solution is forced from the first side of the semiconductor substrate to the second side of the semiconductor substrate through the hole. The hole is plated in a generally planar plating topology from the first side to the second side of the semiconductor substrate. The through-hole conductor may be formed in a plating system where the semiconductor substrate forms at least a partial partition between a higher pressure bath and a lower pressure bath with the plating solution passing through the hole causing plating within the inner surface of the hole.

Abstract: A multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device, and a method for forming the cap.

Abstract: System and method for direct etching. According to an embodiment, the present invention provides a method for manufacturing an integrated circuit device. The method includes a step for providing a substrate having a contact region, which is provided between a first word line and a second word line. The contact region has an overlying plug structure, which is provided within a thickness of a first dielectric layer. The first dielectric layer includes a portion overlying the plug structure. The first dielectric layer has a planarized surface region. The method also includes a step for forming a first line and a second line and a space provided between the first word line and the second world line. The space is provided within a region overlying the plug structure.

Abstract: A method for fabricating a dual damascene structure contains providing a substrate having a conductive layer, an etching stop layer, a dielectric layer, and a photoresist layer thereon, performing an etching process to remove a portion of the dielectric layer through a via pattern of the photoresist layer for forming a via structure in the dielectric layer, providing CO-containing gas to perform an ash process, filling GFP materials into the via structure, forming a photoresist layer with a trench pattern on the substrate, etching the dielectric layer through the trench pattern to form a trench structure in the dielectric layer, above the via structure, and removing the etching stop layer exposed in the via structure.

Abstract: The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.

Abstract: This disclosure describes system(s) and/or method(s) enabling contacts for individual nanometer-scale-thickness layers of a multilayer film.

Abstract: A method of manufacturing an electronic part in which on the upper surface of an insulating member covering lower layer wiring, a conductor portion connected from the lower layer wiring is exposed. In this method, electric power supplying film is formed on the upper surface of the insulating member, whereafter an opening portion having the lower layer wiring as a bottom is formed from the electric power supplying film side. Then metal plating is grown from the edge portion of the electric power supplying film from the opening portion with the electric power supplying film as an electrode, and the opening portion is filled with the metal plating closely contacting with the lower layer wiring to thereby form a conductor portion.

Abstract: A method of forming a predetermined pattern by disposing a functional liquid on a substrate, the method includes the steps of forming banks on the substrate, and disposing the functional liquid on a region divided by the banks, wherein a width of the region is partially formed so as to be large.

Abstract: A method of fabricating a phase-change memory cell is described. The cross-sectional area of a contact with a phase-change memory element within the cell is controlled by a first dimension of a bottom electrode and a second dimension controlled by an etch process. The contact area is a product of the first dimension and the second dimension. The method allows the formation of very small phase-change memory cells.

Abstract: The present invention provides a method for manufacturing a wiring and a method for manufacturing a semiconductor device, which do not require a photolithography step in connecting a pattern of an upper layer and a pattern of a lower layer. According to the present invention, a composition including a conductive material is discharged locally and an electric conductor to function as a pillar is formed on a first pattern over a substrate, an insulator is formed to cover the electric conductor, the insulator is etched to expose a top surface of the electric conductor, and a second pattern is formed on the top surface of electric conductor that is exposed.

Abstract: A method and apparatus is disclosed for sequential processing of integrated circuits, particularly for conductively passivating a contact pad with a material which resists formation of resistive oxides. In particular, a tank is divided into three compartments, each holding a different solution: a lower compartment and two upper compartments divided by a barrier, which extends across and partway down the tank. The solutions have different densities and therefore separate into different layers. In the illustrated embodiment, integrated circuits with patterned contact pads are passed through one of the upper compartments, in which oxide is removed from the contact pads. Continuing downward into the lower compartment and laterally beneath the barrier, a protective layer is selectively formed on the insulating layer surrounding the contact pads. As the integrated circuits are moved upwardly into the second upper compartment, a conducting monomer selectively forms on the contact pads prior to any exposure to air.

Abstract: A first insulating film, a second insulating film, a first resist pattern is formed on a semiconductor substrate, the second insulating film is etched to form a second-insulating-film pattern, a third insulating film is deposited over the second-insulating-film pattern to form a third-insulating-film pattern, the first insulating film is etched to form a first-insulating-film pattern, a fourth insulating film and a second resist pattern is formed over the first-insulating-film pattern, fourth insulating film is etched to form a fourth-insulating-film pattern, a fifth insulating film is deposited over the fourth-insulating-film pattern to form a fifth-insulating-film pattern, line parts of first-insulating-film pattern is etched to form a first-insulating-film pattern for wiring, a wiring film is formed over the first-insulating-film pattern for wiring, the wiring film is removed until the first-insulating-film pattern for wiring is exposed to form a wiring pattern.

Abstract: A method of manufacturing a semiconductor device includes the steps of: forming recesses (a via hole and wiring grooves) in a insulation film; forming a seal layer on inside surfaces of the recesses by using a gas based on a silane having an alkyl group as a precursor; applying EB-cure or UV-cure to the seal layer; and filling up the recesses with a conductor.

Abstract: Provided is a method of forming conductors (e.g., metal lines and/or bumps) for semiconductor devices and conductors formed from the same. First and second seed metal layers may be formed. At least one mask may be formed on a portion on which a conductor is to be formed. An exposed portion may be oxidized. The oxidized portion may be removed. A conductive structure may be formed on an upper surface of a portion which is not oxidized. The conductors may be metal lines and/or bumps. The conductive structures may be solder balls.

Abstract: A chemical vapor deposition reaction system converts a reactant precursor, which includes the metal Ruthenium, to a vapor during a chemical reaction in order to deposit the metal on a semiconductor wafer. The reactant precursor is Bis(2,2,6,6-tetramethyl-3,5-heptanedionato)(1,5-cyclooctadiene)Ru. An energy source provides energy to the reaction chamber to induce the chemical reaction. A controllable metering system alternatively supplies the precursor and oxygen to the reaction chamber. The precursor is supplied into the reaction chamber during a first phase and the oxygen is supplied into the reaction chamber during a second phase, which is non-overlapping with the first phase. A first pump/valve provides the precursor to the reaction chamber, and a second pump/valve provides the oxygen to the reaction chamber, each in response to a controller. The Ruthenium is selectively deposited on oxide sites patterned on a surface of the semiconductor wafer.

Abstract: In a semiconductor device having a semiconductor film crystallized by using a metal element, it is an object to provide a technique for reducing the crystal defects in a semiconductor film, and a technique for forming a semiconductor film with high crystallinity by effectively removing impurity metal elements. An amorphous semiconductor film is formed over a transparent substrate; the amorphous semiconductor film is crystallized by using metal elements; a crystalline semiconductor film is irradiated with a first laser beam in a direction from the semiconductor film to the substrate, thereby partly melted and crystallized; and the semiconductor film is irradiated with a second laser beam through the substrate in a direction from the substrate film to the semiconductor film.

Abstract: The invention concerns a contactless numerical printing machine for products of average fluidity, such as varnish, glue, and conducting or scratchable ink, onto a substrate of variable thickness and dimensions. The machine includes a special device for printing without contact by projection. The projected materials are materials of average fluidity or composed of large-dimension molecules. The process used includes an electro-acoustic device for control of the projection, and a multiplicity of projection nozzles, each controlled individually. The machine also includes a production chain with different work stations, whose printing devices are controlled by a computer management system. The production chain allows printing with a certain precision in given zones located during the processing by an appropriate work station.

Abstract: Method for manufacturing a parylene-based electrode array that includes an underlying parylene layer, one or more patterned electrode layers comprising a conductive material such as a metal, and one or more overlying parylene layers. The overlying parylene is etched away or otherwise processed to expose the electrodes where stimulation or recording is to occur. All other conductive material in the device is occluded from the environment by the two layers of parylene surrounding it.

Abstract: In one embodiment, a selective tungsten deposition process includes the steps of pre-flowing silane into a deposition chamber, pumping down the chamber, and then selectively depositing tungsten on a silicon surface. The silane pre-flow helps minimize silicon consumption, while the pump down helps prevent loss of tungsten selectivity to silicon.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming an interlayer insulating layer and an etch-stop nitride layer over a semiconductor substrate, etching the etch-stop nitride layer and the interlayer insulating layer to form contact holes, forming contacts in the contact holes, forming an oxide layer on the entire surface including the contacts, etching the oxide layer using the etch-stop nitride layer as a target, thus forming trenches through which the contacts and the etch-stop nitride layer adjacent to the contacts are exposed, and forming bit lines in the trenches.

Abstract: In regard to an electroconductive pattern including a high resistivity region partially, by forming a pattern with a photosensitive resin, making the pattern absorb liquid containing a metal component, and baking this, an electroconductive film of metal oxide is formed, this electroconductive film is further covered by a gas shielding layer, and portions which are not shielded are reduced selectively to be made low resistance metal film regions. Since the material which constitutes the electroconductive pattern is hardly removed, a load concerning material reuse is mitigated and material cost is reduced.

Abstract: A method of forming a buried interconnection includes removing a semiconductor substrate to form a groove in the semiconductor substrate. A metal layer is formed on inner walls of the groove using an electroless deposition technique. A silicidation process is applied to the substrate having the metal layer, thereby forming a metal silicide layer on the inner walls of the groove.

Abstract: A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.

Abstract: A semiconductor device comprises metal lines in a specific metallization layer which have a different thickness and thus a different resistivity in different device regions. In this way, in high density areas of the device, metal lines of reduced thickness may be provided in order to comply with process requirements for achieving a minimum pitch between neighboring metal lines, while in other areas having less critical constraints with respect to minimum pitch, a reduced resistivity may be obtained at reduced lateral dimensions compared to conventional strategies. For this purpose, the dielectric material of the metallization layer may be appropriately patterned prior to forming respective trenches or the etch behavior of the dielectric material may be selectively adjusted in order to obtain differently deep trenches.

Abstract: A method of fabricating an integrated circuit comprises forming or providing a solution containing carbon nanotubes and forming a metal layer utilizing the solution.

Abstract: A power semiconductor IC device is disclosed. In one embodiment, the device includes a substrate, and a layer structure formed on the substrate. The layer structure includes a metallization layer including copper, wherein the metallization layer is formed as a stack structure including at least two copper layers and a stabilization layer between the two copper layers.

Abstract: A substrate processing method can securely form a metal film by electroless plating on an exposed surface of a base metal, such as interconnects, with increased throughput and without the formation of voids in the base metal. The substrate processing method includes: cleaning a surface of a substrate having a base metal formed in the surface with a cleaning solution comprising an aqueous solution of a carboxyl group-containing organic acid or its salt and a surfactant as an additive; bringing the surface of the substrate after the cleaning into contact with a processing solution comprising a mixture of the cleaning solution and a solution containing a catalyst metal ion, thereby applying the catalyst to the surface of the substrate; and forming a metal film by electroless plating on the catalyst-applied surface of the substrate.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming barrier metals on first electrodes provided on a chip of the semiconductor device, implementing a predetermined test on the semiconductor device by applying a signal to the semiconductor device via at least one of the barrier metals, and forming second protruded electrodes on the barrier metals. The predetermined tests are implemented before forming second protruded electrodes on the barrier metals.

Abstract: A multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device, and a method for forming the cap.

Abstract: The present invention provides nano-patterning based on flow of an ion current within an ionic conductor to bring ions in proximity to a microscope probe tip touching a surface of the conductor. These ions are then electrochemically reduced to form one or more features on the surface. Ion current flow and the electrochemical reaction are driven by an electrical potential difference between the tip and the ionic conductor. Such features can be erased by reversing the polarity of the potential difference. Indentations can be formed by mechanically removing features formed as described above. The ions in the ion current can be provided by the ionic conductor and/or by oxidation at a counter electrode.