Abstract: A method of manufacturing an intermediate product for an interposer including a glass substrate having a plurality of through holes is provided. The method includes a step of forming a resin layer on a support substrate, and a step of forming a laminated body by adhering the glass substrate having the plurality of through holes on the resin layer. The glass substrate having the plurality of through holes has a thickness within a range of 0.05 mm to 0.3 mm.

Abstract: Methods, devices and systems for patterning of substrates using charged particle beams without photomasks and without a resist layer. Material can be removed from a substrate, as directed by a design layout database, localized to positions targeted by multiple, matched charged particle beams. Reducing the number of process steps, and eliminating lithography steps, in localized material removal has the dual benefit of reducing manufacturing cycle time and increasing yield by lowering the probability of defect introduction. Furthermore, highly localized, precision material removal allows for controlled variation of removal rate and enables creation of 3D structures or profiles. Local gas injectors and detectors, and local photon injectors and detectors, are local to corresponding ones of the columns, and can be used to facilitate rapid, accurate, targeted substrate processing.

Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.

Abstract: An image sensing device includes: an active layer with a plurality of photo-sensing elements; a color pattern disposed over one of the photo-sensing elements, wherein the color pattern has a color selected from the group consisting of red (R), green (G), and blue (B); a microlens disposed on the color pattern; and a transmissive pattern being adjacent to the color pattern and over another one of the photo-sensing elements, wherein the transmissive pattern includes a color filter portion and a microlens portion, and an absolute value of a difference of refractive indexes between the microlens and the color pattern is less than 0.3, and there is no difference of refractive indexes between the microlens portion and the color filter portion of the transmissive pattern.

Abstract: A method for treating a microelectronic substrate to form a chemical template includes patterning the substrate to form a trench structure with a plurality of trenches of a defined trench width and depositing a photoactive material on the substrate to overfill the trench structure to form a fill portion in the plurality of trenches and an overfill portion above the trench structure. The method further includes exposing the photoactive material to electromagnetic radiation comprising a wavelength that is at least four times greater than the defined trench width such that the overfill portion is modified by the exposure while the electromagnetic radiation fails to penetrate into the plurality of trenches leaving the fill portion unmodified and removing the modified overfill portion of the photoactive material to form a planarized filled trench structure for use as a chemical template for selective reactive ion etching, selective deposition, or directed self-assembly.

Abstract: According to one embodiment, a magnetic recording medium includes a silicon oxide underlayer having a recess pattern having a plurality of recesses, a nonmagnetic underlayer having a first hole pattern having a plurality of holes corresponding to the recess pattern, and a magnetic recording layer having a second hole pattern having a plurality of holes connected with the first hole pattern. The silicon oxide underlayer, the nonmagnetic underlayer, and the magnetic recording layer are formed in order on the substrate.

Abstract: Methods to utilize efficient processes to form and use merged spacers in fin generation and the resulting devices are disclosed. Embodiments include providing mandrels separated from each other across two adjacent bit-cells on an upper surface of a dielectric layer on an upper surface of a silicon (Si) layer; forming first spacers on opposite sides of each mandrel; forming second spacers on exposed sides of the first spacers; removing the mandrels; removing exposed sections of the dielectric layer; removing the first and second spacers; forming fin-spacers on opposite sides of remaining sections of the dielectric layer; removing the remaining sections of the dielectric layer; removing exposed sections of the Si layer; and removing the fin-spacers to reveal Si fins.

Abstract: In a method of forming holes, a plurality of guide patterns physically spaced apart from each other is formed on an object layer. The guide pattern has a ring shape and includes a first opening therein. A self-aligned layer is formed on the object layer and the guide patterns to fill the first opening. Preliminary holes are formed by removing portions of the self-aligned layer which are self-assembled in the first opening and between the guide patterns neighboring each other. The object layer is partially etched through the preliminary holes.

Abstract: A pattern forming method includes forming a spin on dielectric film on a substrate, washing the spin on dielectric film by using a washing liquid, drying a surface of the spin on dielectric film after the washing, forming a photosensitive film on the dried coating type insulation film, emitting energy rays to a predetermined position of the photosensitive film in order to form a latent image on the photosensitive film, developing the photosensitive film in order to form a photosensitive film pattern which corresponds to the latent image, and processing the spin on dielectric film with the photosensitive film pattern serving as a mask.

Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.

Abstract: A method for fabricating a semiconductor device is provided, which includes forming a first mask pattern and a second mask pattern on a first layer, forming a block mask that covers the second mask pattern on the first layer, forming first spacers on side walls of the first mask pattern, exposing the second mask pattern through removal of the first mask pattern and the block mask, forming a third mask pattern and a fourth mask pattern through etching of the first layer using the first spacers and the second mask pattern as etch masks, and forming second spacers and third spacers on side walls of the third mask pattern and side walls of the fourth mask pattern, respectively.

Abstract: A method includes forming a first etch target layer and a first mask layer on a substrate. Sacrificial patterns extending in a first direction are formed on the first mask layer in a second direction. Spacers are formed on sidewalls of the sacrificial patterns. After removing the sacrificial patterns, the first mask layer is etched using the spacers as an etching mask to form first masks. Second masks are formed on sidewalls of each first mask to define a third masks including each first mask and the second masks on sidewalls of each first mask. The first etch target layer is etched using the first and third masks as an etching mask to form first and second patterns in the first and second regions, respectively. Each first pattern has a first width, and each second pattern has a second width greater than the first width.

Abstract: A method to generate chemo-epitaxy masks includes receiving a device pattern comprising a plurality of device geometries, wherein the device pattern conforms to chemo-epitaxy constraints, enlarging the device geometries along a width of the device geometries to provide enlarged device geometries, and using the enlarged device geometries to generate at least one chemo-epitaxy mask corresponding to the device pattern. The at least one chemo-epitaxy mask may include a neutral hard mask and one or more cut masks. The method may also include bridging device geometries that are within a selected distance along a length of the device geometries and merging device geometries that overlap. The method may also include filling break regions between the device geometries with a neutral fill pattern. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having at least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.

Abstract: In accordance with this disclosure, there is provided several inventions, including a method for etching a plurality of features in a stack comprising alternating layers above a substrate, comprising: providing a steady state flow of an etching gas, wherein the etching gas comprises: a molecule A comprising sulfur and fluorine; a molecule B comprising carbon, fluorine, and hydrogen; and a molecule C comprising carbon and fluorine and not hydrogen; forming the etching gas into a plasma; and etching the features into the stack through the plurality of alternating layers.

Abstract: Various embodiments provide transistors and methods for forming the same. In an exemplary method, a substrate is provided, having a dummy gate structure including a dummy gate dielectric layer on the substrate and a dummy gate layer on the dummy gate dielectric layer. A dielectric layer is formed on the substrate and on sidewall surfaces of the dummy gate structure. A top surface of the dielectric layer is leveled with a top surface of the dummy gate structure. A barrier layer is formed on the dielectric layer for protecting the dielectric layer. The dummy gate layer and the dummy gate dielectric layer are removed, to form an opening in the dielectric layer without reducing a thickness of the dielectric layer. A gate dielectric layer is formed on sidewall surfaces and a bottom surface of the opening. A gate layer is formed on the gate dielectric layer to fill the opening.

Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor in combination with an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor or an alcohol. The combination react with the patterned heterogeneous structures to remove an exposed silicon oxide portion faster than a second exposed portion. The inclusion of the oxygen-containing precursor may suppress the second exposed portion etch rate and result in unprecedented silicon oxide etch selectivity.

Abstract: A metal gate forming process includes the following steps. A first metal layer is formed on a substrate by at least a first step followed by a second step, wherein the processing power of the second step is higher than the processing power of the first step.

Abstract: The present invention relates to a substrate processing apparatus: including a chamber comprising a body having an inner space and a top lid provided on an upper part of the body, the top lid having at least one gas input port; a substrate supporting unit rotatably installed inside the chamber to support a plurality of substrates; and a gas injection device comprising a central injection unit provided on an upper part of the substrate supporting unit to inject a gas into a central region of the substrate supporting unit, a source gas injection unit provided around the central injection unit to inject a source gas into the substrate supporting unit, a reaction gas injection unit provided around the central injection unit to inject a reaction gas into the substrate supporting unit and a purge gas injection unit disposed between the source gas injection unit and the reaction gas injection unit; wherein at least one of the source gas injection unit and the reaction gas injection unit comprises a main injection un

Abstract: One example of a method includes heating a ground steel part that has been chemical-etched. The method also includes detecting defects caused by grinding and watermarks caused by chemical etching by imaging the steel part with an infrared camera to capture infrared radiation from regions of the steel part that include defects and watermarks. Imaging the steel part can include imaging regions of the steel part at long-wavelengths of infrared radiation to detect defects on the regions of the steel part and generating a first image wherein the defects are visible in the image and the watermarks are not visible in the image.

Abstract: Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate. A via pattern including a plurality of openings may be defined above the substrate. A spacer material layer is formed on a sidewall at least one trench. Via holes can be etched in the dielectric layer using the via pattern and spacer material layer as a masking element.

Abstract: An organic light-emitting device includes, in order an anode, an organic layer comprising a light-emitting layer, and a cathode. The anode is a laminated structure comprising in order: a first anode layer comprising a metal compound or a conductive oxide; a second anode layer that is a reflective layer; and a third anode layer comprising a metal compound or a conductive oxide. Light generated in the light-emitting layer is extracted through the cathode.

Abstract: A method for fabricating a semiconductor device includes forming an etching target layer over a substrate including a first region and a second region; forming a hard mask layer over the etching target layer; forming a first etch mask over the hard mask layer, wherein the first etch mask includes a plurality of line patterns and a sacrificial spacer layer formed over the line patterns; forming a second etch mask over the first etch mask, wherein the second etch mask includes a mesh type pattern and a blocking pattern covering the second region; removing the sacrificial spacer layer; forming hard mask layer patterns having a plurality of holes by etching the hard mask layer using the second etch mask and the first etch mask; and forming a plurality of hole patterns in the first region by etching the etching target layer using the hard mask layer patterns.

Abstract: To provide a wiring board in which wiring conductors are securely protected by a precise and rigid dam portion formed on an outermost layer of a laminate and that is excellent in connection reliability with a semiconductor chip. A laminate that configures this wiring board includes multiple connection terminal portions and wiring conductors as a conductor layer of the outermost layer. The wiring conductors are arranged at predetermined positions, passing through between multiple connection terminal portions for flip-chip mounting a semiconductor chip. A resin insulating layer of the outermost layer of the laminate has a dam portion and a reinforcement portion. The dam portion covers the wiring conductors. The reinforcement portion is formed, between the wiring conductor and the connection terminal portion that is adjacent to the wiring conductor, lower than a height of the dam portion. The reinforcement portion is concatenated with a side surface of the dam portion.

Abstract: A process for depositing a silicon carbon nitride film on a substrate can include a plurality of complete deposition cycles, each complete deposition cycle having a SiN sub-cycle and a SiCN sub-cycle. The SiN sub-cycle can include alternately and sequentially contacting the substrate with a silicon precursor and a SiN sub-cycle nitrogen precursor. The SiCN sub-cycle can include alternately and sequentially contacting the substrate with carbon-containing precursor and a SiCN sub-cycle nitrogen precursor. The SiN sub-cycle and the SiCN sub-cycle can include atomic layer deposition (ALD). The process for depositing the silicon carbon nitride film can include a plasma treatment. The plasma treatment can follow a completed plurality of complete deposition cycles.

Abstract: A manufacturing process, which we term Self-Aligned Capillarity-Assisted Lithography for manufacturing devices having nano-scale or micro-scale features, such as flexible electronic circuits, is described.

Abstract: Methods of performing a wet oxidation process on a silicon containing dielectric material filling within trenches or vias defined within a substrate are provided. In one embodiment, a method of forming a dielectric material on a substrate includes forming a dielectric material on a substrate by a flowable CVD process, curing the dielectric material disposed on the substrate, performing a wet oxidation process on the dielectric material disposed on the substrate, and forming an oxidized dielectric material on the substrate.

Abstract: A method for mask optimization, the method including moving any features of a gate contact mask that are in violation of a spacing rule to a second layer contact mask, splitting an elongated feature of the second layer mask that is too close to a feature moved to the second layer mask from the gate contact mask, and connecting two split features of a first layer contact mask, the split features corresponding to the elongated feature of the second layer mask.

Abstract: A robust metallization profile is formed by forming two or more layers of hard mask with different density. Multi-layer metal hard mask is helpful especially in small feature size process, for example, 50 nm and below. Lower layers have higher density. In such ways, enough process window is offered by lower layers and at the same time, round hard mask profile is offered by upper layers.

Abstract: A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels.

Abstract: The present disclosure provides a method for fabricating semiconductor devices. The method includes providing a substrate with a gate electrode film on the substrate and a gate electrode pattern film on the gate electrode film; forming at least one pattern layer on the gate electrode pattern film; and using the at least one pattern layer as the etch mask to etch portions of the gate electrode pattern film to expose portions of the gate electrode film and form a gate electrode pattern layer on the gate electrode film, the gate electrode pattern layer including a hard mask layer and a silicon layer, and sidewalls of the silicon layer in a direction perpendicular to a first direction having a first poly line width roughness. The method also includes performing an etch-repairing treatment on the sidewalls of the silicon layer in the direction perpendicular to the first direction.

Abstract: Methods of etching a patterned substrate may include flowing an oxygen-containing precursor into a first remote plasma region fluidly coupled with a substrate processing region. The oxygen-containing precursor may be flowed into the region while forming a plasma in the first remote plasma region to produce oxygen-containing plasma effluents. The methods may also include flowing a fluorine-containing precursor into a second remote plasma region fluidly coupled with the substrate processing region while forming a plasma in the second remote plasma region to produce fluorine-containing plasma effluents. The methods may include flowing the oxygen-containing plasma effluents and fluorine-containing plasma effluents into the processing region, and using the effluents to etch a patterned substrate housed in the substrate processing region.

Abstract: The present disclosure describes methods for transferring a desired layout into a target layer. The method includes a step of forming a spacer, having a second width, around a first and a second desired layout feature pattern of the desired layout over a semiconductor substrate. The first desired layout feature pattern is formed using a first sub-layout and the second desired layout feature pattern is formed using a second sub-layout. The first and second desired layout feature patterns are separated by a first width. The method further includes forming a third desired layout feature pattern according to a third sub-layout. The third desired layout feature pattern is shaped in part by the spacer. The method further includes removing the spacer from around the first and second desired layout feature pattern and etching the target layer using the first, second, and third layout feature patterns as masking features.

Abstract: Wire grid polarizers, and methods of making wire grid polarizers, including an array of parallel, elongated nano-structures disposed over a surface of a substrate. Each of the nano-structures can include a first rib disposed over a surface of a substrate and a pair of parallel, elongated wires, each laterally oriented with respect to one another, and disposed over the first rib. The wire grid polarizers can be durable with high transmission of one polarization of light, high contrast, and/or small pitch. The wire grid polarizers can also have high absorption or high reflection of an opposite polarization of light.

Abstract: A semiconductor device includes a substrate having an active region and a device isolation layer defining the active region, a gate electrode on the active region, source/drain regions at the active region at both sides of the gate electrode, a buffer insulating layer on the device isolation layer, an etch stop layer formed on the buffer insulating layer and extending onto the gate electrode and the source/drain region, a first interlayer insulating layer on the etch stop layer, a first contact and a second contact penetrating the first interlayer insulating layer and the etch stop layer. The first contact and the second contact are spaced apart from each other and are in contact with the source/drain region and the buffer insulating layer, respectively.

Abstract: A wire grid polarizer comprising an array of parallel, elongated nano-structures disposed over a surface of a substrate. Each of the nano-structures can include a pair of parallel, elongated wires (or top ribs), each oriented laterally with respect to one another. There can be a first gap disposed between the pair of wires (or top ribs). Each of the nano-structures can be separated from an adjacent nano-structure by a second gap disposed between adjacent nanostructures, and thus between adjacent pairs of wires. A first gap width of the first gap can be different than a second gap width of the second gap. Also included are methods of making wire grid polarizers.

Abstract: Techniques herein enable executing directed self-assembly of block copolymer patterning processes that result in patterns having no defects or a negligibly low occurrence of defects to have a high yield of functional patterns and devices. Methods include executing a same DSA patterning sequence two or more times such that any defects in from a phase-separated first block copolymer film are corrected with a phase-separated second block copolymer film as any defect in the second block copolymer film would only temporarily cover a feature already created and/or transferred from first block copolymer film.

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

Abstract: The present invention provides a method for manufacturing contact holes of a semiconductor device, including a first dielectric layer is provided, a first region and a second region are defined on the first dielectric layer respectively, at least two cutting hard masks are formed and disposed within the first region and the second region respectively, at least two step-height portions disposed right under the cutting hard masks respectively. Afterwards, at least one first slot opening within the first region is formed, where the first slot opening partially overlaps the cutting hard mask and directly contacts the cutting hard mask, and at least one second contact opening is formed within the second region, where the second contact opening does not contact the cutting hard mask directly, and at least two contact holes are formed, where each contact hole penetrates through each step height portion.

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

Abstract: Semiconductor devices with graphene nanoribbons and methods of manufacture are disclosed. The method includes forming at least one layer of Si material on a substrate. The method further includes forming at least one layer of carbon based material adjacent to the at least one layer of Si. The method further includes patterning at least one of the at least one layer of Si material and the at least one layer of carbon based material. The method further includes forming graphene on the patterned carbon based material.

Abstract: A semiconductor device includes a semiconductor substrate, an active region and a trench isolation. The active region is formed in the semiconductor substrate. The trench isolation is disposed adjacent to the active region. The trench isolation includes a lower portion and an upper portion. The upper portion is located on the lower portion. The upper portion has a width gradually decreased from a junction between the upper portion and the lower portion toward a top of the trench isolation. In a method for fabricating the semiconductor device, at first, the semiconductor substrate is etched to form a trench in the semiconductor substrate. Then, an insulator fills the trench to form the trench isolation. Thereafter, the gate structure is formed on the semiconductor substrate. Then, the semiconductor substrate is etched to form a recess adjacent to the trench isolation. Thereafter, at least one doped epitaxial layer grows in the recess.

Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.

Abstract: A method includes forming a first pattern having a first feature of a first material on a semiconductor substrate. A second pattern with a second feature and third feature of a second material, interposed by the first feature, is formed on the semiconductor substrate. Spacer elements then are formed on sidewalls of the first feature, the second feature, and the third feature. After forming the spacer elements, the second material comprising the second and third features is selectively removed to form a first opening and a second opening. The first feature, the first opening and the second opening are used as a masking element to etch the target layer.

Abstract: Embodiments of the present invention pertain to methods of forming more symmetric spacers which may be used for self-aligned multi-patterning processes. A conformal spacer layer of spacer material is formed over mandrels patterned near the optical resolution of a photolithography system using a high-resolution photomask. A carbon-containing layer is further formed over the conformal spacer layer. The carbon-containing layer is anisotropically etched to expose the high points of the conformal spacer layer while retaining carbon side panels. The conformal spacer layer may then be etched to form spacers without the traditional skewing of the profile towards one side or the other.

Abstract: Methods for determining a target thickness of a conformal film with reduced uncertainty, and an integrated circuit (IC) chip having a conformal film of the target thickness are provided. In an embodiment, a first critical dimension of a structure disposed on a wafer is measured. Said structure has at least one vertical surface. A first conformal film is deposited over the structure covering each of a horizontal and the vertical surface of the structure. A second critical dimension of the covered structure is then measured. The target thickness of the conformal film is determined based on difference between the first CD measured on the structure and the second CD measured on the covered structure.

Abstract: To provide a light-emitting device that is provided with an optical member firmly bonded to a semiconductor light-emitting element and has a high light extraction efficiency, the light-emitting device includes a light-emitting element having a semiconductor layer and an optical member bonded to the light-emitting surface of the light-emitting element with a metal film being interposed therebetween wherein the metal film has a thickness in a film-forming rate conversion not less than 0.05 nm nor more than 2 times of an atomic diameter of the metal atoms forming the metal film.

Abstract: Manufacture for an improved stacked-layered thin film solar cell. Solar cell has reduced absorber thickness and an improved back contact for Copper Indium Gallium Selenide solar cells. The back contact provides improved reflectance particularly for infrared wavelengths while still maintaining ohmic contact to the semiconductor absorber. This reflectance is achieved by producing a back contact having a highly reflecting metal separated from an absorbing layer with a dielectric layer.

Abstract: Provided are an organic light emitting display apparatus and a method of manufacturing the same. The organic light emitting display apparatus includes: a thin film transistor (TFT) substrate including a plurality of thin film transistors, an organic light-emissive device on the TFT substrate, and an encapsulation layer on the TFT substrate and the organic light-emissive device, the encapsulation layer being configured to cover the organic light-emissive device, the encapsulation layer including a hybrid material including: a block copolymer, and functionalized graphene.