Abstract: According to various embodiments, a method for processing an electronic device may include: forming a patterned hard mask layer over a power metallization layer, the patterned hard mask layer exposing at least one surface region of the power metallization layer; and patterning the power metallization layer by wet etching of the exposed at least one surface region of the power metallization layer.

Abstract: Methods and apparatuses for spacer profile control using atomic layer deposition (ALD) in multi-patterning processes are described herein. A silicon oxide spacer is deposited over a patterned core material and a target layer of a substrate in a multi-patterning scheme. A first thickness of the silicon oxide spacer is deposited by multiple ALD cycles under a first oxidation condition that includes an oxidation time, a plasma power, and a substrate temperature. A second thickness of the silicon oxide spacer is deposited by multiple ALD cycles under a second oxidation condition, where the second oxidation condition is different than the first oxidation condition by one or more parameters. After etching the patterned core material, a resulting profile of the silicon oxide spacer is dependent at least in part on the first and second oxidation conditions.

Abstract: A composition for forming a silica based layer, the composition including a silicon-containing polymer having polydispersity ranging from about 3.0 to about 30 and a solvent, and having viscosity ranging from about 1.30 centipoise (cps) to about 1.80 cps at 25° C. Also, a silica based layer is formed of the composition, and an electronic device includes the silica based layer.

Abstract: A method of manufacturing a semiconductor structure includes forming a lower hard mask layer on a substrate. A patterned middle hard mask layer is formed on the lower hard mask layer, and the patterned middle hard mask layer has a plurality of openings exposing a portion of the lower hard mask layer. A patterned lower hard mask layer and a textured substrate having a plurality of trenches are formed by etching the exposed portion of the lower hard mask layer and a portion of the substrate under the exposed portion of the lower hard mask layer. A steam treatment is then performed on the textured substrate having the trenchess. An isolation oxide layer is formed to fill the trenches.

Abstract: A method for forming a semiconductor device is disclosed. A p-type field-effect transistor (p-FET) is formed on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate and completely covers the p-FET. At least an opening is formed in the dielectric layer and exposes a source/drain region of the p-FET. A conductive material is then formed filling the opening, wherein the conductive material comprises a first stress; specifically, a tensile stress between 400 and 800 MPa.

Abstract: Disclosed is a method for mechanically anchoring polymers on the surface of a porous substrate by trapping polymer chains within the pores of the substrate under capillary forces. Surface modification of the porous substrate is achieved by anchoring one end of the polymer chains within the pores while one or more other ends of the polymer chains dangle from the surface of the porous substrate. The method provides a unique way of modifying the surface of a material without chemical reactions or precursor-substrate interactions.

Abstract: A process flow for shrinking a critical dimension (CD) in photoresist features and reducing CD non-uniformity across a wafer is disclosed. A photoresist pattern is treated with halogen plasma to form a passivation layer with thickness (t1) on feature sidewalls, and thickness (t2) on the photoresist top surface where t2>t1. Thereafter, an etch based on O2, or O2 with a fluorocarbon or halogen removes the passivation layer and shrinks the CD. The passivation layer slows the etch such that photoresist thickness is maintained while CD shrinks to a greater extent for features having a width (d1) than on features having width (d2) where d1>d2. Accordingly, CD non-uniformity is reduced from 2.3% to 1% when d2 is 70 nm and is shrunk to 44 nm after the aforementioned etch. After a second etch through a MTJ stack to form MTJ cells, CD non-uniformity is maintained at 1%.

Abstract: The present disclosure involves forming a method of fabricating a Micro-Electro-Mechanical System (MEMS) device. A plurality of openings is formed in a first side of a first substrate. A dielectric layer is formed over the first side of the substrate. A plurality of segments of the dielectric layer fills the openings. The first side of the first substrate is bonded to a second substrate that contains a cavity. The bonding is performed such that the segments of the dielectric layer are disposed over the cavity. A portion of the first substrate disposed over the cavity is transformed into a plurality of movable components of a MEMS device. The movable components are in physical contact with the dielectric the layer. Thereafter, a portion of the dielectric layer is removed without using liquid chemicals.

Abstract: Exemplary methods for removing tungsten-containing material may include flowing a chlorine-containing precursor into a processing region of a semiconductor processing chamber. The methods may also include flowing methane into the processing region of the semiconductor processing chamber. The methods may include forming a plasma from the chlorine-containing precursor and the methane to produce plasma effluents. The methods may also include contacting a substrate with the plasma effluents. The substrate may include an exposed region of a tungsten-containing material. The plasma effluents may produce an oxychloride of tungsten. The methods may also include recessing the exposed region of the tungsten-containing material.

Abstract: Disclosed is a substrate processing apparatus including a disc provided so as to be rotatable on its axis, at least one susceptor disposed on the disc such that a substrate is seated on an upper surface thereof, the susceptor being configured to rotate on its axis and to revolve around a center of the disc as the disc rotates on its axis, a metal ring coupled to a lower portion of the susceptor, the metal ring being arranged such that a center thereof coincides with a center of the susceptor, and a magnet provided below the disc so as to be radially arranged on a basis of the center of the disc, at least a portion of the magnet being opposite the metal ring in a vertical direction.

Abstract: A method for isotropically etching film on a substrate with atomic layer control includes a) providing a substrate including a material selected from a group consisting of silicon (Si), germanium (Ge) and silicon germanium (SiGe). The method includes b) depositing a sacrificial layer on the material in a processing chamber by: cooling a lower portion of the substrate; one of creating or supplying an oxidant-containing plasma in the processing chamber; and increasing a surface temperature of the substrate for a predetermined period using rapid thermal heating while creating or supplying the oxidant-containing plasma in the processing chamber. The method includes c) purging the processing chamber. The method includes d) etching the sacrificial layer and the material by supplying an etch gas mixture and striking plasma in the processing chamber.

Abstract: Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate.

Abstract: A method for forming a semiconductor device in a plasma processing chamber is provided. An atomic layer etch selectively etches SiO with respect to SiN and deposits a fluorinated polymer. The fluorinated polymer layer is stripped, comprising flowing a stripping gas comprising oxygen into the plasma processing chamber, forming a plasma from the stripping gas, and stopping the flow of the stripping gas. A SiN layer is selectively etched with respect to SiO and SiGe and Si.

Abstract: A light-emitting device may include an active layer. The light-emitting device may include a first semiconductor layer of a first conductivity type. The first semiconductor layer may be in physical contact with the active layer. The light-emitting device may also include a second semiconductor layer of a second conductivity type. The second semiconductor layer may be in physical contact with the active layer and opposite the first conductive layer. The light-emitting device may further include a first electrode in physical contact with a first side of the first semiconductor layer. The light-emitting device may additionally include a second electrode in physical contact with a second side of the first semiconductor layer. The second side of the first semiconductor layer may be different from the first side of the first semiconductor layer. The light-emitting device may also include a third electrode in physical contact with the second semiconductor layer.

Abstract: Provided is a material composition and method for that includes forming a silicon-based resin over a substrate. In various embodiments, the silicon-based resin includes a nitrobenzyl functional group. In some embodiments, a baking process is performed to cross-link the silicon-based resin. Thereafter, the cross-linked silicon-based resin is patterned and an underlying layer is etched using the patterned cross-linked silicon-based resin as an etch mask. In various examples, the cross-linked silicon-based resin is exposed to a radiation source, thereby de-cross-linking the silicon-based resin. In some embodiments, the de-cross-linked silicon-based resin is removed using an organic solution.

Abstract: Provided is a method of fabricating a semiconductor device. An integrated circuit (IC) layout plan is obtained. The IC layout plan contains critical features and non-critical features. Locational information regarding a defect on a blank reticle is obtained. The blank reticle is a candidate reticle for being patterned with the IC layout plan. Based on the locational information regarding the defect and the IC layout plan, a determination is made that at some of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan, regardless of whether the IC layout plan is globally manipulated or not before being patterned onto the blank reticle. In response to the determination, selected local portions of the IC layout plan are re-arranged such that none of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan.

Abstract: A graphene electronic device includes a gate insulating layer on a conductive substrate, a channel layer on the gate insulating layer, and a source electrode on one end of the channel layer and a drain electrode on another end of the channel layer. The channel layer includes a semiconductor layer and a graphene layer in direct contact with the semiconductor layer, and the graphene layer includes a plurality of graphene islands spaced apart from each other.

Abstract: A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.

Abstract: A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop layer on the spacers and the source/drain region and forming a gate structure between the spacers. The method further includes etching back the gate structure, etching back the spacers and the etch back layer, and forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip; a second interconnection member disposed on the first interconnection member and the semiconductor chip; and connection terminals disposed on the second interconnection member. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip, and a connection pad and a connection terminal are electrically connected to each other by a pathway passing through the redistribution layer of the first interconnection member.

Abstract: Block copolymers comprise a first block comprising an alternating copolymer, and a second block comprising a unit comprising a hydrogen acceptor. The block copolymers find particular use in pattern shrink compositions and methods in semiconductor device manufacture for the provision of high resolution patterns.

Abstract: A substrate processing device includes a holding member for holding a substrate, and an opposed member having a body portion and an extended portion extending from at least a part of a peripheral edge part of the body portion. A protrusion is provided on one part of a tip side part of the extended portion and a side surface part of the holding member, and the other part is provided with a restricting structure disposed opposite to the protrusion and restricting relative motion of the protrusion. The relative motion between the holding member and the opposed member is restricted, and the substrate processing device further includes a rotating mechanism, and a nozzle for discharging a processing solution and the protrusion and the restricting structure are disposed below an upper surface of the holding member.

Abstract: A method includes forming mask patterns spaced apart from each other by at least one opening on an etch target layer, filling the opening with a block copolymer material including first and second polymer blocks of different properties, and annealing the block copolymer material to form first patterns and second patterns, the first patterns in contact with facing sidewalls of adjacent ones of the mask patterns, respectively, and at least one of the second patterns between the first patterns. The first patterns include the first polymer blocks and the second patterns include the second polymer blocks.

Abstract: In an example, a silicone-based thermal interface material includes a thermally conductive material and a silicone-based polymeric material having a solubility parameter that is not less than 9.09 cal1/2 cm?3/2.

Abstract: According to one embodiment, a pattern formation method includes forming a base structure including first and second guide portions each including a pinning portion, and a neutral portion, forming a block copolymer film containing first and second polymers on the bass structure, performing a predetermined treatment for the block copolymer film, thereby forming first and second pattern portions formed of the first polymer, forming third and fourth pattern portions formed of the second polymer, and forming a fifth pattern portion formed of the first and second polymers. The fifth pattern portion includes a plurality of first portions formed of the second polymer, and a second portion formed of the first polymer and provided on the neutral portion and the first portions.

Abstract: Methods for processing a substrate include: (a) depositing a cobalt layer to a first thickness within a first plurality of features and a second plurality of features formed in a substrate, wherein each of the first plurality of features and each of the second plurality of features comprises an opening, and wherein a width of the openings of the first plurality of features is less than a width of the openings of the second plurality of features; and (b) heating the substrate to a first temperature to fill the first plurality of features with cobalt material while simultaneously depositing a fill material on the substrate to fill the second plurality of features.

Abstract: Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate. A spacer material layer is formed over the plurality of trenches. A via pattern including a plurality of openings is formed over the spacer material layer and plurality of trenches. Via holes can be etched in the dielectric layer using the via pattern and spacer material layer as a masking element.

Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants having low sticking coefficients in some embodiments. The protective coating may also be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. In some cases the protective coating is deposited using plasma assisted atomic layer deposition or plasma assisted chemical vapor deposition.

Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.

Abstract: According to one embodiment, a pattern data creating method includes a calculation process, a determination process, and a correction process. In the calculation process, it is calculated a stress distribution of stresses that are applied to a template when a distance between the template and a substrate on which resist are disposed is predetermined, the template including a template pattern. In the determination process, it is determined whether or not there is a stress concentration spot in the template pattern at which a stress value larger than a predetermined criterion value is to appear. If the stress concentration spot is present, in the correction process, it is a corrected pattern data of the template pattern such that the stress value at the stress concentration spot becomes a stress value not larger than the predetermined criterion value.

Abstract: In the examples provided herein, a device is described that has a stack of structure layers including a first structure layer and a second structure layer that are different materials, where the first structure layer is positioned higher in the stack than the second structure layer. The device also has a first sidewall spacer deposited conformally and circumferentially around an upper portion of the stack that includes the first structure layer. Further, the device has a second sidewall spacer deposited conformally and circumferentially around the first sidewall spacer and an additional portion of the stack that includes the second structure layer, where a height of the first sidewall spacer along the stack is different from a height of the second sidewall spacer.

Abstract: A patterns forming method begins with performing a lithography process on a photoresist film with a photomask having first apertures in a first mask region and second apertures in a second mask region to respectively form first main features and dummy features, on which the second mask region is located between the border of the photomask and the first mask region, and a size of each of the first apertures is greater than a size of each of the second apertures. Subsequently, a material is filled into the first main features to respectively form second main features and into the dummy features to seal the dummy features. Then, a substrate is etched to form patterned features by using the photoresist film having the second main features.

Abstract: A method is disclosed to prepare a substrate for photolithography. The method includes forming an underlayer over a surface of the substrate; depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer. Also disclosed is a structure configured for photolithography. The structure includes a substrate; an underlayer over a surface of the substrate; an interface hardmask layer disposed on the underlayer; and a layer of EUV resist disposed on the interface hardmask layer. The interface hardmask layer contains material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer.

Abstract: In one embodiment, a conductive line structure includes a substrate and a plurality of conductive lines thereon. The substrate has a first area and a second area, and the two areas are separated by at least one borderline. The plurality of conductive lines are disposed at the first area and the second area of the substrate, respectively. The at least one borderline may be a straight line, and the conductive lines disposed at the second area are inclined relative to the at least one borderline. A sensing device using the conductive line structure is also provided.

Abstract: Provided herein are methods and related apparatus to smooth the edges of features patterned using extreme ultraviolet (EUV) lithography. In some embodiments, at least one cycle of depositing passivation layer that preferentially collects in crevices of a feature leaving protuberances exposed, and etching the feature to remove the exposed protuberances, thereby smoothing the feature, is performed. The passivation material may preferentially collect in the crevices due to a higher surface to volume ratio in the crevices than in the protuberances. In some embodiments, local critical dimension uniformity (LCDU), a measure of roughness in contact holes, is reduced. In some embodiments, at least one cycle of depositing a thin layer in a plurality of holes formed in photoresist, the holes having different CDs, wherein the thin layer preferentially deposits in the larger CD holes, and anisotropically removing the thin layer to remove it at the bottoms of the holes, is performed.

Abstract: A lithography method and accompanying structure for decreasing the critical dimension (CD) and improving the CD uniformity within semiconductor devices uses a layer of silicon carbide as an embedded blocking mask for defining semiconductor architectures, including contact trench openings to form trench silicide contacts.

Abstract: A first film (3) is formed on a front surface of a semiconductor wafer (1). A second film (4) is formed on the first film (3). A surface protection film (5) is formed to cover the first film (3) and second film (4). After forming the surface protection film (5), a reverse surface of the semiconductor wafer (1) is etched with a chemical liquid. The first film (3) is formed on an outer peripheral section of the semiconductor wafer (1). The second film (4) is not formed on the outer peripheral section of the semiconductor wafer (1). The first film (3) and the surface protection film (5) are adhered to each other in the outer peripheral section of the semiconductor wafer (1). The first film (3) has a higher adhesion to the surface protection film (5) than the second film (4).

Abstract: Techniques and structures for protecting etched features during etch mask removal. In embodiments, a mask is patterned and a substrate layer etched to transfer the pattern. Subsequent to etching the substrate layer, features patterned into the substrate are covered with a sacrificial material backfilling the etch mask. At least a top portion of the mask is removed with the substrate features protected by the sacrificial material. The sacrificial material and any remaining portion of the mask are then removed. In further embodiments, a gate contact opening etched into a substrate layer is protected with a sacrificial material having the same composition as a first material layer of a multi-layered etch mask. A second material layer of the etch mask having a similar composition as the substrate layer is removed before subsequently removing the sacrificial material concurrently with the first mask material layer.

Abstract: On an RAMO4 substrate containing a single crystal represented by the general formula RAMO4 (wherein R represents one or a plurality of trivalent elements selected from a group of elements including: Sc, In, Y, and a lanthanoid element, A represents one or a plurality of trivalent elements selected from a group of elements including: Fe(III), Ga, and Al, and M represents one or a plurality of divalent elements selected from a group of elements including: Mg, Mn, Fe(II), Co, Cu, Zn, and Cd), a buffer layer containing a nitride of In and a Group III element except for In is formed, and a Group III nitride crystal is formed on the buffer layer.

Abstract: A hard mask layer is deposited on a feature layer over a substrate. The hard mask layer comprises an organic mask layer. An opening in the organic mask layer is formed using a first gas comprising a halogen element at a first temperature greater than a room temperature to expose a portion of the feature layer. In one embodiment, a gas comprising a halogen element is supplied to a chamber. An organic mask layer on an insulating layer over a substrate is etched using the halogen element at a first temperature to form an opening to expose a portion of the insulating layer.

Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

Abstract: The method for producing an organic EL display panel includes, in the given order, the steps of: forming a first light-emitting layer by forming a film from a luminescent material of a first luminescent color in a first pixel; performing the etching treatment to remove, while leaving the first light-emitting layer to remain, a thin film of the luminescent material of the first luminescent color which adhered to the second pixel in the step; forming a second light-emitting layer by forming a film from a luminescent material of a second luminescent color different from the first luminescent color in the second pixel; and performing the etching treatment to remove, while leaving the second light-emitting layer to remain, a thin film of the luminescent material of the second luminescent color which adhered to the first pixel in the step.

Abstract: An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.

Abstract: A method for selectively etching SiO and SiN with respect to SiGe or Si of a structure is provided. A plurality of cycles of atomic layer etching is provided, where each cycle comprises a fluorinated polymer deposition phase and an activation phase. The fluorinated polymer deposition phase comprises flowing a fluorinated polymer deposition gas comprising a fluorocarbon gas, forming the fluorinated polymer deposition gas into a plasma, which deposits a fluorocarbon polymer layer on the structure, and stopping the flow of the fluorinated polymer deposition gas. The activation phase comprises flowing an activation gas comprising an inert bombardment gas and H2, forming the activation gas into a plasma, wherein the inert bombardment gas activates fluorine in the fluorinated polymer which with the plasma components from H2 cause SiO and SiN to be selectively etched with respect to SiGe and Si, and stopping the flow of the activation gas.

Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.

Abstract: High-chi diblock copolymers are disclosed whose self-assembly properties are suitable for forming hole and bar openings for conductive interconnects in a multi-layered structure. The hole and bar openings have reduced critical dimension, improved uniformity, and improved placement error compared to the industry standard poly(styrene)-b-poly(methyl methacrylate) block copolymer (PS-b-PMMA). The BCPs comprise a poly(styrene) block, which can optionally include repeat units derived from trimethylsilyl styrene, and a second block that can be a polycarbonate block or a polyester block. Block copolymers comprising a fluorinated linking group L? comprising 1-25 fluorines between the blocks can provide further improvement in uniformity of the openings.

Abstract: Embodiments are directed to a method of forming a dielectric region of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric region adjacent a lower portion of the at least one fin, wherein the dielectric region includes a top surface. The method further includes forming a blocking layer on the top surface of the dielectric region, wherein the blocking layer is configured to prevent at least one subsequent FinFET fabrication operation from impacting the top surface of the dielectric region.

Abstract: According to one embodiment, a pattern forming method includes forming a resist pattern on an under-layer, forming a recessed portion in the under-layer by etching the under-layer using the resist pattern as a mask, slimming the resist pattern, forming a neutral layer having an affinity for first and second polymers on a region of the under-layer not covered with the slimmed resist pattern, forming a block copolymer film containing the first polymer and the second polymer on the slimmed resist pattern and the neutral layer, and forming a microphase separation pattern comprising a first portion formed of the first polymer and a second portion formed of the second polymer by applying microphase separation processing to the block copolymer film.

Abstract: Provided is a method of forming a semiconductor device. The method includes providing a substrate; depositing a flowable dielectric material layer over the substrate; performing a wet annealing process and a dry annealing process to the flowable dielectric material layer. The wet annealing process includes a first portion followed by a second portion. The second portion is performed at a temperature above 850 degrees Celsius, and the first portion is performed at a temperature lower than that of the second portion and is performed for longer duration than the second portion. The dry annealing process is performed at a temperature at least 500 degrees Celsius.

Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.