Abstract: Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods. A method for making an SSL device substrate in accordance with one embodiment of the disclosure includes forming multiple crystals carried by a support member, with the crystals having an orientation selected to facilitate formation of gallium nitride. The method can further include forming a volume of gallium nitride carried by the crystals, with the selected orientation of the crystals at least partially controlling a crystal orientation of the gallium nitride, and without bonding the gallium nitride, as a unit, to the support member. In other embodiments, the number of crystals can be increased by a process that includes annealing a region in which the crystals are present, etching the region to remove crystals having an orientation other than the selected orientation, and/or growing the crystals having the selected orientation.

Abstract: Disclosed herein is a semiconductor device including a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and a vertical portion that is substantially perpendicular to the substrate. Further, disclosed herein, are methods associated with the fabrication of the aforementioned semiconductor device.

Abstract: A method for fabricating a patterned structure in a semiconductor device is provided. First, a substrate with a first region and a second region is provided. Then, a plurality of sacrificial patterns is respectively formed within the first region and the second region. A first spacer is then formed on the sidewalls of each of the sacrificial patterns followed by forming a mask layer to cover the sacrificial patterns located within the first region. Finally, the first spacer exposed from the mask layer is trimmed to be a second spacer and the mask layer is then removed.

Abstract: A method for forming a semiconductor gate structure and a semiconductor gate structure are provided. The method includes: providing a substrate with a Ge layer as a surface thereof; forming a Sn layer on the Ge layer, in which an interface between the Ge layer and the Sn layer is a GeSn layer; removing the Sn layer to expose the GeSn layer; forming a GeSnOx passivation layer by performing an oxidation treatment for the GeSn layer, or forming a GeSnN or GeSnON passivation layer by performing a passivation treatment for the GeSn layer; and forming a gate stack on the GeSnOx , GeSnN or GeSnON passivation layer.

Abstract: A self-healing crack stop structure and methods of manufacture are disclosed herein. The structure comprises a crack stop structure formed in one or more dielectric layers and surrounding an active region of an integrated circuit chip. The crack stop comprises self healing material which, upon propagation of a crack, is structured to seal the crack and prevent further propagation of the crack.

Abstract: A method including forming a line pattern in a substrate includes using a plurality of longitudinally spaced projecting features formed along respective guide lines as a template in forming a plurality of directed self-assembled (DSA) lines that individually comprise at least one of (a): the spaced projecting features and DSA material longitudinally there-between, and (b): are laterally between and laterally spaced from immediately adjacent of the guide lines. Substrate material elevationally inward of and laterally between the DSA lines may be processed using the DSA lines as a mask.

Abstract: A method of forming a fine pattern of a semiconductor device using double SPT process, which is capable of implementing a line and space pattern having a uniform fine line width by applying a double SPT process including a negative SPT process, is provided. The method includes a first SPT process and a second SPT process and the second SPT process includes a Negative SPT process.

Abstract: An object is to provide a compound semiconductor substrate and a surface-treatment method thereof, in which, even after the treated substrate is stored for a long period of time, resistance-value defects do not occur. Even when the compound semiconductor substrate is stored for a long period of time and an epitaxial film is then formed thereon, electrical-characteristic defects do not occur. The semiconductor substrate according to the present invention is a compound semiconductor substrate at least one major surface of which is mirror-polished, the mirror-polished surface being covered with an organic substance containing hydrogen (H), carbon (C), and oxygen (O) and alternatively a compound semiconductor substrate at least one major surface of which is mirror-finished, wherein a silicon (Si) peak concentration at an interface between an epitaxial film grown at a growth temperature of 550° C. and the compound semiconductor substrate is 2×1017 cm?3 or less.

Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.

Abstract: An etch mask is formed on a substrate. The substrate is positioned in an enclosure configured to shield an interior of the enclosure from electromagnetic fields exterior to the enclosure; and the substrate is etched in the enclosure, including removing a portion of the substrate to form a structure having at least a portion that is isolated and/or suspended over the substrate.

Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate including a GeOx layer formed thereon having a first thickness, removing a portion of the GeOx layer by exposing the semiconductor substrate to a NF3/NH3 plasma dry etch so as to reduce the first thickness of the GeOx layer to a second thickness, and depositing a high-k material over the GeOx layer of the semiconductor substrate.

Abstract: A method for flowable oxide deposition is provided. An oxygen source gas is increased as a function of time or film depth to change the flowable oxide properties such that the deposited film is optimized for gap fill near a substrate surface where high aspect ratio shapes are present. The oxygen gas flow rate increases as the film depth increases, such that the deposited film is optimized for planarization quality at the upper regions of the deposited film.

Abstract: Embodiments of the present invention generally relate to methods for lowering the dielectric constant of low-k dielectric films used in semiconductor fabrication. In one embodiment, a method for lowering the dielectric constant (k) of a low-k silicon-containing dielectric film, comprising exposing a porous low-k silicon-containing dielectric film to a hydrofluoric acid solution and subsequently exposing the low-k silicon-containing dielectric film to a silylation agent. The silylation agent reacts with Si—OH functional groups in the porous low-k dielectric film to increase the concentration of carbon in the low-k dielectric film.

Abstract: A method of making a nanoparticle array that includes replicating a dimension of a self-assembled film into a dielectric film, to form a porous dielectric film, conformally depositing a material over the said porous dielectric film, and anisotropically and selectively etching the deposited material.

Abstract: A method for producing an optical semiconductor device includes the steps of determining a wafer size to make a section arrangement including a plurality of sections in each of which the optical semiconductor device including a semiconductor mesa is formed; obtaining an in-plane distribution of a thickness of a resin layer on a wafer; obtaining a correlation between a thickness of a resin layer and a trench width; forming a trench width map using the in-plane distribution of the thickness and the correlation; preparing an epitaxial substrate by forming a stacked semiconductor layer; forming, on the epitaxial substrate, a mask based on the trench width map; forming a trench structure including the semiconductor mesa by etching the stacked semiconductor layer using the mask; forming a resin layer on the trench structure; and forming an opening on the semiconductor mesa by etching the resin layer.

Abstract: A multi-patterning method includes: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask. The second circuit pattern is located between and excluded from the pattern free regions adjacent the at least two first circuit patterns.

Abstract: A method for creating one or more vias in an integrated circuit structure and the integrated circuit structure. The method includes depositing a coating layer over a hard mask layer on the integrated circuit structure; locating an initial via pattern layer over the coating layer; and etching the pattern of the one or more initial openings in the coating layer and through openings in the hard mask layer. The coating layer is a conformal deposition of an oxide, a boron nitride, or other nitride. The initial via pattern layer has one or more initial openings located therein.

Abstract: A method for patterning a substrate is described. The patterning method may include conformally depositing a material layer over a pattern according to a conformal deposition process, selectively depositing a second material layer on an exposed surface of the material layer according to a selected deposition process recipe; partially removing the material layer using a plasma etching process to expose a top surface of the pattern, open a portion of the material layer at a bottom region between adjacent features of the pattern, and retain a remaining portion of the material layer on sidewalls of the pattern; and removing the pattern using one or more etching processes to leave a final pattern comprising the remaining portion of the material layer and the second layer.

Abstract: Polymerized material on a substrate may be removed by exposure to vacuum ultraviolet (VUV) radiation from an energy source within a gaseous atmosphere of a controlled composition. Following such removal, additional etching techniques are also described for nano-imprinting.

Abstract: An interlayer structure that, in one implementation, includes a combination of an amorphous or nano-crystalline seed-layer, and one or more metallic layers, deposited on the seed layer, with the fcc, hcp or bcc crystal structure is used to epitaxially orient a semiconductor layer on top of non-single-crystal substrates. In some implementations, this interlayer structure is used to establish epitaxial growth of multiple semiconductor layers, combinations of semiconductor and oxide layers, combinations of semiconductor and metal layers and combination of semiconductor, oxide and metal layers. This interlayer structure can also be used for epitaxial growth of p-type and n-type semiconductors in photovoltaic cells.

Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.

Abstract: Embodiments of methods for removing carbon-containing films are provided herein. In some embodiments, a method for removing a carbon-containing layer includes providing an ammonia containing process gas to a process chamber having a substrate with a silicon oxide layer disposed atop the substrate and a carbon-containing layer disposed atop the silicon oxide layer disposed in the process chamber; providing RF power to the process chamber to ignite the ammonia containing process gas to form a plasma; and exposing the substrate to NH and/or NH2 radicals and hydrogen radicals formed in the plasma to remove the carbon-containing layer.

Abstract: In a semiconductor device having an insulating layer structure and method of manufacturing the same, a substrate including a first region and a second region may be provided. A first pattern structure may be formed on the first region of the substrate. A second pattern structure may be formed on the second region of the substrate, and have a height that is greater than the height of the first pattern structure. An insulating layer structure is formed on the first and second pattern structures and includes a protrusion near an area at which the first and second regions meet each other. An upper surface of the insulating interlayer structure is higher than a top surface of the second pattern structure. The protrusion may have at least one side surface having a staircase shape. A planarized insulating interlayer may be formed without substantial damage to the infrastructure by using the insulating layer structure in accordance with example embodiments.

Abstract: Block copolymers can be self-assembled and used in methods as described herein for sub-lithographic patterning, for example. The block copolymers can be diblock copolymers, triblock copolymers, multiblock copolymers, or combinations thereof. Such methods can be useful for making devices that include, for example, sub-lithographic conductive lines.

Abstract: Various embodiments provide double patterning methods and structures. In an exemplary method, a to-be-etched layer can be provided. A stress layer can be formed on the to-be-etched layer. The stress layer can have a tensile stress. A plurality of discrete sacrificial layers can be formed on the stress layer. A sidewall-spacer material layer covering the plurality of sacrificial layers and the stress layer can be formed. The sidewall-spacer material layer can be etched to form a sidewall spacer on a sidewall of each sacrificial layer of the plurality of sacrificial layers. The stress layer at each side of the each sacrificial layer can be etched to form a groove passing through a thickness of the stress layer. The plurality of sacrificial layers can be removed.

Abstract: A manufacturing method of substrate structure is provided. A base material having a core layer, a first patterned copper layer, a second patterned copper layer and at least one conductive via is provided. The first and second patterned copper layers are respectively located on a first surface and a second surface of the core layer. The conductive via passes through the core layer and connects the first and second patterned copper layers. A first and a second solder mask layers are respectively formed on the first and second surfaces. Portions of the first and second patterned copper layers are exposed by the first and second solder mask layers, respectively. A first gold layer is formed on the first and second patterned copper layers exposed by the first and second solder mask layers. A nickel layer and a second gold layer are successively formed on the first gold layer.

Abstract: During formation of a charge trap separation in a semiconductor device, a polymer deposition is formed in a reactor using a first chemistry. In a following step, a second chemistry can be used to etch the polymer deposition in the reactor. The same or similar second chemistry can be used in a second etching step to expose a first oxide layer in each of the cells of the semiconductor device and to form a flat upper surface. This additional etch step can also be performed by the reactor, thereby reducing the number of machines required in the formation process.

Abstract: The present invention relates to novel, soluble, multi-ligand-substituted metal oxide compounds to form metal oxide films with improved stability as well as compositions made from them and methods of their use. Specifically, the invention pertains to a compounds having the following structure (I): wherein M is a metal and n is 1 to 20, and wherein at least one of R1, R2, R3, and R4 is i) and at least at least one of R1, R2, R3, and R4 is ii), where i) is a silicon bearing organic moiety having at least 2 carbons, and ii) is an organic moiety. The invention also relates to spin-coatable composition of compounds of structure (I) dissolved into a solvent. The present invention further relates to processes using this spin coatable composition to form a coating on a patterned substrate.

Abstract: Productivity can be improved. A substrate processing method includes a processing liquid supplying process of supplying a processing liquid, which contains a volatile component and forms a film on a substrate, onto the substrate on which a pre-treatment, which requires atmosphere management or time management after the pre-treatment, is performed; and an accommodating process of accommodating, in a transfer container, the substrate on which the processing liquid is solidified or cured by volatilization of the volatile component.

Abstract: A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.

Abstract: A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.

Abstract: A substrate processing method includes supplying onto a substrate a processing liquid which contains a volatile component and forms a film, vaporizing the volatile component in the processing liquid such that the processing liquid solidifies or cures on the substrate and forms a film on the substrate, and supplying onto the film formed on the substrate a removing liquid which removes the processing liquid. The processing liquid is supplied onto the substrate after dry etching or ashing is applied to the substrate.

Abstract: Provided is a substrate processing apparatus, including: a first gas supply system to supply raw material gas of a film being deposited in at least a portion of the surface of the substrate, and first etching gas which removes the deposited film, from a first gas supply nozzle to the processing chamber; a second gas supply system to supply second etching gas, which removes the deposited film, from a second gas supply nozzle to the processing chamber; and a control device to control the first and second gas supply systems such that the raw material gas is supplied from the first gas supply nozzle and the second etching gas is supplied from the second gas supply nozzle while the substrate is in the processing chamber, and the first etching gas is supplied from the first gas supply nozzle while the substrate is not in the processing chamber.

Abstract: Provided are: a resin mold material and a resin replica mold material composition for imprinting having a superior mold releasability; a resin mold and a resin replica mold resulting from containing the material composition; and a method for producing them. The resin mold material or resin replica mold material composition for imprinting contains 100 parts by weight of a mold resin or replica mold resin for imprinting and 0.1 to 10 parts by weight of a curable fluoropolymer (A). Preferably, the fluoropolymer (A) has a weight-average molecular weight of 3,000 to 20,000 and results from including as repeating units (a1) an ?-position substituted acrylate having a fluoroalkyl group having 4 to 6 carbon atoms and (a2) and 5 to 120 parts by weight of a high-softening-point monomer exhibiting a glass transition point or softening point of at least 50° C. in the homopolymer state.

Abstract: A semiconductor process including the following steps is provided. A substrate is provided. A nitride layer is formed on the substrate, but exposing a silicon containing area. An oxidation process is performed to oxidize a surface of the silicon containing area to form an oxidized surface. The nitride layer is removed.

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of discrete storage elements within a memory cell. A copolymer solution comprising first and second polymer species is spin-coated onto a surface of a substrate and subjected to self-assembly into a phase-separated material comprising a regular pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The second polymer species is then removed resulting with a pattern of holes within the polymer matrix. An etch is then performed through the holes utilizing the polymer matrix as a hard-mask to form a substantially identical pattern of holes in a dielectric layer disposed over a seed layer disposed over the substrate surface. Epitaxial deposition onto the seed layer then utilized to grow a substantially uniform pattern of discrete storage elements within the dielectric layer.

Abstract: Provided is a method of etching a silicon oxide film. The method includes exposing a workpiece including the silicon oxide film and a mask formed on the silicon oxide film to plasma of a processing gas to etch the silicon oxide film. The mask includes a first film formed on the silicon oxide film and a second film formed on the first film, and the second film is constituted by a film having an etching rate lower than that of the first film with respect to active species in the plasma.

Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.

Abstract: A method for ameliorating corner rounding effects in a photolithographic process is provided. A semiconductor workpiece having an active device region is provided, and a photoresist layer is formed over the semiconductor workpiece. A mask is provided for patterning for the photoresist layer, wherein the mask comprises pattern having a sharp corner associated with the active device region. The sharp corner is separated from the active device region by a first distance in a first direction and a second distance in a second direction, wherein the first distance meets a minimum criteria for the photolithographic process, and wherein the second distance is greater than the first distance. The photoresist layer is then exposed to a radiation source, and the radiation source patterns the photoresist layer through the mask, defining an exposure region on the semiconductor workpiece having a rounded corner associated with the sharp corner.

Abstract: Devices and method based on disclosed technology include, among others, a method for capable of providing asymmetrical arrangement of hole patterns while improving non-uniformity of an electronic device. Specifically, a method for fabricating hole patterns in one implementation includes forming a mask pattern which is defined with hole patterns of an asymmetrical arrangement with different longitudinal and transverse intervals, over a layer to be etched; and etching the layer to be etched, using the mask pattern as an etch barrier.

Abstract: According to one embodiment, a method of manufacturing a magnetoresistive element, the method includes forming a first non-magnetic layer on a first magnetic layer, forming a second magnetic layer on the first non-magnetic layer, forming a second non-magnetic layer on the second magnetic layer, forming a third magnetic layer on the second non-magnetic layer, patterning the third magnetic layer by a RIE using an etching gas including a noble gas and a nitrogen gas until a surface of the second non-magnetic layer is exposed, and patterning the second non-magnetic layer and the second magnetic layer after patterning of the third magnetic layer.

Abstract: The present invention provides a semiconductor device production method and a rinse used in the production method. The method includes: a sealing composition application process in which a semiconductor sealing layer is formed by applying, to at least a portion of a surface of a semiconductor substrate, a semiconductor sealing composition that includes a resin having a cationic functional group and a weight average molecular weight of from 2,000 to 600,000, wherein a content of sodium and a content of potassium are 10 mass ppb or less on an elemental basis, respectively; and, subsequently, a rinsing process in which the surface of the semiconductor substrate on which the semiconductor sealing layer has been formed is rinsed with a rinse having a pH at 25° C. of 6 or lower.

Abstract: The present invention relates to a method for acidic surface etching of a silicon wafer, such as those used for solar cells, comprising contacting at least one surface of a silicon wafer as cut with an acidic etching agent, provided that the wafer is, prior to the acidic etching, not subjected to an alkaline etching step or process. Further, the present invention is directed to Si wafer, photovoltaic cells, PERC photovoltaic cells and solar modules produced according to the method of the present invention.

Abstract: A method of forming a silicon containing confinement ring for a plasma processing apparatus useful for processing a semiconductor substrate comprises inserting silicon containing vanes into grooves formed in a grooved surface of an annular carbon template wherein the grooved surface of the annular carbon template includes an upwardly projecting step at an inner perimeter thereof wherein each groove extends from the inner perimeter to an outer perimeter of the grooved surface. The step of the grooved surface and a projection at an end of each silicon containing vane is surrounded with an annular carbon member wherein the annular carbon member covers an upper surface of each silicon containing vane in each respective groove. Silicon containing material is deposited on the annular carbon template, the annular carbon member, and exposed portions of each silicon containing vane thereby forming a silicon containing shell of a predetermined thickness.

Abstract: The invention provides a composition for forming a silicon-containing resist underlayer film comprising: (A) a silicon-containing compound obtained by a hydrolysis-condensation reaction of a mixture containing, at least, one or more hydrolysable silicon compound shown by the following general formula (1) and one or more hydrolysable compound shown by the following general formula (2), and (B) a silicon-containing compound obtained by a hydrolysis-condensation reaction of a mixture containing, at least, one or more hydrolysable silicon compound shown by the following general formula (3) and one or more hydrolysable silicon compound shown by the following general formula (4).

Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Abstract: A method for etching features into an etch layer in a stack disposed below a patterned mask with mask features is provided. Coating providing molecules are provided. The coating providing molecules are pyrolyzed, which only produces a first set of byproducts and a second set of byproducts, wherein the first set of byproducts have a sticking coefficient between 10?6 to 5×10?3 and wherein the second set of byproducts includes all remaining byproducts from the pyrolysis wherein all remaining byproducts from the pyrolysis have sticking coefficients less than 10?6. The stack is exposed to the first set of byproducts, causing the first set of byproducts to deposit a coating. The etch layer is etched.

Abstract: A method of making a structure includes forming a first supporting member over a substrate, the first supporting member comprising a first material and having a first width defined along a reference plane. The method further includes forming a second supporting member over the substrate, the second supporting member having a second width defined along the reference plane, and the first supporting member and the second supporting member being separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region being from 5 to 30 times the second width.

Abstract: Methods of forming contact holes include forming a first guide pattern over an etching target layer. The first guide pattern has first openings each extending in a first direction and each first opening arranged in a direction perpendicular to the first direction. A first BCP structure is formed in each first opening. The first BCP structure includes first material layers in the first direction at a first pitch in each of the first openings, and second material layers filling a remaining portion of each first opening. First holes are formed by removing the first material layers. A second guide pattern is formed over the first guide pattern and the second material layers, and the above processes are performed on the second guide pattern to form second holes. Portions of the etching target layer overlapped by the first holes or the second holes are removed to form a desired pattern.

Abstract: According to one embodiment, first, a core pattern is formed above a hard mask layer that is formed above a process object. Then, a spacer film is formed above the hard mask layer. Next, the spacer film is etch-backed. Subsequently, an embedded layer is embedded between the core patterns whose peripheral areas are surrounded by the spacer film. Then, the core pattern and the embedded layer are removed simultaneously. Subsequently, using the spacer pattern as a mask, the hard mask layer and the process object are processed.