Abstract: In a semiconductor device manufacturing method, a target object including a multilayer film and a mask formed on the multilayer film is prepared in a processing chamber of a plasma processing apparatus. The multilayer film is formed by alternately stacking a silicon oxide film and a silicon nitride film. The multilayer film is etched by supplying a processing gas containing hydrogen gas, hydrogen bromide gas, nitrogen trifluoride gas and at least one of hydrocarbon gas, fluorohydrocarbon gas and fluorocarbon gas into the processing chamber of the plasma processing apparatus and generating a plasma of the processing gas in the processing chamber.

Abstract: A method for forming a fine pattern includes forming an etching target material layer on a substrate, forming a first photoresist layer on the etching target material layer, forming a metal pattern on the first photoresist layer, the metal pattern having a plurality of lines and thin film lines alternately arranged, the lines having predetermined linewidth and thickness and are spaced apart from each other by a predetermined distance, exciting surface plasmons in the metal pattern by light irradiation to produce a surface plasmon resonance that exposes a fine first pattern shape in the first photoresist layer, forming a first photoresist pattern by removing the metal pattern and developing the first photoresist layer, and etching the etching target material layer by using the first photoresist pattern as a mask.

Abstract: A gas comprising hydrogen is supplied to a plasma source. Plasma comprising hydrogen plasma particles is generated from the gas. A passivation layer is deposited on a first mask layer on a second mask layer over a substrate using the hydrogen plasma particles.

Abstract: An embodiment includes a substrate, wherein a portion of the substrate extends upwards forming a fin, a gate dielectric over a top surface and at least portions of sidewalls of the fin, a gate electrode over the gate dielectric, and a contact over and extending into the gate electrode, wherein the contact has a first width above the gate electrode and a second width within the gate electrode, the first width being smaller than the second width.

Abstract: A wafer processing method divides a wafer into individual devices along crossing streets formed on the front side of the wafer. The wafer has a substrate and a functional layer formed on the front side of the substrate. The individual devices are formed from the functional layer and are partitioned by the streets. A laser beam is applied along the streets from the front side of the functional layer to thereby remove the functional layer along the streets. A resist film is formed on the front side of the functional layer except on each street. The substrate of the wafer is plasma-etched along each street where the functional layer is absent to the depth corresponding to the finished thickness of each device, thereby forming a division groove along each street and also etching off a modified layer formed on the opposite sides of each street.

Abstract: The present invention provides, in a plasma etching method for plasma-etching a magnetic film, a plasma etching method that allows a desired etching depth to be obtained regardless of the opening size of a mask. The present invention is, in a plasma etching method for plasma-etching a magnetic film by using a tantalum film as a mask, characterized by including: a first process to plasma-etch the magnetic film to a desired depth by using a mixed gas of an ammonia gas and a helium gas; and a second process, after the first process, to plasma-etch the magnetic film etched to the prescribed depth by using a mixed gas of an ammonia gas and a gas containing the oxygen element or a mixed gas of an ammonia gas and a gas containing a hydroxyl group.

Abstract: There is provided a pattern forming method, including: forming an organic film layer on a substrate; forming a patterned photoresist mask on the organic film layer; and performing a specific dry etching process to form a pattern on the organic layer.

Abstract: In at least one embodiment, a method of forming a platinum thin film is provided, including performing a first atomic layer deposition (ALD) process on a substrate using a first platinum organometallic precursor in a first step and an oxidizing precursor in a second step to form an at least partially coated substrate. A second ALD process is then performed on the at least partially coated substrate using a second platinum organometallic precursor in a first step and a reducing precursor in a second step to form a thin film of platinum on the substrate. The first ALD process may be performed for 5 to 150 cycles to nucleate platinum on the substrate surface and the second ALD process may be performed thereafter to grow the thin film and remove surface oxides. A conformal platinum thin film having a thickness of 1 to 10 monolayers may be deposited.

Abstract: Systems and methods for forming precise and self-aligned top metal contact for a Magnetoresistive random-access memory (MRAM) device include forming a magnetic tunnel junction (MTJ) in a common interlayer metal dielectric (IMD) layer with a logic element. A low dielectric constant (K) etch stop layer is selectively retained over an exposed top surface of the MTJ. Etching is selectively performed through a top IMD layer formed over the low K etch stop layer and the common IMD layer, based on a first chemistry which prevents etching through the low K etch stop layer. By switching chemistry to a second chemistry which precisely etches through the low K etch stop layer, an opening is created for forming a self-aligned top contact to the exposed top surface of the MTJ.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is exposed to a plasma treatment process to increase an etch resistance of the mask. The mask is patterned with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to exposing the mask to the plasma treatment process, the semiconductor wafer is plasma etched through the gaps in the mask to singulate the integrated circuits.

Abstract: In a method for etching an organic film according to an embodiment, a target object that has an organic film is set in a processing chamber. Then, a processing gas containing COS gas and O2 gas is supplied to the processing chamber and a microwave for plasma excitation is supplied to the inside of the processing chamber to etch the organic film.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a silicon nitride layer on a metal layer, forming a plasma of a gas mixture of carbon oxide and oxygen, and selectively etching the silicon nitride layer with respect to the metal layer by using the plasma of the gas mixture.

Abstract: In a plasma processing method for plasma-etching magnetic layer by using a plasma processing device including a processing chamber in which a sample is plasma-processed, a dielectric window to seal an upper part of the processing chamber hermetically, an inductive coupling antenna disposed above the dielectric window, a radio-frequency power source to supply radio-frequency electric power to the inductive coupling antenna and a Faraday shield disposed between the inductive coupling antenna and the dielectric window, a deposit layer is formed on the plasma-etched magnetic layer by plasma processing while applying radio-frequency voltage to the Faraday shield after the magnetic layer is plasma-etched.

Abstract: An etching method and apparatus for etching a silicon oxide film selectively with respect to a silicon nitride film formed on a substrate are provided. A processing gas containing a plasma excitation gas and a CHF-based gas is introduced into a processing chamber such that a flow rate ratio of the CHF-based gas to the plasma excitation gas is 1/15 or higher. By generating a plasma in the processing chamber, the silicon oxide film is etched selectively with respect to the silicon nitride film formed on the substrate in the processing chamber.

Abstract: This invention involves structure and fabrication method of a black silicon-based MEMS thermopile IR detector. The high-performance black silicon-based MEMS thermopile IR detector includes a substrate; a releasing barrier band on the substrate; a thermal isolation cavity constructed by the releasing barrier band; a black silicon-based IR absorber located right above the thermal isolation cavity; a number of thermocouples are set around the lateral sides of the black silicon-based IR absorber. The thermopiles around the black silicon-based IR absorber are electrically connected in series thus to form a thermopile. Metallic electrodes are located beside the electrically-connected thermopiles for signal output. The cold junctions of the thermopile are connected to the substrate through the first thermal-conductive-electrical-isolated structures, the heat conductor is located at the lateral sides of the thermal isolation cavity.

Abstract: Disclosed herein are various methods of forming a replacement gate structure with a gate electrode comprised of a deposited intermetallic compound material. In one example, the method includes removing at least a sacrificial gate electrode structure to define a gate cavity, forming a gate insulation layer in the gate cavity, performing a deposition process to deposit an intermetallic compound material in the gate cavity above the gate insulation layer, and performing at least one process operation to remove portions of intermetallic compound material positioned outside of the gate cavity.

Abstract: Various embodiments are provided for dilute source enabled vertical organic light emitting transistors. In various embodiments, a display panel includes an array of pixels. In one embodiment, among others, at least one pixel includes a switching transistor and a driving transistor coupled to the switching transistor, where the driving transistor is configured to emit light responsive to activation by the switching transistor. The driving transistor may be a dilute source enabled vertical organic light emitting transistor (DS-VOLET). The switching transistor may include a dilute source enabled vertical-field effect transistor (DS-VFET). In another embodiment, a double dilute source enabled vertical-field effect transistor (DS-VFET) includes a first DS-VFET coupled to a second DS-VFET.

Abstract: A method of forming a pattern on a silicon layer of a substrate, to be processed, wherein a semiconductor device is formed at a front surface side of the substrate that is supported by a support substrate at the front surface side, includes an etching step of etching the substrate by plasma via a mask having a predetermined pattern formed at a back surface side of the silicon layer of the substrate; and a cleaning step of cleaning the substrate by plasma using cleaning gas obtained by mixing CF series gas and inert-gas, after the etching step.

Abstract: There is disclosed a method for forming a TiSiN thin film on a substrate according to ALD including a first process of preheating a substrate while supplying Ar or N2 containing inert gas to a chamber, after disposing a substrate in a chamber; a second process of forming a TiN film on the substrate by repeating at least one time a process of purging over-supplied Ti containing gas after supplying Ti containing gas and inert gas after that and a process of purging residual product after supplying N containing gas and inert gas after that; a third process of forming a SiN film by repeating at least one time a process of purging over-supplied Si containing gas after supplying Si containing gas on the TiN film and supplying inert gas after that and a process of purging residual product after supplying N containing gas and supplying inert gas after that; and a fourth process of forming a TiSiN film having a desired thickness by repeating the second and third processes at least one time, a partial pressure range of

Abstract: A plasma etching method deposits a silicon-containing deposit by a plasma processing using a Si-containing gas on an object to be processed that includes a film to be processed, an organic film formed in a plurality of narrow linear portions on the film to be processed, and a rigid film that covers both the film to be processed which is exposed between the linear portions and the linear portions. In the plasma etching method, each of the plurality of narrow linear portions of the organic film and the film to be processed between the linear portions are exposed by etching the silicon-containing deposit by plasma of CF-based gas and CHF-based gas after the silicon-containing deposit is deposited.

Abstract: The invention involves structure and fabrication method of a high performance IR detector. The structure comprises a substrate; a releasing barrier band on the substrate; a thermal isolation chamber constructed by the releasing barrier band; a black silicon-based IR absorber located right above the thermal isolation chamber and the black silicon-based IR absorber is set on the releasing barrier band; a number of thermocouples are set around the lateral sides of the black silicon-based IR absorber. The thermopiles around the black silicon-based IR absorber are electrically connected in series. The cold junctions of the thermopile are connected to the substrate through the first thermal-conductive-electrical-isolated structures as well as the heat conductor under the first thermal-conductive-electrical-isolated structures.

Abstract: The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit wherein the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.

Abstract: A method of etching silicon oxide from a trench is described which allows more homogeneous etch rates up and down the sides of the trench. One disclosed method includes a sequential introduction of (1) a hydrogen-containing precursor and then (2) a fluorine-containing precursor into a substrate processing region. The temperature of the substrate is low during each of the two steps in order to allow the reaction to proceed and form solid residue by-product. A second disclosed method reverses the order of steps (1) and (2) but still forms solid residue by-product. The solid residue by-product is removed by raising the temperature in a subsequent sublimation step regardless of the order of the two steps.

Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.

Abstract: A method for etching features into an etch layer through a patterned mask in a plasma processing chamber is provided. A main etch gas is flowed into the plasma processing chamber. The main etch gas is formed into a main etch plasma. A bias greater than 600 volts is provided. The bias is pulsed at a frequency between 1 Hz and 20 kHz with a duty cycle less than 45%.

Abstract: A semiconductor device having reduced leakage current and increased capacitance without increasing an equivalent oxide thickness (EOT) can be manufactured by a method that includes providing a substrate having a dummy gate pattern; forming a gate forming trench by removing the dummy gate pattern; forming a stacked insulation layer within the gate forming trench, wherein the forming of the stacked insulation layer includes forming a first high-k dielectric layer, forming a second high-k dielectric layer by performing heat treatment on the first high-k dielectric layer, and, after the heat treatment, forming a third high-k dielectric layer on the second high-k dielectric layer, the third high-k dielectric layer having a higher relative permittivity than the second high-k dielectric layer and having a dielectric constant of 40 or higher; and forming a gate electrode within the gate forming trench.

Abstract: A plasma etching method is provided for etching a substrate corresponding to an etching object within an etching apparatus that includes a supply condition adjustment unit for adjusting a supply condition for supplying etching gas to the substrate, a temperature adjustment unit for adjusting a temperature of the substrate placed on a stage along a radial direction, and a plasma generating unit for generating plasma within a space between the supply condition adjustment unit and the stage. The plasma etching method includes a control step in which the temperature adjustment unit controls the temperature of the substrate to be uniform within a substrate plane of the substrate, and an adjustment step in which the supply condition adjustment unit adjusts a concentration distribution of active species contained in the plasma generated by the plasma generation unit within the space above the substrate.

Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.

Abstract: A method for manufacturing a semiconductor device includes: forming a first active region, a second active region, an inactive region located between the first active region and the second active region, and a third active region, which crosses the inactive region to electrically connect the first active region to the second active region, in a semiconductor layer; forming an insulating layer on the semiconductor layer; and forming an opening selectively in the insulating layer by dry etching.

Abstract: A semiconductor device manufacturing method includes exciting a processing gas containing a HBr gas and a Cl2 gas within a processing chamber that accommodates a target object including a substrate, regions made of silicon, which are protruded from the substrate and arranged to form a gap, a metal layer formed to cover the regions, a polycrystalline silicon layer formed on the metal layer, and an organic mask formed on the polycrystalline silicon layer. The Cl2 gas is supplied at a flow rate of about 5% or more to about 10% or less with respect to a flow rate of the HBr gas in the processing gas.

Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials are provided. The method involves providing a partially fabricated semiconductor substrate and depositing a tungsten-containing layer on the substrate surface to partially fill one or more high aspect ratio features. The method continues with selective removal of a portion of the deposited layer such that more material is removed near the feature opening than inside the feature. In certain embodiments, removal may be performed at mass-transport limited conditions with less etchant available inside the feature than near its opening. Etchant species are activated before being introduced into the processing chamber and/or while inside the chamber. In specific embodiments, recombination of the activated species is substantially limited and/or controlled during removal, e.g., operation is performed at less than about 250° C. and/or less than about 5 Torr.

Abstract: A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF6 without forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.

Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch created from a remote plasma etch. The remote plasma excites a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor. Reactants thereby produced etch the patterned heterogeneous structures to remove two separate regions of differing silicon oxide at different etch rates. The methods may be used to remove low density silicon oxide while removing less high density silicon oxide.

Abstract: Methods of depositing a tin-containing layer on a substrate are disclosed herein. In some embodiments, a method of depositing a tin-containing layer on a substrate may include flowing a tin source comprising a tin halide into a reaction volume; flowing a hydrogen plasma into the reaction volume; forming one or more tin hydrides within the reaction volume from the tin source and the hydrogen plasma; and depositing the tin-containing layer on a first surface of the substrate using the one or more tin hydrides.

Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.

Abstract: Embodiments described herein generally relate to a substrate processing system and related methods, such as an etching/deposition method. The method comprises (A) depositing a protective layer on a first layer disposed on a substrate in an etch reactor, wherein a plasma source power of 4,500 Watts or greater is applied while depositing the protective layer, (B) etching the protective layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the protective layer, and (C) etching the first layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the first layer, wherein a time for the depositing a protective layer (A) comprises less than 30% of a total cycle time for the depositing a protective layer (A), the etching the protective layer (B), and the etching the first layer (C).

Abstract: A plasma etching method performs plasma etching on a sample, which has laminated films containing a variable layer of a magnetic film, a barrier layer of an insulating material, and a fixed layer of a magnetic film, using a hard mask, which includes at least one of a Ta film and a TiN film. The plasma etching method includes a first step of etching the laminated films using N2 gas; and a second step of etching the laminated films after the first step using mixed gas of N2 gas and gas containing carbon elements.

Abstract: A semiconductor device includes a substrate having a hexagonal crystalline structure and a (0001) surface, and conductive films on the surface of the substrate. The conductive films include a first conductive film and a second conductive film located above the first conductive film with respect to the surface, wherein the first conductive film has a crystalline structure which does not have a plane that has a symmetry equivalent to the symmetry of atomic arrangement in the surface of the substrate, the second conductive film has a crystalline structure having at least one plane that has a symmetry equivalent to the symmetry of atomic arrangement in the surface of the substrate, and the second conductive film is polycrystalline and has a grain size no larger than 15 ?m.

Abstract: A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.

Abstract: A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.

Abstract: A substrate processing method for processing a substrate by supplying a processing gas into a processing chamber and allowing the processing gas to react on the substrate in the processing chamber by using a substrate processing apparatus includes the processing chamber accommodating the substrate, a processing gas supply unit for supplying the processing gas into the processing chamber, and a gas exhaust unit, for exhausting the processing chamber, having a turbo molecular pump. The method controls a processing uniformity by controlling a revolution speed of the turbo molecular pump while maintaining a pressure in the processing chamber to a predetermined level when by-products having a larger molecular mass compared to the processing gas are generated by the reaction of the processing gas.

Abstract: Provided is a method of selectively etching a portion of silicon existing on a surface of a substrate to be processed, which includes: loading the substrate to be processed into a chamber; and supplying an FNO gas and an F2 gas that are diluted with an inert gas into the chamber such that the FNO gas and the F2 gas are reacted with the portion of silicon existing on the surface of the substrate to be processed.

Abstract: A method to prevent movable structures within a MEMS device, and more specifically, in recesses having one or more dimension in the micrometer range or smaller (i.e., smaller than about 10 microns) from being inadvertently bonded to non-moving structures during a bonding process. The method includes surface preparation of silicon both structurally and chemically to aid in preventing moving structures from bonding to adjacent surfaces during bonding, including during high force, high temperature fusion bonding.

Abstract: A structure includes a silicon layer disposed on a buried oxide layer that is disposed on a substrate; at least one transistor device formed on or in the silicon layer, the at least one transistor having metallization; a released region of the silicon layer disposed over a cavity in the buried oxide layer; a back end of line (BEOL) dielectric film stack overlying the silicon layer and the at least one transistor device; a nitride layer overlying the BEOL dielectric film stack; a hard mask formed as a layer of hafnium oxide overlying the nitride layer; and an opening made through the layer of hafnium oxide, the layer of nitride and the BEOL dielectric film stack to expose the released region of the silicon layer disposed over the cavity in the buried oxide layer. The hard mask protects the underlying material during a MEMS/NEMS HF vapor release procedure.

Abstract: A method of selectively etching silicon nitride from a substrate comprising a silicon nitride layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the silicon nitride layer at a higher etch rate than the reactive gas etches the silicon oxide layer.

Abstract: The present invention relates to methods of forming substrate elements, including semiconductor elements such as nanowires, transistors and other structures, as well as the elements formed by such methods.

Abstract: Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s). In certain embodiments, the selectively removing includes implanting the sidewall(s) with a dopant to produce a doped region(s) of the gate structure, and subsequently, at least partially removing the doped region(s) of the gate structure selective to an undoped region of the gate structure.

Abstract: A plasma processing method is used to etch a multilayered material having a stacked structure, in which a first magnetic layer, an insulating layer, a second magnetic layer, and a mask material are stacked in sequence, in a plasma processing apparatus including a processing chamber that partitions a processing space where plasma is generated and a gas supply unit that supplies a processing gas into the processing space. The plasma processing method includes a mask forming process of forming a mask on the second magnetic layer by etching the mask material; an etching process of supplying the processing gas into the processing chamber to generate plasma, etching the second magnetic layer by the mask, and stopping the etching on a surface of the insulating layer. Further, the second magnetic layer contains CoFeB, the insulating layer contains MgO, and the processing gas contains H2 and F or a fluorine compound.

Abstract: The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole.

Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated hydrogen species. The activated hydrogen species can be used to etch/clean semiconductor oxide surfaces such as silicon oxide or germanium oxide.