Abstract: Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating sensitive surfaces without unduly contaminating the same, while, in a second deposition process, a moderately high process temperature may be used to provide enhanced material characteristics and a reduced overall cycle time compared to conventional ALD or multi-layer deposition techniques.

Abstract: A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen.

Abstract: A silicon nitride film including stoichiometrically excessive silicon with respect to nitrogen is formed. The silicon nitride film may be formed by supplying dichlorosilane to a substrate under a condition where CVD (chemical vapor deposition) reaction is caused to form a silicon film including several or less atomic layers on the substrate, supplying ammonia to the substrate in a non-plasma atmosphere to thermally nitride the silicon film under a condition where the nitriding reaction of the silicon film by the ammonia is not saturated, and alternately repeating the supplying of dichlorosilane and the supplying of ammonia.

Abstract: A method of depositing a silicon and nitrogen containing film on a substrate. The method includes introducing silicon-containing precursor to a deposition chamber that contains the substrate, wherein the silicon-containing precursor comprises at least two silicon atoms. The method further includes generating at least one radical nitrogen precursor with a remote plasma system located outside the deposition chamber. Moreover, the method includes introducing the radical nitrogen precursor to the deposition chamber, wherein the radical nitrogen and silicon-containing precursors react and deposit the silicon and nitrogen containing film on the substrate. Furthermore, the method includes annealing the silicon and nitrogen containing film in a steam environment to form a silicon oxide film, wherein the steam environment includes water and acidic vapor.

Abstract: A silicon nitride thin film formation apparatus is provided for stationary and moving substrates and a process for forming such films. The process provides high uniformity of film thickness and film properties as well as a high deposition rate. The film properties are adequate for application as an antireflection layer or passivation layer in solar cell devices or as dielectric layer in thin film transistors. The apparatus includes a number of metal filaments. In the space within the formation apparatus opposite to the substrate with respect to the filaments, a gas dosage system is arranged at a predetermined distance of the filaments. The film formation apparatus for stationary substrates also contains a shutter to control the starting and ending conditions for film formation and to control the film thickness.

Abstract: There is provided a method for modifying a high-k dielectric thin film provided on the surface of an object using a metal organic compound material. The method includes a preparation process for providing the object with the high-k dielectric thin film formed on the surface thereof, and a modification process for applying UV rays to the highly dielectric thin film in an inert gas atmosphere while maintaining the object at a predetermined temperature to modify the high-k dielectric thin film. According to the above constitution, the carbon component can be eliminated from the high-k dielectric thin film, and the whole material can be thermally shrunk to improve the density, whereby the occurrence of defects can be prevented and the film density can be improved to enhance the specific permittivity and thus to provide a high level of electric properties.

Abstract: A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dieletric thickness of less than approximately 20 angstroms.

Abstract: A method of depositing a silicon and nitrogen containing film on a substrate. The method includes introducing silicon-containing precursor to a deposition chamber that contains the substrate, wherein the silicon-containing precursor comprises at least two silicon atoms. The method further includes generating at least one radical nitrogen precursor with a remote plasma system located outside the deposition chamber. Moreover, the method includes introducing the radical nitrogen precursor to the deposition chamber, wherein the radical nitrogen and silicon-containing precursors react and deposit the silicon and nitrogen containing film on the substrate. Furthermore, the method includes annealing the silicon and nitrogen containing film in a steam environment to form a silicon oxide film, wherein the steam environment includes water and acidic vapor.

Abstract: Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.

Abstract: A semiconductor device manufacturing method comprises a process of forming a film on each of multiple substrates arrayed in a processing chamber by a thermal CVD method by supplying a film forming gas into the processing chamber while heating the interior of the processing chamber, wherein in the film forming process, a cycle is performed one time or multiple times with one cycle including a step of flowing the film forming gas from one end towards the other end along the substrate array direction, and a step of flowing the film forming gas from the other end towards the one end along the substrate array direction, without forming temperature gradient along the substrate array direction in the processing chamber.

Abstract: A disclosed substrate processing method in a single wafer substrate processing device including a first process position for introducing nitrogen atoms to a high-dielectric film and a second process position for performing heat treatment on the high-dielectric film includes: successively conveying plural substrates to be processed to the first process position and the second process position one by one; and successively performing the introduction of nitrogen atoms and the heat treatment on the high-dielectric film on the substrates to be processed, wherein the treatment on the substrate to be processed is started within 30 seconds at the second process position after the process at the first position.

Abstract: A thin silicon-rich nitride film (e.g., having a thickness in the range of around 100A to 10000A) deposited using low-pressure chemical vapor deposition (LPCVD) is used for etch stop during vapor HF etching in various MEMS wafer fabrication processes and devices. The LPCVD silicon-rich nitride film may replace, or be used in combination with, a LPCVD stoichiometric nitride layer in many existing MEMS fabrication processes and devices. The LPCVD silicon-rich nitride film is deposited at high temperatures (e.g., typically around 650-900 degrees C.). Such a LPCVD silicon-rich nitride film generally has enhanced etch selectivity to vapor HF and other harsh chemical environments compared to stoichiometric silicon nitride and therefore a thinner layer typically can be used as an embedded etch stop layer in various MEMS wafer fabrication processes and devices and particularly for vapor HF etching processes, saving time and money in the fabrication process.

Abstract: A charge retention characteristic of a nonvolatile memory transistor is improved. A first insulating film that functions as a tunnel insulating film, a charge storage layer, and a second insulating film are sandwiched between a semiconductor substrate and a conductive film. The charge storage layer is formed of two silicon nitride films. A silicon nitride film which is a lower layer is formed using NH3 as a nitrogen source gas by a CVD method and contains a larger number of N—H bonds than the upper layer. A second silicon nitride film which is an upper layer is formed using N2 as a nitrogen source gas by a CVD method and contains a larger number of Si—H bonds than the lower layer.

Abstract: Disclosed is a method for using a film formation apparatus to form a silicon nitride film by CVD on target substrates while suppressing particle generation. The apparatus includes a process container and an exciting mechanism attached on the process container. The method includes conducting a pre-coating process by performing pre-cycles and conducting a film formation process by performing main cycles. Each of the pre-cycles and main cycles alternately includes a step of supplying a silicon source gas and a step of supplying a nitriding gas with steps of exhausting gas from inside the process container interposed therebetween. The pre-coating process includes no period of exciting the nitriding gas by the exciting mechanism. The film formation process repeats a first cycle set that excites the nitriding gas by the exciting mechanism and a second cycle that does not excite the nitriding gas by the exciting mechanism.

Abstract: A method for fabricating a semiconductor device, includes forming a porous dielectric film above a substrate using a porous insulating material, forming an opening in the porous dielectric film, repairing film quality of the porous dielectric film on a surface of the opening by feeding a predetermined gas replacing a Si—OH group to the opening, and performing pore sealing of the surface of the opening using the same predetermined gas as that used for film quality repairs after repairing the film quality.

Abstract: A fabrication method of a semiconductor device includes forming a silicon nitride layer on a compound semiconductor layer with a plasma CVD method and selectively treating the compound semiconductor layer with use of the silicon nitride layer for a mask. The silicon nitride layer has a refraction index of less than 1.85. The compound semiconductor layer includes Ga.

Abstract: Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide optimal performance versus stability (i.e., optimal drive current versus leakage current) for logic circuits, analog devices and/or memory devices. Also disclosed are embodiments of a method of forming the integrated circuit structure embodiments. These method embodiments incorporate the use of a cap layer pullback technique on select semiconductor bodies and subsequent wet etch process so as to avoid (or at least minimize) divot formation adjacent to some but not all semiconductor bodies.

Abstract: A MOSFET fabrication process comprises nitridation of the dielectric silicon interface so that silicon-dangling bonds are connected with nitrogen atoms creating silicon—nitrogen bonds, which are stronger than silicon-hydrogen bonds. A tunnel dielectric is formed on the substrate. A nitride layer is then formed over the tunnel dielectric layer. The top of the nitride layer is then converted to an oxide and the interface between the substrate and the tunnel dielectric is nitrided simultaneously with conversion of the nitride layer to oxide.

Abstract: A structure and a method of making the structure. The structure includes a field effect transistor including: a first and a second source/drain formed in a silicon substrate, the first and second source/drains spaced apart and separated by a channel region in the substrate; a gate dielectric on a top surface of the substrate over the channel region; and an electrically conductive gate on a top surface of the gate dielectric; and a dielectric pillar of a first dielectric material over the gate; and a dielectric layer of a second dielectric material over the first and second source/drains, sidewalls of the dielectric pillar in direct physical contact with the dielectric layer, the dielectric pillar having no internal stress or an internal stress different from an internal stress of the dielectric layer.

Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon substrate, and forming a silicon nitride film on the silicon oxide film. The step of forming the silicon nitride film includes the steps of growing a first silicon layer having a thickness larger than a thickness of a monoatomic silicon layer, nitriding the first silicon layer to form a first silicon nitride layer, growing a second silicon layer on the first silicon layer on the first silicon nitride layer, and nitriding the second silicon oxide layer to form a second silicon nitride layer.

Abstract: A flash memory device and method of forming a flash memory device are provided. The flash memory device includes a silicon nitride layer having a compositional gradient in which the ratio of silicon to nitrogen varies through the thickness of the layer. The silicon nitride layer having a compositional gradient of silicon and nitrogen provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.

Abstract: A process of cleaning a semiconductor manufacturing system, and a method of manufacturing a semiconductor device. The cleaning process includes, for example, positioning a ceramic cover on the electrostatic chuck in tight contact with the chuck, and feeding a fluoride-based cleaning gas into a chamber. After the cleaning process, a process of forming a semiconductor film (deposition process) is performed. It is possible to prevent fluorine degasification from a substrate-supporting electrode (electrostatic chuck) during the deposition process. A semiconductor film can be formed without causing a temperature drop near the substrate. This prevents irregular film thickness, defective etching, film flaking, etc.

Abstract: A semiconductor device having an etch stop layer and a method of fabricating the same are provided. The semiconductor device may include a substrate and a first gate electrode formed on the substrate. An auxiliary spacer may be formed on the sidewall of the first gate electrode. An etch stop layer may be formed on the substrate having the auxiliary spacer. The etch stop layer and the auxiliary spacer may be formed of a material having a same stress property.

Abstract: A method of manufacturing a semiconductor film capable of suppressing difficulty in temperature control of a catalytic wire is obtained. This method of manufacturing a semiconductor film includes steps of heating a catalytic wire to at least a prescribed temperature and forming a semiconductor film by introducing source gas for a semiconductor and decomposing the source gas with the heated catalytic wire after heating the catalytic wire to at least the prescribed temperature.

Abstract: A method is disclosed for making a MEMS device wherein anhydrous HF exposed silicon nitride is used as a temporary adhesion layer allowing the transfer of a layer from a Carrier Wafer to a Device Wafer.

Abstract: A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

Abstract: A method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device that is provided with a step of successively forming a gate insulating film and a gate electrode on a semiconductor substrate and a step of forming a silicon nitride film that covers at least the gate insulating film and the side portions of the gate electrode, in which the silicon nitride film is formed by laminating a plurality of silicon nitride layers by repeating a step of forming a silicon nitride layer of a predetermined thickness by the low-pressure chemical vapor deposition method and a step of exposing the silicon nitride layer to nitrogen.

Abstract: A semiconductor device including a gate stack located over a substrate and a spacer located over the substrate and adjacent the gate stack. The spacer includes a plurality of layers, wherein at least one of the plurality of layers is a batch layer and at least one of the plurality of layers is a non-batch layer.

Abstract: A substrate processing apparatus, including: a reaction container in which a substrate is processed; a seal cap, brought into contact with one end in an opening side of the reaction container via a first sealing member and a second sealing member so as to seal the opening of the reaction container air-tightly; a first gas channel, formed in a region between the first sealing member and the second sealing member in a state where the seal cap is in contact with the reaction container; a second gas channel, provided to the seal cap and through which the first gas channel is in communication with an inside of the reaction container; a first gas supply port that is provided to the reaction container and supplies a first gas to the first gas channel; and a second gas supply port that is provided to the reaction container and supplies a second gas into the reaction container, wherein a front end opening of the first gas supply port opening to the first gas channel, and a base opening of the second gas channel openin

Abstract: Film thickness uniformity and stoichiometry are controlled and deposition rate is increased in the chemical vapor deposition (CVD) of silicon nitride from complex gas mixtures in microwave plasmas. In Si2H6+NH3+Ar gas mixtures using a radial line slot antenna (RLSA) microwave plasma to deposit SiN by CVD, deposition rate and film uniformity are improved by limiting the amounts of atomic or molecular hydrogen from the gas mixture during the deposition process. A halogen, for example, fluorine, is added to a gas mixture of silane or disilane, ammonia and argon. The halogen scavenges hydrogen from the mixture, and prevents the hydrogen from blocking the nitrogen and silicon atoms and their fragments from bonding to the surface atoms and to grow stoichiometric silicon nitride. Adding the halogen generates free halogen radicals that react with hydrogen to create hydrogen halide, for example, HF or HCl, thereby scavenging the hydrogen.

Abstract: A method for fabricating a semiconductor device includes forming a silicided gate utilizing a CMP stack. The CMP stack includes a first liner formed over the underlying semiconductor device and a first dielectric layer formed over the first liner layer. The first dielectric layer is formed to approximately the height of the gate. A second liner layer is formed over the first dielectric layer. Since the first dielectric layer is formed to approximately the height of the gate, the second liner over the moat regions is at approximately the height of the first liner over the gate. A CMP process is performed to expose the first liner over the top of the gate. Since the first dielectric layer is formed to the height of the gate, a portion of the second liner remains over the moat regions after the CMP process. Afterwards, the gate is exposed and a silicidation is performed to create a silicided gate.

Abstract: A nonvolatile semiconductor memory including a semiconductor substrate having an upper surface; a plurality of memory cell transistors formed in the semiconductor substrate, each memory cell transistor including a gate electrode having a gate insulating layer on the upper surface of the semiconductor substrate, a floating gate electrode layer on the gate insulating layer, an inter-gate insulating layer on the floating gate electrode layer, and a control gate electrode layer on the inter-gate insulating layer; a first oxide-based insulating film formed above the upper surface of the semiconductor substrate between the gate electrodes, and including an upper surface as high or higher than that of the floating gate electrode layer but lower than that of the control gate electrode layer; a nitride-based insulating film containing boron formed on the first oxide-based insulating film and the control gate layer; and a second oxide-based insulating film formed on the nitride-based insulating film.

Abstract: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region; a charge storage film formed on the first insulating film; a second insulating film formed above the charge storage film and made of a high-permittivity material; a control gate electrode formed above the second insulating film; and a silicon nitride layer including nitrogen atoms having three-coordinate nitrogen bonds, at least one of second-nearest neighbor atoms of the nitrogen atoms being a nitrogen atom. At least one of the charge storage film and the control gate electrode contains silicon, the silicon nitride layer is located between the second insulating film and the at least one of the charge storage film and the control gate electrode.

Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

Abstract: A method of manufacturing a memory cell 200. The method comprises forming a memory stack 215. Forming the memory stack includes pre-treating an insulating layer 210 in a substantially ammonia atmosphere for a period of more than 5 minutes to thereby form a pre-treated insulating layer 310. Forming the memory stack also includes depositing a silicon nitride layer on the pre-treated insulating layer.

Abstract: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film having Si—N bonds on the substrate.

Abstract: One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer (165). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer (180) over the metal interconnects (170, 175) and the first interlevel dielectric layer (165) within a deposition tool. An adhesion layer (185) is formed on the SiCN layer (180), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer (190) is formed over the adhesion layer (185).

Abstract: A semiconductor integrated circuit structure and method for fabricating. The semiconductor integrated circuit structure includes a light sensitive device integral with a semiconductor substrate, a cover dielectric layer disposed over the light sensitive device, and a lens-formation dielectric layer disposed over the cover dielectric layer. Light is transmittable though the cover dielectric layer, and through the lens-formation dielectric layer. The lens-formation dielectric layer forms an embedded convex microlens. The microlens directs light onto the light sensitive device.

Abstract: A flash memory device and method of forming a flash memory device are provided. The flash memory device includes a silicon nitride layer having a compositional gradient in which the ratio of silicon to nitrogen varies through the thickness of the layer. The silicon nitride layer having a compositional gradient of silicon and nitrogen provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.

Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.

Abstract: A semiconductor device is disclosed that includes a contact and an adjacent film on the surface of an underlying doped semiconductor material. The film has sufficient fixed charge to create an inversion layer adjacent the surface of the doped semiconductor material that under depletion conditions at least balances the number of surface states at the doping concentration of the underlying semiconductor material.

Abstract: An insulating film is formed as a pore-wall protective film (103) on pore walls in a porous layer (102) by the use of a mixed gas plasma of a noble gas and an insulating film forming gas generated by microwave excitation. As a result, the pore-wall protective film can have film properties as a protective film.

Abstract: A semiconductor device includes an operating layer made of a semiconductor and a silicon nitride film formed on the operating layer with the use of a mixed gas that includes mono-silane gas, hydrogen gas, and nitrogen gas, by a plasma CVD apparatus, under a condition that a flow rate of the hydrogen gas is 0.2 percent to 5 percent to an overall flow rate.

Abstract: A method for depositing a silicon nitride based dielectric layer is provided. The method includes introducing a silicon precursor and a radical nitrogen precursor to a deposition chamber. The silicon precursor has a N—Si—H bond, N—Si—Si bond and/or Si—Si—H bond. The radical nitrogen precursor is substantially free from included oxygen. The radical nitrogen precursor is generated outside the deposition chamber. The silicon precursor and the radical nitrogen precursor interact to form the silicon nitride based dielectric layer.

Abstract: A semiconductor structure including an nFET having a fully silicided gate electrode wherein a new dual stress liner configuration is used to enhance the stress in the channel region that lies beneath the gate electrode is provided. The new dual stress liner configuration includes a first stress liner that has an upper surface that is substantially planar with an upper surface of a fully silicided gate electrode of the nFET. In accordance with the present invention, the first stress liner is not present atop the nFET including the fully silicided gate electrode. Instead, the first stress liner of the present invention partially wraps around, i.e., surrounds the sides of, the nFET with the fully silicided gate electrode. A second stress liner having an opposite polarity as that of the first stress liner (i.e., of an opposite stress type) is located on the upper surface of the first stress liner as well as atop the nFET that contains the fully silicided FET.

Abstract: A silicon nitride film including stoichiometrically excessive silicon with respect to nitrogen is formed. The silicon nitride film may be formed by supplying dichlorosilane to a substrate under a condition where CVD (chemical vapor deposition) reaction is caused to form a silicon film including several or less atomic layers on the substrate, supplying ammonia to the substrate in a non-plasma atmosphere to thermally nitride the silicon film under a condition where the nitriding reaction of the silicon film by the ammonia is not saturated, and alternately repeating the supplying of dichlorosilane and the supplying of ammonia.

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.

Abstract: The present invention is directed to methods of forming contact openings. In one illustrative embodiment, the method includes forming a feature above a semiconducting substrate, forming a layer stack comprised of a plurality of layers of material above the feature, the layer stack having an original height, reducing the original height of the layer stack to thereby define a reduced height layer stack above the feature, forming an opening in the reduced height layer stack for a conductive member that will be electrically coupled to the feature and forming the conductive member in the opening in the reduced height layer stack.

Abstract: A method for fabricating an ultra-high tensile-stressed nitride film is disclosed. A PECVD process is first performed to deposit a transitional silicon nitride film over a substrate. The transitional silicon nitride film has a first concentration of hydrogen atoms. The transitional silicon nitride film is subjected to UV curing process for reducing the first concentration of hydrogen atoms to a second concentration of hydrogen atoms.