Abstract: A method of manufacturing a ferroelectric film capacitor includes forming a platinum film used as an electrode material over a whole surface of a silicon substrate, batch-etching the platinum film to form opposite electrodes that serve as a pair of capacitor electrodes, and embedding a ferroelectric film corresponding to a dielectric film of the capacitor into a portion interposed between the pair of opposite electrodes.

Abstract: A thin film transistor array substrate has a gate electrode of the thin film transistor, a gate line connected to the gate electrode, and a gate pad connected to the gate line; a source/drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode, a data pad connected to the data line, a storage electrode formed and superimposed with the gate line; a semiconductor pattern formed in low part of the substrate; a transparent electrode pattern including a pixel electrode connected to the drain electrode and the storage electrode, a gate pad protection electrode covering the gate pad, and a data pad protection electrode covering the data pad; and a protection pattern and a gate insulation pattern stacked in a region other than the region where the transparent electrode pattern is formed.

Abstract: A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

Abstract: A thin-film transistor for an active matrix display is fabricated using printing means, such as a gravure offset printer. First and second pattern layers (251, 252; 30) are formed on a layer structure (4) wherein at least one of the layers is printed. The printed layers (251, 252; 30) mask regions (271, 272, 28) for defining source a and drain terminals. The second pattern layer (28) can be removed so as to allow etching of the second region (28) for defining a channel.

Abstract: The present invention is a process for transfer of a pattern of material from a donor substrate to a receiver substrate by lamination. The pattern of the transferred material is defined by an aperture in a mask interposed between the donor and receiver during lamination. The technique is compatible with flexible polymer receiver substrates and is useful in fabricating thin film transistors for flexible displays.

Abstract: For patterning an IC (integrated circuit) material, a rigid organic under-layer is formed over the IC material, and the rigid organic under-layer is patterned to form a rigid organic mask structure. In addition, the rigid organic mask structure is trimmed to lower a critical dimension of the rigid organic mask structure beyond the limitations of traditional BARC mask structures. Any portion of the IC material not under the rigid organic mask structure is etched away to form an IC structure.

Abstract: The method includes forming on an underlayer wiring a first insulating film, a second insulating, and first mask forming layer; forming a first resist mask having an inverted pattern of wiring Wenches for the upper wiring; etching the first mask forming layer through the first resist mask, thereby forming in the first mask forming layer a concave part conforming to the inverted pattern of wiring tenches for the upper wiring, forming on the first mask forming layer a second mask forming layer, thereby filling the concave part with the second mask forming layer; selectively removing the second mask forming layer on the region in which the wiring trench is formed, thereby forming the second mask having the wiring trench pattern; forming on the first mask forming layer a second resist mask having an opening pattern of the via holes; etching the first mask forming layer and the second insulating film through the second resist mask, thereby forming the via holes.

Abstract: This invention generally relates to semiconductor devices, for example lasers and more particularly to single frequency lasers and is directed at overcoming problems associated with the manufacture of these devices. In particular, a laser device is provided formed on a substrate having a plurality of layers (1,2,3,4,5), the laser device comprising at least one waveguide (for example a ridge) established by the selective removal of sections of at least one of the layers. Wherein alignment features are provided on the device to facilitate subsequent placement.

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched.

Abstract: The present invention provides a method of manufacturing a semiconductor device which includes a step of forming a laminated film for pattern formation on a substrate, in which the laminated film for pattern formation includes an innermost layer, an inner layer and a surface layer, an extinction coefficient k of the innermost layer is 0.3 or more, and an extinction coefficient k of the inner layer is 0.12 or more. It also provides a method of forming a pattern which includes a step of forming a laminated film for pattern formation on a substrate, in which the laminated film for pattern formation includes an innermost layer, an inner layer and a surface layer, an extinction coefficient k of the innermost layer is 0.3 or more, and an extinction coefficient k of the inner layer is 0.12 or more.

Abstract: The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first material. An imagable material is formed on the second material, and patterned. A pattern is then transferred from the patterned imagable material to the first and second materials. The invention also includes a structure comprising a first layer of silicon nitride over a substrate, and a second layer on the first layer. The second layer comprises silicon and is free of nitrogen. The structure further comprises a third layer consisting essentially of imagable material on the second layer.

Abstract: The invention provides a semiconductor device and a method for manufacturing the same that are capable of improving the product performance and operational efficiency of a cross-point FeRAM, as well as increasing the area of capacitors included in the cross-point FeRAM. An upper electrode supporting layer forming mask for forming an upper electrode supporting layer can be made of a hard mask material. By making use of the upper electrode supporting layer forming mask remaining unremoved in forming and processing a lower electrode layer, prior to forming an upper electrode layer, a region where a ferroelectric capacitor is formed can be made larger than an area occupied by an intersection of the upper electrode layer and the lower electrode layer.

Abstract: A method and apparatus that produces highly ordered, nanosized particle arrays on various substrates. These regular arrays may be used as masks to deposit and grow other nanoscale materials.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relatively small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask has an opening at a central part of each relatively large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A photoresist pattern and a method of fabricating the same make it easy to quickly identify a particular portion of a photolithography process that is responsible for causing process defects. The method of fabricating the photoresist pattern includes forming main patterns having a predetermined critical dimension in device-forming regions of a semiconductor substrate, and forming a plurality of test patterns in scribe regions of the substrate. The scribe regions are defined alongside the device-forming regions and separate the device-forming regions from one another. The test patterns have shapes similar to that of the main patterns. Also, one of the test patterns has a critical dimensions similar to that of the main patterns, and other test patterns have respective critical dimensions that are different from the critical dimension of the main patterns.

Abstract: A mask containing apertures therein which is used for fabricating a channel of a thin film transistor (TFT), wherein the pixel charging time for a TFT in a high-resolution liquid crystal display (LCD) device is reduced by minimizing the length of the channel in the TFT when the active region is made of amorphous silicon. The length of the channel can be minimized by exposing light through the apertures is an exposure mask when forming the channel.

Abstract: In an interconnection mask pattern generation, there are suppressed a decrease in reliability of an interconnection and a decrease in manufacture yield, which are resulted from use of an interconnection pattern generated with single minimum line width data for a semiconductor device or the like. When a layout interconnection pattern on a mask for an interconnection which connects functional elements to each other being arranged based on logical circuit data is generated, an interconnection pattern based on the minimum line width data is generated, an interconnection pattern based on the minimum line spacing data is also generated, and an interconnection pattern arranging a new interconnection boundary in the middle of both of them is then generated to be used as a final interconnection pattern, so that the interconnection pattern width becomes properly thick in width, thereby making it possible to improve reliability of the interconnection and suppress a decrease in manufacturing yield.

Abstract: Disclosed is a method for fabricating a semiconductor device with an improved tolerance to a wet cleaning process. For a contact formation such as a gate structure, a bit line or a metal wire, a spin on glass (SOG) layer employed as an inter-layer insulation layer becomes tolerant to the wet cleaning process by allowing even a bottom part of the SOG layer to be densified during a curing process. The SOG layer is subjected to the curing process after a maximum densification thickness of the SOG layer is obtained through a partial removal of the initially formed SOG layer or through a multiple SOG layer each with the maximum densification thickness. After the SOG layer is cured, a self-aligned contact etching process is performed by using a photoresist pattern singly or together with a hard mask.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: A method of forming capacitors with geometric deep trenches. First, a substrate with a pad structure formed thereon is provided, and a first hard mask layer is formed on the pad structure. Next, a second hard mask layer is formed on the first hard mask layer. Next, a spacer layer is formed in the first opening on the first hard mask layer to expose a second opening. Next, a third hard mask layer is filled the second opening, and the spacer layer is removed. Next, the first hard mask layer is etched to expose a third opening with a salient of the first hard mask layer, with the second hard mask layer and the third hard mask layer acting as masks. Finally, the first hard mask layer, the pad structure, and the substrate are etched to form a geometric deep trench.

Abstract: In order to shorten the period for the development and manufacture of a semiconductor integrated circuit device, at the time of transferring integrated circuit patterns onto a wafer by an exposure process, a photomask PM1 is used which is provided partially with light shielding patterns 3a formed of a resist film, in addition to light shielding patterns formed of a metal.

Abstract: A mask capable of alignment by the TTR system and complementary division and having a high strength, a method of production of the same, and a method of production of a semiconductor device having a high pattern accuracy are provided. A stencil mask having stripe-shaped grid lines 4 formed by etching a silicon wafer in four sub-regions A to D on a membrane, having the stripes arranged point symmetrically about a center of the membrane, and having all of the grid lines connected to other grid lines or the silicon wafer around the membrane (support frame), a method of production of the same, and a method of production of a semiconductor device using the mask.

Abstract: A method for planarizing a substrate surface having a non-planar surface topography comprises forming a material layer over the substrate, the material layer having a surface topography, determining the surface topography of the material layer, and forming a mask using information relating to the surface topography of the material layer. The mask defines portions of averaging regions of the material layer for selective removal to equalize the averaging regions in average height, the averaging regions having a maximum dimension. The material layer is etched using the mask, and a planarizing layer is formed over the substrate surface. The planarizing layer provides a low-pass lateral filtering effect characterized by a length greater than the maximum dimension of the averaging region.

Abstract: In a method for creating a stepped structure on a substrate, which at least includes a first portion with a first thickness and a second portion with a second thickness, at first a layer sequence of a first oxide layer, a first nitride layer, and a second oxide layer is applied onto the substrate. Then a portion of the second oxide layer and a portion of the first nitride layer are removed to expose a portion of the first oxide layer. Then a part of the first nitride layer is removed to establish the first region of the stepped structure. Then the thickness of the first oxide layer is changed at least in the established first region to establish the first thickness of this region. Subsequently, a further part of the first nitride layer is removed to establish a second region of the stepped structure.

Abstract: Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of active area formed within the semiconductive substrate which are continuous between adjacent memory cells, said adjacent memory cells being isolated from one another relative to the continuous active area formed therebetween by a conductive line formed over said continuous active area between said adjacent memory cells. At least some adjacent lines of continuous active area within the array are isolated from one another by LOCOS field oxide formed therebetween. The respective area consumed by individual memory cells is ideally equal less than 8F2, where “F” is no greater than 0.

Abstract: A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.

Abstract: A new method to form a floating gate for a flash memory device is achieved. The method comprises forming a first conductor layer overlying a substrate with a gate dielectric layer therebetween. A masking layer is deposited overlying the first conductor layer. The masking layer is patterned to expose first regions of and to cover second regions of the first conductor layer. A plurality of first concave surfaces are formed on the first conductor layer first regions. The masking layer is removed. A plurality of second concave surfaces are formed on the first conductor layer second regions. The first conductor layer is patterned to form floating gates. The interfaces between the plurality of first and second concave surfaces form vertical tips on the floating gates. A method to form an electron emitter is also disclosed.

Abstract: In a semiconductor integrated circuit device including a plurality of semiconductor devices formed on a substrate, the principal plane of the substrate is partitioned into a plurality of device regions and into a plurality of routing regions each crossing a boundary between the plural device regions. A device group including one or more semiconductor devices among the plural semiconductor devices and a local interconnect for connecting the semiconductor devices included in the device group are disposed within the plural device regions. A global routing for connecting the device groups to each other is disposed within each of the plural routing regions.

Abstract: Aperture masks and deposition techniques for using aperture masks are described. In addition, techniques for creating aperture masks and other techniques for using the aperture masks are described. The various techniques can be particularly useful in creating circuit elements for electronic displays and low-cost integrated circuits such as radio frequency identification (RFID) circuits. In addition, the techniques can be advantageous in the fabrication of integrated circuits incorporating organic semiconductors, which typically are not compatible with wet processes.

Abstract: An alignment pattern is required for photo masks to be exactly aligned with one another; an amorphous silicon is deposited over the entire surface of an insulating layer except for an area where the alignment pattern is to be formed, and a pattern for an ion-implantation and the alignment pattern are concurrently transferred to a photo resist layer; dopant impurity is ion implanted into the amorphous silicon layer by using the photo resist mask, and the insulating layer is selectively etched also by using the photo resist mask; this results in simplification of the process sequence.

Abstract: Disclosed are layered groupings and methods for constructing digital circuitry, such as memory known as Permanent Inexpensive Rugged Memory (PIRM) cross point arrays which can be produced on flexible substrates by patterning and curing through the use of a transparent embossing tool.

Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.

Abstract: An optical system includes multiple cubic crystalline optical elements aligned along a common optical axis and having their crystal lattices oriented with respect to each other to minimize the effects of intrinsic birefringence and produce a system with reduced retardance. The optical system may be a refractive or catadioptric system having a high numerical aperture and using light with a wavelength at or below 248 nanometers. The net retardance of the system is less than the sum of the retardance contributions of the respective optical elements as the elements are oriented such that the intrinsic birefringences of the individual elements cancel each other out. In one embodiment, two [110] cubic crystalline optical elements are clocked with respect to one another and used in conjunction with a [100] cubic crystalline optical element to reduce retardance. Various birefringent elements, wave plates, and combinations thereof provide additional correction for residual retardance and wavefront aberrations.

Abstract: A conductive pattern is obtained by forming concave-convex on a substrate by using a pattern substrate. A conductive thin layer is formed and then coated with a layer of a photosensitive resin. The photo sensitive resin is exposed and development by using the pattern substrate to bare the conductive thin layer on the convex portion and electrolytic plating. The conductive thin layer and the layer of the photosensitive resin on the concave portion may then be removed.

Abstract: In a method for exposing a photosensitive resist layer with near-field light, a liquid film layer is provided between the photosensitive resist layer and a photomask. The photomask has a light-shielding film containing an opening portion through which a propagated light emitted from a light source cannot pass. The photosensitive resist layer is exposed with near-field light through the opening portion and the liquid film layer.

Abstract: A method for the duplication of microscopic patterns from a master to a substrate is disclosed, in which a replica of a topographic structure on a master is formed and transferred when needed onto a receiving substrate using one of a variety of printing or imprint techniques, and then dissolved. Additional processing steps can also be carried out using the replica before transfer, including the formation of nanostructures, microdevices, or portions thereof. These structures are then also transferred onto the substrate when the replica is transferred, and remain on the substrate when the replica is dissolved. This is a technique that can be applied as a complementary process or a replacement for various lithographic processing steps in the fabrication of integrated circuits and other microdevices.

Abstract: Disclosed is a thin film transistor (TFT) for a liquid crystal display (LCD) and a method for manufacturing the same that allows the number of photomasks used in a photolithography process to be decreased as compared to conventional methods. A passivation film is formed as a single layered organic insulating film, and the number of needed exposure steps is reduced, so as to decrease the number of needed photomask sheets and thereby improve the efficiency of the TFT production process. Applications of the disclosed method include reflection and transmission composite type LCDs as well as a reflection type LCD.

Abstract: An alignment mark mask element protects an underlying alignment mark during subsequent processing of the fabrication substrate. The alignment mark mask element is formed concurrent with formation of a photomask from a dual-tone photoresist that exhibits a pattern reversal upon exposure to an energy level. A portion of the dual-tone photoresist above the alignment mark is exposed to an energy sufficient to reverse a positive tone resist to a negative tone, which remains above the alignment mark after developing. The remainder of the dual-tone photoresist is exposed through a reticle at a lesser energy level and patterned to define aperture locations of a photomask for formation of semiconductor device features. In addition, a photomask for use on a fabrication substrate and an intermediate semiconductor device are disclosed. Methods of forming a photomask and an intermediate semiconductor device structure are also disclosed.

Abstract: The present invention provides a method of forming a TFT and a reflective electrode having recesses or projections with reduced manufacturing cost and a reduced number of manufacturing steps, and provides a liquid crystal display device to which the method is applied. A photosensitive film 8 is formed on a metal film 7. Then, remaining portions 81, 82 and 83 are formed from the photosensitive film 8. Then, the metal film 7 is etched by using the remaining portions 81, 82 and 83 as masks. And then, a photosensitive film 9 and a reflective electrode film 10 are formed without removing the remaining portions 81, 82 and 83.

Abstract: Dual damascene methods of fabricating conducting lines and vias in organic intermetal dielectric layers utilize sacrificial inorganic dielectrics. In one embodiment, a via opening formed in organic intermetal dielectric layers is filled with sacrificial inorganic dielectric. A line opening is formed aligned with the via opening. The sacrificial inorganic dielectric is selectively removed. The via and line openings are filled with conducting material. In a second embodiment, a line opening formed in organic intermetal dielectric layers is filled with sacrificial inorganic dielectric. A via opening is formed aligned with the line opening. The sacrificial inorganic dielectric is selectively removed. The via and line openings are filled with conducting material. The sacrificial inorganic dielectrics protect the organic intermetal dielectric layers, preserving critical dimensions and facilitating photoresist rework.

Abstract: A method to relax the alignment accuracy requirement in an integrate circuit manufacturing is described. The method comprises forming a mask layer over a substrate, and the mask layer comprises a plurality of first openings. Thereafter, a buffer layer fills the first opening, followed by forming a photoresist layer over the substrate. The photoresist layer is then patterned to form a second opening that corresponds to the first opening, and the second opening exposes a portion of the buffer layer. Isotropic etching is then performed to remove the buffer layer exposed by the second opening to expose a sidewall of the first opening that corresponds to the second opening. The photoresist layer is further removed to expose the mask layer that comprises the embedded buffer layer and the opening pattern, which is used as a hard mask layer in a subsequent process.

Abstract: There is provided a method of fabricating a semiconductor device whereby fine patterns are formed with high dimensional accuracy by means of multiple exposures, using a phase shift mask and a trim mask. Phases are periodically assigned to shifter patterns within a given range from patterns generated with the phase shift mask, respectively.

Abstract: A substrate exposure apparatus, having a display apparatus and a control system. The display apparatus is used to display the pattern and to transfer the pattern to the photoresist, and includes a non-self luminescent display or a self-luminescent display. The control system is used to control the pattern displayed on the display apparatus.

Abstract: A method of forming a resist layer on a non-planar surface of a substrate includes placing the non-planar surface into an electrophoretic resist. While the non-planar surface is in the electrophoretic resist, an electrical voltage is applied between the substrate and the electrophoretic resist. The non-planar surface can then be removed from the electrophoretic resist.

Abstract: A method for manufacturing an electronic device is provided. In one example of the method, the method prevents deformation of a resist mask caused by the irradiation of exposure light. The resist mask has a resist as an opaque element, and can afford mask patterns undergoing little change even with an increase in the number of wafers subjected to exposure processing. The resist mask maintains a high dimensional accuracy. A photomask pattern is formed using as an opaque element a resist comprising a base resin and Si incorporated therein or a resist with a metal such as Si incorporated thereby by a silylation process, to improve the resistance to active oxygen. The deformation of a resist opaque pattern in a photomask is prevented. The dimensional accuracy of patterns transferred onto a Si wafer is improved in repeated use of the photomask.

Abstract: A pan/tilt camera system includes a sensor spaced from a rotational shaft of a pan/tilt camera, a detected piece rotated with the rotational shaft so as to correspond to the sensor, an origin setting unit rotating the rotational shaft in a first direction upon turn-on of a power and thereafter in a second direction opposite to the first direction so that the sensor detects a rear end of the detected piece for setting an origin, a pulse counter applying a predetermined number of pulses to the motor after set of the origin so that the rotational shaft is continuously rotated in the second direction and counting pulses applied to the motor until a front end of the detected piece with respect to the rotation direction of the detected piece is detected, and a backlash calculating unit comparing a count of the pulse counter with the predetermined number of pulses applied to the motor thereby to calculate an amount of backlash of the drive mechanism.

Abstract: Polymer blobs that are development related defects are substantially eliminated in patterned photoresist masks by a heat treatment of the wafer performed at a development step in two different manners according to the present invention. In the first method, after the development has been performed as standard, the wafer is heated at 140° C. and before cooling takes place, it is rinsed with deionized water (DIW) at room temperature. In the second method, the wafer is either developed as standard but rinsed with 60° C. DIW instead of 22° C. DIW, or, after standard development, it is submitted to an extra rinse step with 60° C. DIW.

Abstract: An exposure apparatus comprising (a) irradiating means for illuminating a mask with laser light from an excimer laser and (b) a projection optical system for projecting a pattern of the mask onto a substrate with the laser light, wherein a characteristic of the projection optical system is measured by use of a harmonic of a predetermined laser, and wherein the laser light from the excimer laser has a wavelength corresponding to that of the harmonic of the predetermined laser.

Abstract: A method and system for providing a semiconductor device is disclosed. The method and system include providing a semiconductor substrate and providing a plurality of lines separated by a plurality of spaces. Each of the plurality of spaces preferably has a first width that is less than a minimum feature size. In one aspect, the method and system include providing a reverse mask having a plurality of apertures on an insulating layer. In this aspect, the method and system also include trimming the reverse mask to increase a size of each of the plurality of apertures, removing a portion of the insulating layer exposed by the plurality of trimmed apertures to provide a plurality of trenches and providing a plurality of lines in the plurality of trenches. In a second aspect, the method and system include providing a reverse mask on the insulating layer and removing a first portion of the insulating layer exposed by the plurality of apertures to provide a plurality of trenches.

Abstract: A method of manufacturing a mask includes: attaching a second substrate having a plurality of penetrating holes to a first substrate having an opening. The second substrate is attached such that the penetrating holes are positioned within the opening. A groove is formed on a surface of the first substrate facing the second substrate. The groove is utilized to form a flow path between the first and second substrates.