Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: A method for fabricating a thin film transistor array and driving circuit comprising the steps of: providing a substrate; patterning a polysilicon layer and an N+ thin film over the substrate to form a plurality of islands; patterning the islands to form P+ doped regions; patterning out source/drain terminals and the lower electrode of a storage capacitor; etching back the N+ thin film; patterning out a gate and the upper electrode of the storage capacitor and patterning a passivation layer and a conductive layer to form pixel electrodes and a wiring layout.

Abstract: A circuit pattern, a reticle alignment mark, a bar code, and a discrimination mark which are formed on a glass plate of a photo mask is constituted of a photo sensitive and photo attenuative material containing a fine particle material and a binder. Discrimination of the photo mask is performed by irradiating predetermined discrimination light on the discrimination mark or the bar code. Alignment of the photo mask by an aligner is performed by irradiating predetermined detection light on the reticle alignment mark. In an exposure process, the pattern on the photo mask is transferred onto a semiconductor wafer by using exposure light having a wavelength different from that of the discrimination light or that of the detection light.

Abstract: Measure of forming an EL layer by selectively depositing through evaporation a material for forming the EL layer at a desired location is provided. When a material for forming an EL layer is deposited, a mask (113) is provided between a sample boat (111) and a substrate (110). By applying voltage to the mask (113), the direction of progress of the material for forming the EL layer is controlled to be selectively deposited at a desired location.

Abstract: The membrane mask is based on an SOI substrate. In an existing or subsequently produced multilayer semiconductor/insulator/semiconductor-carrier-layer substrate, the inhomogeneous mechanical stresses in the semiconductor layer, which lead to undesirable distortions, are converted at least partly into a homogenous state prior to the structuring of the semiconductor layer. In order to accomplish this, either an additional layer structure is provided on an existing SOI substrate, or a modified layer structure is provided in the fabrication of the SOI substrate, or both.

Abstract: The method of making a GaN single crystal substrate comprises a mask layer forming step of forming on a GaAs substrate 2 a mask layer 8 having a plurality of opening windows 10 disposed separate from each other; and an epitaxial layer growing step of growing on the mask layer 8 an epitaxial layer 12 made of GaN.

Abstract: Disclosed is a method of manufacturing a photomask, comprising calculating a pattern area ratio, which is a ratio of the light transmitting pattern portion or the light shielding pattern portion to an area of the photomask from the design data of a given layout pattern of the photomask, and a pattern density, which is a ratio of the light transmitting pattern portion or light shielding pattern portion within the region to the area of the region extracted from the given layout pattern, estimating from the calculated pattern area ratio and the pattern density the size of a pattern formed in the case where the pattern is formed on the photomask by using the design data of the given layout pattern, and imparting the amount of correction to the design data of the given layout pattern based on the estimated pattern size.

Abstract: A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.

Abstract: A semiconductor device comprises a semiconductor substrate, a p-type well formed in the semiconductor substrate, an n-type well formed in the semiconductor substrate and positioned contiguous to the p-type well, an n-type diffused region formed in the p-type well, and a p-type diffused region formed in the n-type well, wherein a corner C1 having the p-type well on the inside is present in a part of the boundary pattern between the p-type well and the n-type well. At least one of the two sides defining the corner C1 extends from a top of the corner to the n-well by a predetermined width d over a predetermined length. The particular structure permits suppressing generation of a difference in a well isolation punch-through voltage between the corner and the straight portion of the well boundary of the semiconductor device, making it possible to provide a fine device structure while ensuring a desired well isolation punch-through voltage without relaxing a design rule.

Abstract: The present invention describes a method of forming a mask comprising: providing a substrate, the substrate having a first thickness; forming a balancing layer over the substrate, the balancing layer having a second thickness; forming an absorber layer over the balancing layer, the absorber layer having a first region separated from a second region by a third region; removing the absorber layer in the first region and the second region; removing the balancing layer in the second region; and reducing the substrate in the second region to a third thickness. The present invention also describes a mask comprising: an absorber layer, the absorber layer having a first opening and a second opening, the first opening uncovering a balancing layer disposed over a substrate having a first thickness, and the second opening uncovering the substrate having a second thickness.

Abstract: A partial plating system able to gold plate only inner leads of a TAB frame, provided with a mask having an opening formed to correspond to a plating region of a TAB frame and provided horizontally; an elevating means for lowering the TAB frames toward the mask; and a pressing means for pressing the TAB frame on to the mask; a plating solution being sprayed from below the openings toward the openings to plate the plating region.

Abstract: A method for manufacturing an x-ray detector comprises the steps of: preparing an insulating substrate; forming a gate and a pad on the insulating substrate; forming a gate insulating film, an amorphous silicon layer and an etch stopper over the insulating substrate, inclusive of the gate and the pad; simultaneously forming a channel layer, an ohmic contact layer and a source/drain over the gate insulating film, inclusive of the etch stopper, and a common electrode over a proper portion of the gate insulating film; forming a first storage electrode over the gate insulating film, inclusive of the common electrode; forming a protective layer over the entire structure of the insulating substrate on which the source/drain and the first storage electrode have been formed, and subsequently forming a contact hole and via holes over a proper portion of the protective layer; and forming a second storage electrode over the protective layer.

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched.

Abstract: A method of precluding diffusion of a metal into adjacent chalcogenide material upon exposure to a quanta of actinic energy capable of causing diffusion of the metal into the chalcogenide material includes forming an actinic energy blocking material layer over the metal to a thickness of no greater than 500 Angstroms and subsequently exposing the actinic energy blocking material layer to said quanta of actinic energy. In one implementation, an homogenous actinic energy blocking material layer is formed over the metal and subsequently exposed to said quanta of actinic energy. A method of forming a non-volatile resistance variable device includes providing conductive electrode material over chalcogenide material having metal ions diffused therein.

Abstract: The process for the fabrication of an electronic device has the steps of forming a layer to be etched on top of a substrate in a wafer of semiconductor material; depositing a masking layer; and carrying out a plasma etch to define the geometry of the layer to be etched. The masking layer is made so as to be conductive, at least during one part of the etching step; in this way, the electrons implanted on the top part of the masking layer during plasma etching can recombine with the positive charges which have reached the layer to be etched. The recombination of the charges makes it possible to prevent damage from plasma resulting from the formation of parasitic electric currents which are detrimental to the electronic device itself.

Abstract: A new method is provided for the creation of an attenuated phase shifting mask. A transparent mask substrate is provided, a layer of attenuating phase shifting material is deposited on the surface of said transparent mask substrate, a layer of opaque material is deposited on the surface of said layer of attenuating phase shifting material. A layer of photoresist is deposited over the surface of the layer of opaque material. The photoresist is exposed by E-beam, creating a mask pattern and a guard ring pattern in the photoresist. The (E-beam) exposed photoresist is removed, the pattern created in the layer of photoresist is used to etch a mask pattern in the layer of opaque material and the layer of attenuating phase shifting material. The remaining photoresist is exposed to UV radiation in the region of the mask pattern and partially in the region of the guard ring.

Abstract: A method for fabricating a resonator, and in particular, a thin film bulk acoustic resonator (FBAR), and a resonator embodying the method are disclosed. An FBAR is fabricated on a substrate by introducing a mass loading top electrode layer. For a substrate having multiple resonators, the top mass loading electrode layer is introduced for only selected resonator to provide resonators having different resonance frequencies on the same substrate.

Abstract: In order to shorten the period for the development and manufacture of a semiconductor integrated circuit device, at the time of transferring integrated circuit patterns onto a wafer by an exposure process, a photomask PM1 is used which is provided partially with light shielding patterns 3a formed of a resist film, in addition to light shielding patterns formed of a metal.

Abstract: A method is provided for well printing a specified pattern even when the exposure treatment using a resist mask uses exposure light with a wavelength over 200 nm. When exposure treatment is applied to a semiconductor wafer by using exposure light with a wavelength over 200 nm, a photomask is used. The photomask is provided with an opaque pattern of a resist layer on an organic layer which is photoabsorptive in reaction to exposure light.

Abstract: In one illustrative embodiment, the method includes providing a wafer including at least one non-production area, forming a process layer above the wafer, forming a masking layer above the process layer, the masking layer being patterned so as to expose a portion of the process layer formed above the at least one non-production area, and performing a process operation on the exposed portion of the process layer formed above the at least one non-production area. In another aspect, the present invention is directed to a system that includes a controller for identifying at least one non-production area of a wafer, a photolithography tool for forming a masking layer above the process layer, the masking layer being patterned so as to expose a portion of the process layer formed above the at least one non-production area, and an etch tool for performing an etching process on the exposed portion of the process layer formed above the at least one non-production area.

Abstract: The present invention is directed to an automated method of controlling photoresist develop time to control critical dimensions, and a system for accomplishing same. In one embodiment, the method comprises measuring a critical dimension of each of a plurality of features formed in a layer of photoresist, providing the measured critical dimensions of the features, in the layer of photoresist to a controller that determines, based upon the measured critical dimensions, a duration of a photoresist develop process to be performed on a layer of photoresist formed above a subsequently processed wafer, and performing a photoresist develop process on the subsequently processed wafer for the determined duration.

Abstract: A thin film transistor. The thin film transistor comprises a substrate, a dielectric layer and a polysilicon layer. A gate electrode is located on the substrate. A dielectric layer is located on the substrate and the gate electrode. A polysilicon layer is located on the dielectric layer. The polysilicon layer comprises a channel region and a doped region, wherein the channel region is located above the gate electrode and the doped region is adjacent to the channel region.

Abstract: A method of manufacturing a semiconductor device and an apparatus of automatically adjusting a semiconductor pattern can precisely correct a difference in the shape or position of a pattern exposed or formed in two exposure steps. A pattern measuring unit measures an offset between the first pattern and the second pattern in a pattern measuring step. Based on the information on the offset thus detected, the first pattern is adjusted in a first patterning step with a high degree of freedom in the next manufacturing step cycle of a semiconductor device to precisely align the shape or position of the first pattern with the second pattern in a second patterning step with a low degree of freedom.

Abstract: The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lover erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole. However, when only some memory cells of a group have a higher erase speed, an excessive erase requiring electric charge supply occurs only in some memories and accordingly, it is possible to rapidly complete the data.

Abstract: A graphic method for preparing a surface map used to synthesize a masking layer. The proposed structures on a semiconductor surface are mapped as trapezoidal figures on a numerical grid. The first grouping step groups trapezoids into a plurality of groups based on Ymin, and groups are then internally sorted based on Xmin. A to-be-judged group is selected. A intra-group judging step uses a trapezoid as a to-be-judged figure in order of sorting, and trapezoids sorted after the to-be-judged trapezoid as a to-be-compared figures successively in order of sorting, determining if there is intersection and if so incrementally moving the to-be-compared figure, and repetitively executing an intersection judgment processing until there is no intersection or until the to-be-compared figure disappears.

Abstract: A pattern is transferred to a resist film on a wafer by a reduction projection exposure method using a half-tone phase-shift mask in which is formed a half-tone phase-shifter pattern including a thin-film pattern functioning as an attenuator and a resist pattern functioning as the photosensitive composition for phase adjustment. This method improves the accuracy of dimensions of the pattern transferred to the wafer.

Abstract: A method for using intermediate transfer layers for transferring nanoscale patterns to substrates and forming nanostructures on substrates. An intermediate transfer layer is applied to a substrate surface, and one or more mask templates are then applied to the intermediate transfer layer. Holes are etched through the intermediate transfer layer, and material may be deposited into the etched holes.

Abstract: A damascene structure, and a method of fabricating same, containing relatively low dielectric constant materials (e.g., k less than 3.8). A silicon-based, photosensitive material, such as plasma polymerized methylsilane (PPMS), is used to form both single and dual damascene structures containing low k materials. During the manufacturing process that forms the damascene structures, the silicon-based photosensitive material is used as both a hard mask and/or an etch stop.

Abstract: The invention relates to the manufacture of semiconductor elements (10), in which manufacturing process a part (50) of a semiconductor body (11) having a silicon substrate (32) from which the semiconductor elements (10) are formed is removed by means of powder blasting. For this purpose, the surface of the semiconductor body (11) is provided with a mask pattern (40). In this manner, for example, discrete diodes (10) are manufactured in a simple and inexpensive way. A drawback of the known method resides in that it results in diodes (10) having non-uniform properties which, in addition, cannot be readily reproduced from batch to batch.

Abstract: A method of forming a dual damascene line structure suitable for forming a fine pattern is disclosed in the present invention. The method for forming a dual damascene line structure on a substrate includes sequentially depositing an inter-metal dielectric and a first hard mask over the substrate, partially removing the first hard mask to have a positive trench pattern using a first photoresist pattern as a mask, forming a second hard mask having a substantially different etch selectivity from the first hard mask on the partially removed portion of the first hard mask, selectively removing the first hard mask to have a negative via hole pattern using a second photoresist pattern as a mask, partially removing the inter-metal dielectric to have a via hole pattern using the first hard mask as a mask, and forming a trench and a via hole by removing the exposed first hard mask and selectively etching the inter-metal dielectric using the second hard mask.

Abstract: Mask and integrated circuit fabrication approaches are described to facilitate use of so called “full phase” masks. This facilitates use of masks where substantially all of a layout is defined using phase shifting. More specifically, exposure settings including relative dosing between the phase shift mask and the trim masks are described. Additionally, single reticle approaches for accommodating both masks are considered. In one embodiment, the phase shifting mask and the trim mask are exposed using the same exposure conditions, except for relative dosing. In another embodiment, the relative dosing between the phase and trim patterns is 1.0:r, 2.0<r<4.0. These approaches facilitate better exposure profiles for the resulting ICs and can thus improve chip yield and increase throughput by reducing the need to alter settings and/or switch reticles between exposures.

Abstract: A method for forming a thin film transistor (TFT) is disclosed. A gate electrode, insulating layer, semiconductor layer, doped silicon layer and metal layer are formed on a substrate. A first photoresist layer with a first absorptivity is formed on the metal layer. A second photoresist layer with a second absorptivity is formed on the first photoresist layer. The second absorptivity is higher than the first absorptivity. An exposure process and a development process are performed to form a first pattern on the first photoresist layer and a second pattern on the second photoresist layer at the same time. An etching process is then performed to transfer the first pattern into the semiconductor layer, the doped silicon layer and the metal layer and transfer the second pattern into the doped silicon layer and the metal layer. After performing the etching process, the first photoresist layer and the second photoresist layer are removed.

Abstract: The membrane mask is based on an SOI substrate. In an existing or subsequently produced multilayer semiconductor/insulator/semiconductor-carrier-layer substrate, the inhomogeneous mechanical stresses in the semiconductor layer, which lead to undesirable distortions, are converted at least partly into a homogenous state prior to the structuring of the semiconductor layer. In order to accomplish this, either an additional layer structure is provided on an existing SOI substrate, or a modified layer structure is provided in the fabrication of the SOI substrate, or both.

Abstract: In the manufacturing method of an array substrate for a planar display device, a first pattern is formed on a substrate by correcting in advance the size of the first pattern in view of an amount of deformation of the substrate. Then, the next pattern is formed on the substrate in conformity with the pattern formed in the preceding step.

Abstract: A method for forming high quality multiple thickness oxide layers having different thicknesses by eliminating descum induced defects. The method includes forming an oxide layer, masking the oxide layer with a photoresist layer, and developing the photoresist layer to expose at least one region of the oxide layer. The substrate is then heated and descummed to remove any residue resulting from developing the photoresist. Alternatively, the photoresist layer may be cured prior to heating and descumming the substrate. The oxide layer is then etched, and the remaining photoresist is stripped before another layer of oxide is grown on the substrate.

Abstract: A method for fabricating a multi-channel array optical device having uniform spacing between different wavelengths and for having precise wavelengths by accomplishing wavelength adjustment and by the forming of mirror layers simultaneously through a multi-layer binary mask and a selective oxidization process. This method is especially useful for fabricating multi-channel array optical devices including multi-channel passive filters and multi-channel surface emitting laser arrays. The method includes forming a plurality of semiconductor mirror layers on a semiconductor substrate; forming an oxidization protective layer on the plurality of semiconductor mirror layers; selectively removing the oxidization protective layer by using a binary mask to expose the semiconductor mirror layer which will adjust a wavelength; oxidizing the exposed semiconductor mirror layer.

Abstract: Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.

Abstract: An apparatus and system for fabricating a wafer utilizing a dual damascene process. A photolithographic device having transparent portions and radiant energy inhibiting portions is used to process a wafer-in-process having a first dielectric layer, a hard mask over the first dielectric layer, vias in a second dielectric layer which overlies the hard mask, and a photoresist material within the vias. The photolithographic device is registered to the wafer-in-process to prevent radiant energy from being directly transmitted into the photoresist material overlaying the vias. This prevents the exposure of a portion of the photoresist material at a lower portion of the vias, thus protecting the hard mask layer and/or the conductive plugs from damage during a subsequent etching process. The exposed photoresist material is then removed.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: Disclosed is a method of manufacturing a photomask, comprising calculating a pattern area ratio, which is a ratio of the light transmitting pattern portion or the light shielding pattern portion to an area of the photomask from the design data of a given layout pattern of the photomask, and a pattern density, which is a ratio of the light transmitting pattern portion or light shielding pattern portion within the region to the area of the region extracted from the given layout pattern, estimating from the calculated pattern area ratio and the pattern density the size of a pattern formed in the case where the pattern is formed on the photomask by using the design data of the given layout pattern, and imparting the amount of correction to the design data of the given layout pattern based on the estimated pattern size.

Abstract: A resist mask pattern having a reduced thickness is formed overlying on a silicon oxynitride film during formation of a memory gate. The resist mask pattern has a resist thickness (3000 to 4000 Angstroms) sufficient to withstand removal during etching of the silicon oxynitride film. The silicon oxynitride film, having a thickness of about 800 to 1500 Angstroms, is etched based on the resist mask pattern and then used as a mask pattern to etch the polysilicon gate layer underlying the silicon oxynitride layer, to expose a portion of an isolation region aligned relative to the resist mask pattern. The portion of the resist mask remaining after etching, in combination with the etched silicon oxynitride film, have a sufficient overall thickness to serve as a channel implant mask. Use of the resist mask pattern having the reduced thickness improves yield by minimizing the occurrence of misregistration, and enables reliable formation of spaces in the mask pattern having widths of less than 0.

Abstract: This invention increases the overlapped area between the diffusion area and the borderless contact by using optical proximity correction (OPC) method. The method includes performing an optical proximity correction on an outer corner of an active area mask to enlarge a portion of an outer corner of an active area on a substrate in a photolithography process, wherein the outer corner of the active area is used to make contact with a borderless contact. The enlarged portion of the outer corner of the active area increases the overlapped area between the borderless contact and the active area, and reduces borderless contact leakage.

Abstract: The present invention provides a multiple exposure method for defining a rectangular pattern on a photoresist layer. The method comprises the following steps. First, a rectangular region is defined on the photoresist layer, having a first margin pair and a second margin pair corresponding to the rectangular pattern. Next, a first exposure process is performed on a first exposure region of the photoresist layer. An extension of the first margin pair acts as a boundary between the first exposure region and the rectangular region. Next, a second exposure process is performed on a second exposure region of the photoresist layer. An extension of the second margin pair acts as a boundary between the second exposure region and the rectangular region. Finally, a development process is performed on the first exposure region and the second exposure region to create the rectangular pattern on a substrate.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

Abstract: An etching mask having high etching selectivity for an inorganic interlayer film of SiO2 or Si3N4, an organic interlayer film such as ARC and an electrically conductive film and a contact hole using such an etching mask, a process for forming same and a resultant semiconductor device. On formation of contact holes for connecting wirings disposed through interlayer films of inorganic or organic material (20, 23 in FIG. 2), a thin film of silicon carbide (21 in FIG. 2) having high etching selectivity for any of the inorganic and organic materials is deposited on an interlayer film, and a mask pattern of silicon carbide is formed using a resist pattern (22 in FIG. 2). Thereafter, high aspect ratio contact holes having a size which is exactly same as that of the mask is formed by etching the interlayer film using the silicon carbide mask.

Abstract: A method and a system for processing a semiconductor device intended to improve the overlay accuracy of a semiconductor device product, particularly in its device area, in carrying out the mix-and-match exposure process are designed to calculate the difference of exposure distortions between two layers in the device area and the difference of exposure distortions between the two layers at the overlay measurement mark position from data of exposure field distortions of two exposure tools used for the mix-and-match exposure process and data of device area and overlay measurement mark position of the product, calculate a modification value which relates both differences to each other, calculate a first exposure condition correction value from the measurement result of overlay, and carry out the exposure process based on a second exposure condition correction value which is evaluated by modifying the first exposure condition correction value with the modification value.

Abstract: The manufacturing method produces a semiconductor in which current is not generated during the off state by reducing the electric field at the corner of an active region. The method includes patterning a gate material layer on a predetermined portion on the active region. The mask has an open region which exposes the active region but does not expose the filed region. A gate electrode and source/drain regions are formed by doping impurities into the exposed gate material layer and the active region.

Abstract: In the construction of electronic devices with one or more flip chips and, in some cases, one or more leadless components, mounted on a substrate, the interconnections are made with conductive adhesive deposited using specialized masks. A magnetic metal mask fabricated of a membrane of magnetic material is placed temporarily onto the face of a semiconductor wafer or of a circuit or other substrate. When properly positioned with respect to the wafer or substrate, such as by relational guide holes, the mask is held in place by the magnetic forces produced by a controllable electromagnet. Contact pad openings in the magnetic metal mask are formed by suitable means such as laser cutting or photo-etching. The magnetic metal mask may include a flexible interface layer on the side facing the wafer or substrate to assure tight sealing thereto, so as to reduce smearing and bridging of the conductive adhesive paste and avoid bridging between contact pads that might otherwise occur during deposition of the paste.