Abstract: Methods of forming substrates having two-sided microstructures therein include selectively etching a first surface of the substrate to define a plurality of alignment keys therein that extend through the substrate to a second surface thereof. A direct photolithographic alignment step is then performed on a second surface of the substrate by aligning a photolithography mask to the plurality of alignment keys at the second surface. This direct alignment step is performed during steps to photolithographically define patterns in the second surface.

Abstract: A method for fabricating semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second mask pattern having a first portion and a second portion over the etch target layer in the peripheral region, forming a photoresist pattern over the cell region, trimming the first portion of the second mask pattern, removing the photoresist pattern and the second portion of the first mask pattern and the second portion of the second mask pattern, and etching the etch target layer to form a pattern in the cell region and a pattern in the peripheral region.

Abstract: A method of manufacturing a silicon carbide semiconductor device according to the present invention includes the steps of (a) forming an implantation mask made up of a plurality of unit masks on a silicon carbide semiconductor layer, and (b) implanting predetermined ion in the silicon carbide semiconductor layer at a predetermined implantation energy by using the implantation mask. In the step (a), the implantation mask is formed such that a length from any point in the unit mask to an end of the unit mask can be equal to or less than a scattering length obtained when the predetermined ion is implanted in silicon carbide at the predetermined implantation energy and the implantation mask can have a plurality of regions different from each other in terms of a size and an arrangement interval of the unit masks.

Abstract: A semiconductor device is formed by providing a substrate and forming a semiconductor-containing layer atop the substrate. A mask having a plurality of openings is then formed atop the semiconductor-containing layer, wherein adjacent openings of the plurality of openings of the mask are separated by a minimum feature dimension. Thereafter, an angled ion implantation is performed to introduce dopants to a first portion of the semiconductor-containing layer, wherein a remaining portion that is substantially free of dopants is present beneath the mask. The first portion of the semiconductor-containing layer containing the dopants is removed selective to the remaining portion of semiconductor-containing layer that is substantially free of the dopants to provide a pattern of sublithographic dimension, and the pattern is transferred into the substrate to provide a fin structure of sublithographic dimension.

Abstract: Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts.

Abstract: A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9, and each of the units 10 has an external output electrode 4 independently of each other. Bumps 11 (the diameter is from several tens to several hundreds of ?m) are formed only on the external output electrodes 4 of non-defective units among the units 10 formed on the SiC chip 9, meanwhile bumps are not formed on the external output electrodes 4 of defective units in which the withstand voltage is too low, or the leakage current is too much.

Abstract: Nanoporous substrate with fine pores having a diameter from 3 to 40 nm arranged with less than 60 nm periodicity is prepared by a method comprising the steps of coating amphipathic block copolymer on a substrate, forming a film containing hydrophilic cylinders aligned perpendicularly to the surface of the film on a substrate, and immersing the substrate into a solution containing an etchant.

Abstract: A direct write lithography system. The system includes a converter having an array of light controllable electron sources, each field emitter being arranged for converting light into an electron beam, the field emitters having an element distance between each two adjacent field emitters, each filed emitter having an activation area. A plurality of individually controllable light sources, each light source arranged for activating one field emitter. A controller controls each light source individually. Each electron beam is focused from the field emitters with a diameter smaller than the diameter of a light source on an object plane.

Abstract: A single crystal semiconductor layer is provided over a base substrate with a second insulating film, a first conductive film, and a first insulating film interposed therebetween; an impurity element having one conductivity type is selectively added to the single crystal semiconductor layer, using a first resist mask; the first resist mask is removed; a second conductive film is formed over the single crystal semiconductor layer; a second resist mask having a depression is formed over the second conductive film; a first etching is performed on the first insulating film, the first conductive film, the second insulating film, the single crystal semiconductor layer, and the second conductive film, using the second resist mask; and a second etching with accompanying side-etching is performed on a part of the first conductive film to form a pattern of a gate electrode layer.

Abstract: To provide a laser irradiation apparatus which performs alignment of an irradiated object and emits a laser beam precisely, a laser irradiation method, and a manufacturing method of a TFT with high reliability with the use of a method for precisely targeting a desired irradiation position of the laser beam. A substrate with marker is mounted on a stage formed using a material which transmits infrared light; a marker, which is provided in the substrate with marker mounted on the stage, is detected using a camera capable of sensing infrared light, and a position of the stage is controlled; a laser beam is emitted from a laser oscillator; the laser beam emitted from the laser oscillator is processed into a linear shape by an optical system, and the substrate with marker mounted on the stage is irradiated with the laser beam.

Abstract: A method for forming fine patterns in a semiconductor device includes forming a first hard mask layer over an etch target layer, forming first etch mask patterns having negative slopes over the first hard mask layer, thereby forming a resultant structure, forming a first material layer for a second etch mask over the resultant structure, performing a planarization process until the first etch mask patterns are exposed to form second etch mask patterns filled in spaces between the spacers, removing the spacers, and etching the first hard mask layer and the etch target layer using the first etch mask patterns and the second etch mask patterns.

Abstract: Methods for fabricating sublithographic, nanoscale arrays of openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Embodiments of the invention use a self-templating or multilayer approach to induce ordering of a self-assembling block copolymer film to an underlying base film to produce a multilayered film having an ordered array of nanostructures that can be removed to provide openings in the film which, in some embodiments, can be used as a template or mask to etch openings in an underlying material layer.

Abstract: A process for preparing a phase change memory semiconductor device comprising a (plurality of) nanoscale electrode(s) for alternately switching a chalcogenide phase change material from its high resistance (amorphous) state to its low resistance (crystalline) state, whereby a reduced amount of current is employed, and wherein the plurality of nanoscale electrodes, when present, have substantially the same dimensions.

Abstract: A method for fabricating an integrated circuit device is disclosed. The method is a lithography patterning method that can include providing a substrate; forming a protective layer over the substrate; forming a conductive layer over the protective layer; forming a resist layer over the conductive layer; and exposing and developing the resist layer.

Abstract: Disclosed are embodiments of a lithographic patterning method that incorporates a combination of photolithography and self-assembling copolymer lithography techniques in order to create, on a substrate, a grid-pattern mask having multiple cells, each with at least one sub-50 nm dimension. The combination of different lithographic techniques further allows for precise registration and overlay of the individual grid-pattern cells with corresponding structures within the substrate. The resulting grid-pattern mask can then be used, in conjunction with directional etch and other processes, to extend the cell patterns into the substrate and, thereby form openings, with at least one sub-50 nm dimension, landing on corresponding in-substrate structures. Once the openings are formed, additional structures can be formed within the openings.

Abstract: An interconnection architecture, for a semiconductor device (having regions arranged to include at least an inner region, an intermediate region located at least aside the inner region, and an outer region located at least on a side of the intermediate region opposite to the inner region, includes: one or more pairs of first and second signal lines, each pair extending from the inner region into the intermediate region; first portions and second portions of the first and second signal lines being parallel, respectively, the first portions being located in the inner region; the first and second portion of at least the first signal line not being collinear; and an intra-pair line-spacing, d(i), for each pair including the following magnitudes, d2 in the inner region, and d2? in the intermediate region, where d2<d2?.

Abstract: In a method of making device of a display, an insulating layer, a semiconductor layer, an ohmic contact layer, a second conductive layer, and a photoresist pattern are consecutively formed on a first conductive structure. The photoresist pattern includes a first thickness region, and a second thickness region outside the first thickness region. The thickness of the second thickness region is smaller than that of the first thickness region. In addition, in a gate driver on array (GOA) of a display, it includes a gate driver on array structure with a pull-down transistor. The pull-down transistor has a gate electrode, a semiconductor island, a source electrode and a drain electrode. The semiconductor island extends out of the edges of the gate electrode, the source electrode, and the drain electrode.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.

Abstract: Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.

Abstract: To provide a laser irradiation apparatus which performs alignment of an irradiated object and emits a laser beam precisely, a laser irradiation method, and a manufacturing method of a TFT with high reliability with the use of a method for precisely targeting a desired irradiation position of the laser beam. A substrate with marker is mounted on a stage formed using a material which transmits infrared light; a marker, which is provided in the substrate with marker mounted on the stage, is detected using a camera capable of sensing infrared light, and a position of the stage is controlled; a laser beam is emitted from a laser oscillator; the laser beam emitted from the laser oscillator is processed into a linear shape by an optical system, and the substrate with marker mounted on the stage is irradiated with the laser beam.

Abstract: A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.

Abstract: An apparatus for manufacturing a liquid crystal display device is disclosed. A first robot arm at a loading side of the thru-conveyor receives a substrate coated with photoresist and conveys the substrate to a thru-conveyor. A softbake hot plate (SHP) at the unloading side of the thru-conveyor removes solvent from the substrate. A cool plate lowers the substrate temperature from which the solvent is removed. A buffer temporarily stores the substrate having the lowered temperature. A second robot arm between the thru-conveyor, the SHP, the cool plate and a loading side of the buffer, loads/unloads the substrate. A temperature control unit adjusts the substrate temperature unloaded from the buffer. A third robot arm between the unloading side of the buffer, the temperature control unit and an exposure unit that exposes the substrate, loads/unloads the substrate.

Abstract: Etching is performed on an insulating layer 23 and a conductive layer 32 with a photoresist 41 as the mask, to form an opening 51 in the conductive layer 32. After removing the photoresist 41, another insulating layer 24 is formed all over, which is etched back so as to expose a surface of a conductive layer 31, to thereby cover the inner wall of the opening 51. Then etching is performed on the conductive layer 31 with the latter insulating layer 24 as the mask, so as to form another opening 52 in the conductive layer 31. Then still another insulating layer 25 is formed all over, which is then etched back so as to expose a surface of the conductive layer 32, to thereby fill the opening 52 with the last formed insulating layer 25.

Abstract: The present invention describes An RFID antenna manufacturing system whereby the RFID antenna becomes an integral part of an integrated circuit package. The RFID manufacturing system contemplated by this invention includes photoresist manufacturing techniques to produce a template or die specifically designed to mass produce RFID transponders whereby the chip and antenna becomes one integrated unit. The RFID antenna template or die is precisely tuned, using trimming algorithms and laser technology, to resonate with electro magnetic signal increments of 2 megahertz. According to this system each electro magnetic signal increment is assigned to a different category in a supply chain. This invention reduces the cost, size and weight of prior art RFID transponders. This invention reduces signal to noise ratio by producing precisely tuned antennas which provide a gatekeeper function directly correlated to ambient electro magnetic signals.

Abstract: A production method for a semiconductor device includes providing a semiconductor substrate having semiconductor layer of a first conductivity type formed on a surface thereof; forming a first mask so as to cover a predetermined region of the semiconductor layer; (c) forming a well region of a second conductivity type by implanting impurity ions of the second conductivity type into the semiconductor layer having the first mask formed thereon; reducing the thickness of the first mask by removing a portion of the first mask; forming a second mask covering a portion of the well region by using photolithography; and forming a source region of the first conductivity type by implanting impurity ions of the first conductivity type into the semiconductor layer having the first mask with the reduced thickness and the second mask formed thereon.

Abstract: A method of fabricating a non-volatile memory device having a charge trapping layer includes forming a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer over a substrate, forming a mask layer pattern on the control gate electrode layer, performing an etching process using the mask layer pattern as an etching mask to remove an exposed portion of the control gate electrode layer, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness, forming an insulating layer for blocking charges from moving on the control gate electrode layer and the mask layer pattern, performing anisotropic etching on the insulating layer to form an insulating layer pattern on a sidewall of the control gate electrode layer and a partial upper sidewall of the blocking layer, and performing an etching process on the blocking layer exposed by the anisotropic etching, wherein the etching process is performed as excessive etching to

Abstract: In extremely scaled semiconductor devices, an asymmetric transistor configuration may be established on the basis of tilted implantation processes with increased resist height and/or tilt angles during tilted implantation processes by providing an asymmetric mask arrangement for masked transistor elements. For this purpose, the implantation mask may be shifted by an appropriate amount so as to enhance the overall blocking effect for the masked transistors while reducing any shadowing effect of the implantation masks for the non-masked transistors. The shift of the implantation masks may be accomplished by performing the automatic alignment procedure on the basis of “shifted” target values or by providing asymmetrically arranged photolithography masks.

Abstract: A method for fabricating a semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second mask pattern having a first portion and a second portion over the etch target layer in the peripheral region, forming a photoresist pattern over the cell region, trimming the first portion of the second mask pattern, removing the photoresist pattern and the second portion of the first mask pattern and the second portion of the second mask pattern, and etching the etch target layer to form a pattern in the cell region and a pattern in the peripheral region.

Abstract: There is provided a method for pattern formation, including a step of coating a composition comprising a block copolymer, a silicon compound, and a solvent for dissolving these components onto an object to form a layer of the composition on the object, a step of subjecting the layer of the composition to self-organization of the block copolymer to cause phase separation into a first phase, in which the silicon compound is localized, having higher etching resistance by heat treatment or/and oxygen plasma treatment, and a second phase comprising a polymer phase and having lower etching resistance by heat treatment or/and oxygen plasma treatment, and thereby forming a pattern layer with a fine pattern, and a step of etching the object using as a mask the thus formed pattern layer.

Abstract: A method for forming a trench-gated field effect transistor (FET) includes the following steps. Using a first mask, defining and simultaneously forming a plurality of active gate trenches and at least one gate runner trench extending to a first depth within a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench; and using the first mask and a second mask for protecting the at least one gate runner trench, further extending only the plurality of active gate trenches to a second and final depth within the silicon region.

Abstract: In a method for forming hard mask patterns of a semiconductor device first hard mask patterns are formed on a semiconductor substrate. Second hard mask patterns are formed and include first patterns which are substantially perpendicular to the first hard mask patterns and second patterns which are positioned between the first hard mask patterns. Third hard mask patterns are formed between the first patterns.

Abstract: A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9, and each of the units 10 has an external output electrode 4 independently of each other. Bumps 11 (the diameter is from several tens to several hundreds of ?m) are formed only on the external output electrodes 4 of non-defective units among the units 10 formed on the SiC chip 9, meanwhile bumps are not formed on the external output electrodes 4 of defective units in which the withstand voltage is too low, or the leakage current is too much.

Abstract: A wafer fabrication method includes a first step of forming a plurality of first channel regions in a first region on a surface of a water, a second step of forming a plurality of second channel regions having an impurity concentration different from an impurity concentration of the first channel regions, a third step of forming a plurality of third channel regions in a third region on the surface of the water, and a fourth step of forming a plurality of fourth channel regions having an impurity concentration different from an impurity concentration of the third channel regions in a fourth region, wherein the first region and the second region are divided by a first line segment on the wafer, and the third and fourth regions are divided by a second line segment intersecting with the first line segment on the wafer.

Abstract: A method of correcting for pattern run out in a desired pattern in directional deposition or etching comprising the steps of providing a test substrate; providing a stencil of known thickness on the test substrate; providing a stencil pattern extending through the stencil to the test substrate.

Abstract: A method for manufacturing a semiconductor device of the present invention includes: forming a first film, a second film and a third film in sequence on a silicon substrate; patterning a resist film formed on the third film by conducting an exposure and developing process for the resist film employing an exposure mask including a phase shifter; selectively dry-etching the third film through a mask of the resist film employing the second film as an etch stop to process the third film into a first pattern; further dry-etching the third film employing the second film as an etch stop to partially remove the third film, thereby processing the third film into a second pattern; patterning the second film employing the third film having the second pattern as a mask; and patterning the first film employing the patterned second film as a mask.

Abstract: Forming structures such as fins in a semiconductor layer according to a pattern formed by oxidizing a sidewall of a layer of oxidizable material. In one embodiment, source/drain pattern structures and a fin pattern structures are patterned in the oxidizable layer. The fin pattern structure is then masked from an oxidation process that grows oxide on the sidewalls of the channel pattern structure and the top surface of the source/drain pattern structures. The remaining oxidizable material of the channel pattern structure is subsequently removed leaving a hole between two portions of the oxide layer. These two portions are used in one embodiment as a mask for patterning the semiconductor layer to form two fins. This patterning also leaves the source/drain structures connected to the fins.

Abstract: Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a plurality of first test patterns having a first phase shift and at least one plurality of second test patterns having at least one second phase shift. The layer of photosensitive material of the workpiece is developed, and features formed on the layer of photosensitive material from the plurality of first test patterns and the at least one plurality of second test patterns are measured to determine a optimal focus level or optimal dose of the lithography system for exposing the layer of photosensitive material of the workpiece.

Abstract: One possible embodiment is a method of manufacturing a structure on or in a substrate with the following steps a) positioning at least one spacer structure by a spacer technique on the substrate, b) using at least one of the groups of the spacer structure and a structure generated by the spacer structure as a mask for a subsequent particle irradiation step for generating a latent image in the substrate c) using the latent image for further processing the substrate.

Abstract: Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts.

Abstract: A method for manufacturing a flexible display, includes forming a gate line including a plurality of gate electrodes with a first interval on a substrate having a coefficient of thermal expansion, sequentially depositing both a gate insulating layer covering the gate line and a semiconductor layer, etching the semiconductor layer by using a mask having a plurality of semiconductor patterns with a second interval different from the first interval to form a semiconductor, forming both a data line including a source electrode and a drain electrode on the semiconductor and the gate insulating layer, and forming a pixel electrode coupled with the drain electrode.

Abstract: A method of forming a semiconductor device includes depositing a fill material (4) on a substrate portion (2) and on a dielectric layer (3) being disposed on the substrate (1) and having an opening (10) located above the substrate portion (2), removing the fill material (4) disposed above the dielectric layer (3), thereby leaving an exposed top surface (6) of the dielectric layer (3) and residual fill material (15) within the opening (10), forming a hard mask material (5) on the exposed top surface (6) of the dielectric layer (3) and on the residual fill material (15), patterning the hard mask material (5) for forming a hard mask (25) having trenches (8a, 8b) extending along a lateral direction (X) and exposing portions of the residual fill material (15) adjacent to the dielectric layer (3) and portions of the dielectric layer (3) adjacent to the residual fill material (15), anisotropically etching the dielectric layer (3), the residual fill material (15) and the substrate (1) selectively to the hard mask (5)

Abstract: A method for fabricating a semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second mask pattern having a first portion and a second portion over the etch target layer in the peripheral region, forming a photoresist pattern over the cell region, trimming the first portion of the second mask pattern, removing the photoresist pattern and the second portion of the first mask pattern and the second portion of the second mask pattern, and etching the etch target layer to form a pattern in the cell region and a pattern in the peripheral region.

Abstract: Provided is a method of manufacturing a semiconductor device using double patterning. The method includes: forming a first material layer pattern having recesses in a first direction on an object layer and a second material layer pattern formed on the first material layer pattern; selectively etching the second material layer pattern and the first material layer pattern in a direction perpendicular to the first direction to form an etching mask; and etching the object layer to form minute patterns.

Abstract: A transmissivity controlled film 12 (CrO or the like), a transmissivity reduced film 13 (Cr or the like), and a resist film 14, for instance, are sequentially formed on, e.g., a transparent substrate 11. A resist is removed from an area (an area C) where a light-transmission section is to be formed, and the transmissivity reduced film 13 and the transmissivity controlled film 12 are removed from the area, thereby forming a light-transmission section. Next, a resist is removed from an area (an area A) in which a graytone section is to be formed, thereby removing the transmissivity reduced film 13 from that area, to thereby form a graytone section. Thus, a graytone mask is manufactured.

Abstract: Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts.

Abstract: A method for manufacturing a shallow trench isolation (STI) structure is provided. In the method, a substrate is initially provided. Then, a patterned pad layer and a patterned mask layer are successively formed in order on the substrate. After that, a portion of the substrate is removed by using the patterned mask layer and the patterned pad layer as a mask to form trenches in the substrate. Next, a first insulation layer is formed in the trenches. Afterwards, a protection layer is conformally formed on the substrate. Then, a second insulation layer is formed on the protection layer above the first insulation layer. Next, the patterned mask layer and the patterned pad layer are removed. Finally, a portion of the protection layer and the second insulation layer are removed.

Abstract: A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; forming a hard mask layer over the substrate; forming protected portions and unprotected portions of the hard mask layer; performing a first etching process, a second etching process, and a third etching process on the unprotected portions of the hard mask layer, wherein the first etching process partially removes the unprotected portions of the hard mask layer, the second etching process treats the unprotected portions of the hard mask layer, and the third etching process removes the remaining unprotected portions of the hard mask layer; and performing a fourth etching process to remove the protected portions of the hard mask layer.

Abstract: According to an aspect of the invention, there is provided a semiconductor device fabrication method including forming a first mask on a semiconductor substrate, processing the first mask to form a first mask pattern of a fine portion, forming a second mask on the semiconductor substrate on which the first mask pattern is formed, forming a second mask pattern on a predetermined portion of the second mask, forming a third mask pattern by anisotropically etching the second mask by using the second mask pattern, removing the second mask pattern and the first mask pattern, and processing the semiconductor substrate by using the third mask pattern.

Abstract: Methods for removing photoresist from semiconductor structures are provided. In an exemplary embodiment, a method for removing photoresist from a semiconductor structure having a high-k dielectric material layer overlying a substrate comprises depositing a photoresist overlying the high-k dielectric material layer and patterning the photoresist. The temperature of the substrate is adjusted to a temperature of no less than about 400° C. and hydrogen gas is excited to form a hydrogen plasma of excited H and H2 species. The photoresist is subjected to the excited H and H2 species from the hydrogen plasma.

Abstract: The present invention relates to a method of fabricating a flash memory device. In a method according to an aspect of the present invention, a first hard mask film is formed over a semiconductor laminate. A plurality of first hard mask patterns are formed by etching an insulating layer for a hard mask. Spacers are formed on top surfaces and sidewalls of the plurality of first hard mask patterns. A second hard mask film is formed over a total surface including the spacers. Second hard mask patterns are formed in spaces between the spacers by performing an etch process so that a top surface of the spacers is exposed. The spacers are removed. Accordingly, gate patterns can be formed by employing hard mask patterns having a pitch of exposure equipment resolutions or less.