Abstract: When a through hole 17 is transferred on a pair of contact holes 10 putting a data line DL therebetween, even if a pair of through holes 17 putting the data line DL therebetween are deviated, the pair of through holes are connected to the contact hole 10b and not connected to the data line DL. By this manner, a mask pattern formed by a photomask is use so as to be deviated and disposed in a direction separately from the data line DL at a design stage. This results in improvement of an alignment tolerance of the pattern.

Abstract: This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, and more particularly to a lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template. The lithographic template (10) is formed having a substrate (12), an optional etch stop layer (16) formed on a surface (14) of the substrate (12), and a patterning layer (20) formed on a surface (18) of the etch stop layer (16). The template (10) is used in the fabrication of a semiconductor device (30) for affecting a pattern in device (30) by positioning the template (10) in close proximity to semiconductor device (30) having a radiation sensitive material formed thereon and applying a pressure to cause the radiation sensitive material to flow into the relief image present on the template.

Abstract: A method is provided for forming dual damascene structures with a partial hard mask through a judicious use of partial opening or etching of the mask which simplifies the dual damascene process, and makes it especially suitable for low-k dielectric materials in advanced sub-micron technologies capable of forming features approaching less than 0.10 micrometers (&mgr;m). This is accomplished by forming a hard mask over a low-k dielectric layer. The hard mask is first opened partially to form a trench, and later again to form a via opening. The via opening is next extended into the low-k dielectric layer, followed by etching further the partial trench into the hard mask, and then transferring the trench pattern into the dielectric layer while at the same time extending the via opening to the underlying metal layer.

Abstract: Provided is a mask data correction apparatus that can increase efficiency of processing while maintaining high accuracy by effectively using the hierarchical structure of a layout data. A Fourier transformation part (421) performs Fourier transformation of base elements defined by the layout data, to obtain Fourier images of the base elements. A synthesizing part (422) superimposes, based on the hierarchical structure, the Fourier images of the base elements in Fourier space, to obtain Fourier image of the entire graphic. A spatial filter part (423) subjects the Fourier image of the entire graphic to spatial filter processing that corresponds to distortion expected in a manufacturing process. An inverse Fourier transformation part (424) performs inverse Fourier transformation of the Fourier image after spatial filter processing, to obtain the inverse Fourier image reflecting the distortion.

Abstract: A method for producing a pinhole-free dielectric film comprising applying a photopolymer to a first dielectric surface of a dielectric film having pinholes, exposing a second and opposing surface to an amount of radiation effective to polymerize the photopolymer exposed by the pinholes, and removing unpolymerized photopolymer.

Abstract: A method of forming a partial reverse active mask. A mask pattern comprising a large active region pattern with an original dimension and a small active region pattern is provided. The large active region pattern and the small active region pattern are shrunk until the small active region pattern disappears. The large active region pattern enlarged to a dimension slightly smaller than the original dimension.

Abstract: To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.

Abstract: A resin sealing film is formed on a silicon substrate by using a printing mask and a squeegee. The side surface in the tip portion of the squeegee is substantially V-shaped, and the printing is performed by pushing the tip portion of the squeegee into the gap between adjacent bump electrodes. As a result, the sealing film is formed in a manner to be depressed in the region between adjacent bump electrodes so as to facilitate the swinging movement of the bump electrodes. It follows that, in a temperature cycle test performed after the silicon substrate is mounted to a circuit substrate, the stress derived from the difference in thermal expansion coefficient between the silicon substrate and the circuit substrate is absorbed by the bump electrode.

Abstract: A semiconductor device with an improved speed response has a linear ridge pattern including an active layer, a cladding layer, a current blocking layer, and a contact layer on a semiconductor substrate. The insulating layer may be formed in a pattern having a high resistance to dry etching along a longitudinal side of the ridge pattern.

Abstract: A method of fabricating a mask forms a rectangular opening within etch resistant material that overlays a substrate. The mask preferably comprises two layers of photoresist separated by a layer of light blocking material. One of the layers of photoresist is patterned per a longitudinal exposure strip, and the other per an overlap of a lateral exposure strip with the longitudinal exposure strip, so as to provide an opening for the mask where the two overlap. With this mask over a substrate, the substrate is etched to form a container therein with a rectangular cross-section corresponding to the aperture of the mask. The container is then lined with electrically conductive material, dielectric, and electrically conductive material respectively to form a capacitor in the container—e.g., a container-cell capacitor for a DRAM device.

Abstract: A plurality of uniform bumps are formed on a semiconductor device by forming a mask onto the surface of the semiconductor device with openings in the mask that correspond to the electrical contact pads on the surface of the semiconductor device. Solder or other conductive material is deposited on the pads. A rate of solder or other conductive material deposition which may not give a uniform thickness of solder or other conductive material across the surface of the wafer may be used. Solder or other conductive material is deposited until each opening in the mask is filled with solder or other conductive material. Next, the mask and solder or other conductive material balls formed are scrubbed until the mask and the soldier balls reach a substantially uniform height. The openings formed in the mask have substantially the same footprint or area associated with each pad.

Abstract: An etching mask is made of a metal such as Permalloy (NiFe) and has a T-shaped cross section made up of a vertical bar having width W1 and a lateral bar having width W2. Through ion beam etching with the etching mask, the region in the surface of a workpiece not covered with the mask is selectively removed by the ion beams applied thereto. In the mask the vertical bar has a region obstructed by the lateral bar and a redeposit portion. As a result, the region of the vertical bar near the interface between the workpiece and the vertical bar that substantially determines the pattern width does not change in width. Consequently, a pattern of the workpiece on which etching has been performed has the top width and bottom width substantially equal to width W1 of the vertical bar of the mask. The pattern is rectangular in cross section.

Abstract: A semiconductor device includes a lead frame, a semiconductor chip, a resin-encapsulated portion, and tie bars. The semiconductor chip is mounted on a die pad of the lead frame. The resin-encapsulated portion resin-encapsulates the semiconductor chip. The tie bars are provided to outer lead portions of the lead frame to prevent resin leakage during resin encapsulation, and are cut and removed in a finishing step of resin encapsulation. A plating surface is formed on a sectional surface of each of the tie bars. A semiconductor device manufacturing method and apparatus are also disclosed.

Abstract: The present invention is directed to a method and process to reduce plasma etch fluting during etching of a pattern on a semiconductor substrate by modifying the resist profile. The present invention forms a resist structure profile having an overhang or undercut, which is not in contact with the surface of the substrate. The overhang results in a shadowed region on the substrate from the primary etch direction adjacent to the base of the resist structure. Since the overhang is not in direct contact with the substrate surface, the resist pattern does not transfer into the surface of the substrate during etching and fluting is reduced or eliminated.

Abstract: A passivating layer (220) is formed overlying portions of a mask (200). The mask (200) is used to pattern a semiconductor device substrate (62). In accordance with one embodiment of the present invention, the passivating layer (220) is removed prior to patterning the semiconductor device substrate (62). In yet another embodiment, the passivating layer (220) is cleaned prior to patterning the semiconductor device substrate (62) and then left to remain overlying portions of the mask (200) during the patterning process.

Abstract: Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of active area formed within the semiconductive substrate which are continuous between adjacent memory cells, said adjacent memory cells being isolated from one another relative to the continuous active area formed therebetween by a conductive line formed over said continuous active area between said adjacent memory cells. At least some adjacent lines of continuous active area within the array are isolated from one another by LOCOS field oxide formed therebetween. The respective area consumed by individual of said adjacent memory cells is ideally equal to less than 8F2, where “F” is no greater than 0.

Abstract: A hard resist layer is formed on and/or within a deep-UV configured resist mask prior to patterning a semiconductor device feature. The hard resist layer reduces the amount of polymer residue generated during the patterning process, which can effect the resulting profile of the device feature. The hard resist mask is formed by either ion implantation or plasma treatments. Due to the formation of the hard resist layer, the thickness of the resist mask can be reduced, thereby increasing the resolution capabilities of the resist mask.

Abstract: In one embodiment, a masking chuck (68) is placed in contact with an integrated circuit structure (70) that contains conductive members (90). The masking chuck (68) is used to deposit a dielectric layer (92) on the integrated circuit structure (70). The dielectric layer (92) is then cured, and the masking chuck (68) is separated from the integrated circuit structure (68) to define openings (96) within the dielectric layer (92) which expose a portion of the underlying conductive members (90). A conductive layer (100) is then deposited in the openings (96), and polished to form conductive members (102) within the openings (96), which are electrically shorted to the underlying conductive members (90).

Abstract: An optical semiconductor device of the present invention is provided with a core layer having a quantum well layer in that film thickness gets thinner from a inner region to an end portion in an optical waveguide region.

Abstract: A structure is provided comprising a semiconductor substrate, a gate oxide layer on the substrate, and a polysilicon layer on the gate oxide layer. A masking layer is formed on the polysilicon layer. The masking layer is then patterned into a mask utilizing conventional photolithographic techniques, but without patterning the polysilicon layer. The photoresist layer is then removed, whereafter the mask, which is patterned out of the masking layer, is utilized for patterning the polysilicon layer. The use of a carbon free mask for patterning the polysilicon layer, instead of a conventional photoresist layer containing carbon, results in less breakthrough through the gate oxide layer when the polysilicon layer is patterned. Less breakthrough through the gate oxide layer allows for the use of thinner gate oxide layers, and finally fabricated transistors having lower threshold voltages.

Abstract: A method for fabricating a high power laser diode device with an output emission with a nearly circular mode profile for efficient coupling into an optical fiber. A vertical taper waveguide and a window tolerance region are formed in a base structure of the device employing successive etching steps. Further regrowth completes the device structure. The resultant laser device has a vertical and lateral tapered waveguide that adiabatically transforms the highly elliptical mode profile in an active gain section of the device into a substantially circular mode profile in a passive waveguide section of the device.

Abstract: A method for effectively generating limited trench width isolation structures without incurring the susceptibility to dishing problems to produce high quality ICs employs a computer to generate data representing a trench isolation mask capable of being used to etch a limited trench width isolation structure about the perimeter of active region layers, polygate layers, and Local Interconnect (LI) layers. Once the various layers are defined using data on the computer and configured such that chip real estate is maximized, then the boundaries are combined using, for example, logical OR operators to produce data representing an overall composite layer. Once the data representing the composite layer is determined, the data is expanded evenly outward in all horizontal directions by a predetermined amount, .lambda., to produce data representing a preliminary expanded region.

Abstract: A process of forming on an integrated circuit substrate at least two different gate masks having different lengths is described. The process includes: (i) providing the integrated circuit substrate having a surface; (ii) depositing on the surface a gate layer; and (iii) masking portions of the gate layer using a reticle having at least two die patterns including a first die pattern defining an image of a first gate electrode having a first length and a second die pattern defining an image of a second gate electrode having a second length, the first length being different from the second length and relative positioning of the image of the first gate electrode in the first die pattern and of the image of second gate electrode in the second die pattern is substantially similar.

Abstract: A semiconductor processing system comprising a semiconductor processing chamber, a light, a temperature detector, and a member. The light is positioned to heat the confines of the chamber. The temperature detector measures the temperature at the location within the chamber. The member has a translucent quartz shell and opaque core and shields the location from light emanating from the light source.

Abstract: The invention is a method of fabricating a self-aligned, sub-minimum guard ring for a Schottky diode device wherein the sub-minimum guard ring is positioned at the inside edges of adjacent isolation structures and is self-aligned to the intrinsic base implanted regions. In this particular invention, illustrating the guard ring fabrication technique, an improved Schottky diode is fabricated at minimum groundrules which utilizes a frequency-doubling resist and an appropriate mask to provide the implant mask for a p- or n-type guard ring. This shallow implant near the surface prepares a guard ring that minimizes the electric field at the interface where the deposited metal or silicide joins the STI structure. Additional ion implants with energies greater than and less than the guard ring implantation energy may be deposited to tailor the substrate surface and reduce the parasitic capacitance of the diode.

Abstract: A method of fabricating a semiconductor device includes etching holes through at least one deposited layer to an underlying structure. A hard mask is deposited on an upper surface of a device to be etched, the mask is patterned with the aid of a photoresist, and holes are etched in the hard mask. After removal of the photoresist, contact or via holes are etched through the patterned hard mask in the deposited layer(s) to reach the underlying structure.

Abstract: A method of manufacturing a bipolar transistor in an integrated circuit including the steps of forming a P-type base area, coating this base area with an isolating layer, and forming an opening in the isolating layer at a location where it is desired to form the emitter region. The method further includes coating the structure with an N-type doped polysilicon layer, etching the polysilicon layer to delimit a portion therefrom, forming spacers at a periphery of the polysilicon portion, and implanting a P-type dopant to form a base contact making region, after masking the polysilicon portion, above the area where it is in contact with the base area.

Abstract: A method for forming semiconductor devices involves nebulizing a liquid suspension of particles to form tiny droplets of particles and liquid which are well separated from one another. The nebulized droplets may correspond roughly to the average particle size which may be, for example, about one to two microns. The particles in droplet form then form a vaporous dispersion which can be dried to remove the liquid. The particles may be biased so as to repel one another to further form a well defined separation between adjacent particles. The particles may then be collected on a substrate so that a random distribution of masking particles are formed. The randomly distributed particles may be used as a mask for defining features in a semiconductor structure. The mask may be utilized, for example, to define emitters in a field emission display or spacers in a liquid crystal display.

Abstract: A method for forming square shape images in a lithographic process is disclosed wherein a first plurality of lines running in a first direction is defined in a first, usually sacrificial, layer, and then a second resist is defined wherein the lines run in an intersecting pattern to those of the first layer, thereby creating cornered images wherever the first and second layer intersect and in the open areas between the lines. Methods are proposed for developing the square intersecting areas and the square angle areas defined by the openings. Additionally, a photomask is disclosed in which the length and width of the cornered images are independently patterned using the two-exposure process.

Abstract: An improved semiconductor device including an MOS capacitance is provided, having enhanced MOS capacitance accuracy. A well of a first conductivity type is formed at the main surface of a semiconductor substrate. The above-described well is removed immediately under a capacitance dope layer.

Abstract: A two-terminal current limiting component, includes a substrate of a first conductivity type; separated wells of the second conductivity type; a first annular region of the first conductivity type in each well; a second annular region of the first conductivity type having a low doping level between the periphery of each first annular region and the periphery of each well; an insulating layer over the second annular region and the surface portions of the substrate; a first metallization coating the upper surface of the component; and a second metallization coating the lower surface of the component.

Abstract: A method for fabricating a multi-level integrated circuit is disclosed which utilizes a grid pattern from which portions corresponding to the metal layer are selectively removed to form a mask which is subsequently used to deposit dummy features in the open areas between metal lines, thereby to allow the deposition of a substantially planar dielectric surface over the metal layers and dummy features.

Abstract: In an embodiment of a method of manufacturing semiconductor integrated circuit devices according to the present invention, word lines are provided in a straight form, which serve as gate electrodes of two selecting MOSFETs formed symmetrical about a center portion of an active region surrounded by a LOCOS oxide film on a semiconductor substrate, and bit lines have straight segments and protruding segments. Each protruding segment is formed to protrude from the bit line and is connected through a first contact hole to a first semiconductor region formed at the center portion of the active region. The straight line segments and the protruding segments are formed separately by two separate exposure steps.

Abstract: A method for manufacturing phase-shifting masks utilizing a photolithographic process and sidewall spacers to fabricate a phase-shifting layer. The method provides precise control over the shape and size of the resulting phase-shifting layer, and thus, simplifies photomask production.

Abstract: In a method for manufacturing a semiconductor device having a sharp step portion, a mask pattern to perform a patterning process of a photoresist layer is formed so that the dimension of the mask pattern is set to be larger than a design value of the corresponding wiring pattern only at a region where the thickness of the photoresist layer is different from that at a flat portion, and the mask pattern dimension at the flat portion which is away from the step portion is set to a design value of the corresponding wiring pattern. By using the mask pattern thus formed, the wiring dimension in the vicinity of the step portion can be prevented from becoming smaller than that at the flat portion under the condition that the wiring dimension of the design value can be obtained at the flat portion, so that the wirings can be formed according to the design value at any place containing the portion in the vicinity of the step portion and the flat portion.

Abstract: A waveguide type semiconductor photodetecting device has a semiconductor substrate, a photodetecting element, and a waveguide optically coupled with the photodetecting element which can avoid occurrence of light loss in the tapered waveguide even when a width of a light inciding side of the tapered waveguide is widened. The waveguide has a waveguide layer gradually narrowing a width and gradually increasing a layer thickness and a refraction index from light incident side to the photodetecting element. The waveguide is integrated with the photodetecting element on the semiconductor substrate.

Abstract: A new method for forming a feature having a feature size of one half the resolution of the photolithography process by adjusting the etching conditions is achieved. A capping oxide layer is deposited overlying the feature layer. A first layer of photoresist is patterned using a photolithography process to provide a first photomask having a first feature size. The oxide layer is etched vertically through no more than half of its thickness and the photomask and oxide layer are etched horizontally to provide a first oxide mask having a second feature size one half the width of the first feature size. The first photomask is removed. A second photoresist layer is patterned to provide a second photomask for forming the second feature wherein the second photomask has a first feature size and is shifted horizontally by twice the desired feature size from the first photomask.

Abstract: In a fine processing method for forming a silicon substrate, first, an oxynitride layer is formed on the silicon substrate. Thereafter, a silicon nitride layer is formed on the oxynitride layer and patterned into a predetermined shape to cause it to function as an etching mask. The silicon substrate is etched through the etching mask. In this case, because of the oxynitride layer formed between the silicon substrate and the silicon nitride layer, an interface between the silicon substrate and the silicon nitride layer is not easily eroded in the etching process. As a result, processing accuracy of the substrate is improved.

Abstract: A base is etched using as mask a first masking layer which has been patterned, softened and deformed. Then, the first masking layer is eroded, a second masking layer is selfaligningly formed only on bare portions of the base, and the base is again etched using as mask the second masking layer. Within a pitch of the first masking layer, the base can thus be etched in two regions which are separated from each other. These treatments can also be conducted in two directions.

Abstract: A method for producing a small feature in a semiconductor device includes depositing a mask material on an unpatterned layer in which an ultra-narrow opening is to be formed, and then masking and etching the mask material to form a narrow opening. A spacer material is then deposited on the mask material, with spacer material settling into and covering the narrow opening. Thereafter, a portion of the spacer material is removed by etching, leaving some spacer material in the opening but exposing an ultra-narrow region of the first layer at the bottom of the opening in the mask material. The ultra-narrow region left uncovered by the spacer material is smaller than the narrow region in the mask material. Once the ultra-narrow region is uncovered, material in the first layer is removed through the ultra-narrow region, by anisotropic etching, for example, to form an ultra-narrow opening in the first layer.

Abstract: Apparatus and methods are disclosed for increasing the illuminance at a mask used for proximity-type microlithography and for achieving increases in throughput. A mask defining a pattern is illuminated by an illumination optical system. The pattern is transferred to a workpiece separated from the mask by a prescribed standoff. The mask and workpiece can be relatively moved in a scan direction. With respect to the illumination optical system, the workpiece-side numerical aperture in a first direction on the plane of the mask is different from the workpiece-side numerical aperture in a second direction, perpendicular to the first direction, on the plane of the mask. A reflective-type relay optical system can be included that comprises first and second spherical mirrors that do not produce chromatic aberrations.

Abstract: A process for bulk micromachining a silicon wafer to form a silicon micromachined structure. The process involves the application of a protective film on one or more surfaces of the silicon wafer to protect metallization and circuitry on the wafer during the bulk micromachining process, during which a wet chemical etchant is employed to remove bulk silicon from a surface of the silicon wafer. The protective film is divinylsiloxane bisbenzocyclobutene (BCB), which has been found to be highly resistant to a wide variety of wet chemical etchants, and retains such resistant at elevated temperatures commonly preferred for bulk silicon etching. The degree to which this material is cured prior to etching is advantageously tailored to promote its resistance to the etchant and promote its adhesion to the silicon wafer.

Abstract: An auxiliary device is constituted by a U-bolt-shaped, pincer-like implement which, during the fabrication of semiconductor devices with a mesa structure from a starting substrate forming a wafer, serves to transfer the outline geometry of the individual semiconductor devices from one side of the wafer to the back of the wafer. The implement has at least one tracer at the end of one of its arms for engaging a sawed groove and for guiding the implement along the sawed groove on one side of the wafer. At the end of the other arm, a marking device with at least one marking stylus is provided whereby the course of the at least one sawed grooved can be transferred from the front side of the wafer to the back, and scribed there in the form of auxiliary lines.

Abstract: A process has been developed which allows contact between levels of interconnect metallization structures, to occur without the use of via holes, etched in interlevel insulator layers. The process features creation of a raised tungsten plug structure, used to provide contact between underlying active device regions and an overlying interconnect metallization structure. The tungsten plug structure is formed by photolithographic masking and dry etching procedures, thus avoiding increasing the size of a tungsten seam, in the center of the plug structure. In addition the tungsten definition process, also results in a raised plug structure, allowing subsequent contact of interconnect metallization levels to proceed without the use of etched via holes in interlevel insulator layers.

Abstract: This invention relates to methodology to resolve the problem of low drain/source breakdown voltage (BVdss) in small geometry devices with thin gate oxide. Improved drain diffusion profile implanting through disjoint NSD/NWELL windows in the extended drain region, This provides essentially an improved lightly diffused (LDD) structure. Further this invention relates to alternative methods to resolve the problem of low drain/source breakdown voltage in other structures which can be achieved by for example, building a number of side wall oxide layers, impurity compensation or oxygen implantation. The improved LDD structure to which this invention relates has a number of advantages when compared with other solutions. It enables high voltage transistors to be fabricated with high drive capability, without additional process steps being required to implement the structure. The inventions will find applications wherever a high voltage capability is required to interface with the outside world.

Abstract: A device and method is provided for programming an output logic level based on one or more revisions to mask layers utilized for forming an integrated circuit. The programmed logic level is represented as a logic value and is output from a device embodied within the integrated circuit formed from the mask layers. Each revision of mask layers is represented as a binary value at bit locations within a revision code output from the present system. The device and method hereof is used to program the system in accordance with an infinite numbers of mask layers and revisions to those mask layers. The programmed output from the system is represented as a revision code of numerous bits output through a pin location extending from the outer surface of a package surrounding the integrated circuit. Ready access to the pin location allows an end user to access and determine a version of integrated circuit product embodied within a sealed package, without opening the package and destroying the enclosed product.

Abstract: A method of fabricating semiconductor devices which eliminates the need to use additional window mask process to expose topographical marks, such as alignment targets, on a wafer when chemical-mechanical polish planarization technique are used to substantially planarize the surface of the wafer prior to metal deposition.