Abstract: A method for simulating an effect of at least one electrical/electronic load includes: providing a controllable power supply unit that is connected to at least one terminal of a control unit; and simulating a first current theoretically flowing through a simulated load at the at least one terminal by drawing a second current from the control unit by the controllable power supply unit or impressing a third current on the control unit by the controllable power supply unit.

Abstract: A computer-implemented method may include defining an input bus signal in a graphical block diagram model by associating the input bus signal with a first group of signals, at least two of the first group of signals having a different data type; defining an output bus signal in the graphical block diagram model by associating the second bus signal with a second group of signals, each of the second group of signals corresponding to one of the first group of signals; defining an input to a non-virtual operation block in the graphical block diagram model as the input bus signal; defining an output to the non-virtual operation block in the graphical block diagram as the output bus signal; and simulating an operation performed on the input bus signal by the non-virtual operation block, the operation being performed on each of the first group of signals and output to each of the second group of signals.

Abstract: A coupled analysis simulation apparatus includes a coupled analysis processing unit configured to perform coupled analysis by performing electromagnetic field analysis and circuit analysis in coordination with each other, the electromagnetic field analysis being performed on a space including conductive layers to which an electronic circuit module is connected, the circuit analysis being performed on the electronic circuit module; a first generating unit configured to generate a virtual conductive part in a section or a region including connection parts connecting the electronic circuit module with the conductive layers; and a second generating unit configured to generate virtual connection parts that virtually connect the virtual conductive part with the conductive layers at positions where the connection parts are connected to the conductive layers.

Abstract: One or more embodiments provide a load balancing solution for improving the runtime performance of parallel HDL simulators. During compilation each process is analyzed to determine a simulation cost based on complexity of the HDL processes. During simulation, processes to be executed in the same simulation cycle are scheduled using the simulation costs computed at compile-time in order to reduce the delay incurred during simulation.

Abstract: A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.

Abstract: In one embodiment, a method is provided for processing a circuit design having first and second sets of ports configured to couple to respective first and second sets of ports of a device on a hardware platform. In a data-acquisition mode, the circuit design is simulated using a user-selectable plug-in that couples the ports of the circuit design to an interface circuit. During the simulation, the interface circuit communicates data between respective ports of the circuit design and ports of the device. In a deployment mode, the circuit design is implemented in the hardware platform, in which the first and second sets of ports of the circuit design are respectively coupled to the first and second sets of ports of the device.

Abstract: A computer software tool comprises a simulated radio frequency transmitter device (6), a simulated radio frequency receiver device (6?) and a shared memory resource (10). The shared memory resource (10) is arranged to receive messages from the simulated transmitter (8) and to pass said messages to the simulated receiver (8?) wherein said messages are in a format understandable by software running on both the simulated radio frequency transmitter device (6) and the simulated radio frequency receiver device (6?).

Abstract: A method and system create a model of a set of relationships between a set of parent computer network objects and a set of corresponding child computer network objects, over a period of time, and output a user interface graphing the model in a single view to illustrate the set of relationships over the period of time. The parent computer network objects include virtual machines and the child computer network objects include hosts. The user interface includes a search option to provide for a search of problems with the child computer network objects over the period of time.

Abstract: A system may be configured to receive a request to generate code based on a model. The model may include a logical entity associated with a variable. The system may further be configured to identify a boundary for the variable based on a code section of the code corresponding to the logical entity and add alignment code to the code. The alignment code may be for the variable and based on the boundary.

Abstract: Generating of the initial temperature value for a simulated annealing process in the placement of circuit components in the physical design of integrated circuit (IC) is based on previous partitioning, if any, of the IC components into bins. An iteration limit value is then assigned equal to the initial temperature value. The simulated annealing process is then performed on a current partitioning of the IC components into bins according to the iteration limit value. The IC components are partitioned further into an exponentially larger total number of smaller bins compared to a previous number of bins. The process is then repeated starting with the operation of generating an initial temperature value for the simulated annealing process until the number of circuit components in each bin is below a specified number.

Abstract: In one embodiment of the invention, a method of simulating a circuit is disclosed including simulating an analog component of the circuit over a first simulation time period with a first envelope simulation; adaptively switching from simulating the analog component with the first envelope simulation to simulating the analog component with a transient simulation over a second simulation time period; and adaptively switching from simulating the analog component with the transient simulation to simulating the analog component with a second envelope simulation over a third simulation time period. The adaptive switching from the first envelope simulation to the transient simulation may be in response to the envelope simulation accuracy falling below a predetermined level of accuracy in comparison with a transient simulation or in response to the second simulation time period including expected digital transitions where one or more digital events may occur to change the analog input signals to the analog component.

Abstract: A system and method for performing circuit simulation is described. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. Mechanisms are provided that allow for viewing, measurement or other manipulation of signals at specific locations in a circuit design for simulation, such as parameters that include observation points which are implemented using probes. One approach to executing a measurement is via a controllable and flexible control statement, which in one embodiment is the “run” statement. Improved interfaces for viewing, controlling, and manipulating simulations and simulation results are also provided.

Abstract: A system and method for measuring various weld characteristics is presented. The system and method can comprise a means to measure penetration depth of butt welds in thin plates, for example, using laser generated ultrasounds. Superimposed line sources (SLS) can be used to generate narrowband ultrasounds. A signal processing procedure that combines wavenumber-frequency (k-?) domain filtering and synthetic phase tuning (SPT) is used to reduce the complexity of Lamb wave signals. The reflection coefficients for different wavelengths corresponding to each wave mode can be calculated. Regression analysis that can include stepwise regression and corrected Akaike's information criterion (AIC) can be performed to build prediction models that use the reflection coefficients as predictors.

Abstract: Provided are a method, system, and computer program product to generate references to reusable code in a schema. A program coded in a first programming language has data structures, wherein at least one of the data structures includes a reference to reusable code. A model file is generated identifying the reusable code, elements and attributes in a second programming language for the reference to the reusable code in the program. The data structure coded in the first programming language is processed to generate a data structure schema in a second programming language describing elements and attributes of the data structure coded in the first programming language. A reference in the data structure schema to the reusable code is generated.

Abstract: A method and system are provided for generating code from a graphical model in a graphical modeling environment. The graphical model includes at least one signal having a data size, a data dimensionality, or both that can vary from a first time instance to a second time instance as the model executes. The size and dimensionality of the signal can vary without the use of a graphically rendered connection to convey the size and dimension information to a block associated with the signal.

Abstract: Exemplary embodiments allow executable graphical models, such as block diagram models, to be graphically partitioned for execution on concurrent computing resources. Embodiments allow model components to be grouped into subtasks that are affiliated with tasks associated with concurrent computing resources. Tasks and sub graphs can be mapped to concurrent computing resources according to characteristics, such as sample time, solver type, etc. Embodiments further allow mappings to be visually indicated to a user via various display techniques including color, text, icons, shading, grouping of identifiers, etc. Concurrently executing portions of a model allows model results to be obtained faster than can be obtained when models are executed on a single computing resource, such as a single processor.

Abstract: A simulation environment for running a process simulation used to validate an industrial control program. The simulation environment exposes the I/O module configurations defined in the control program and retrieves module configuration information therefrom. This I/O module configuration information is combined with generic, module-specific I/O module profiles to create a pool of available controller I/O points, which can be selectively associated with I/O points in the simulation to create an I/O point mapping. During control program validation, simulated I/O data is exchanged between the process simulation and the I/O module instances in the controller in accordance with the I/O point mapping.

Abstract: A method for determining a representation (y) of a signal (s) comprise selecting a predetermined number (m) of row vectors (v1, . . . , vm) from a predetermined measurement matrix (M). The predetermined measurement matrix (M) is predetermined dependent on a product of a predetermined Hadamard matrix or generalized Hadamard matrix (H) and a predetermined representation matrix(B). The predetermined representation matrix (B) represents a predetermined basis for the signal(s). The method further comprises determining a respective inner product of the signal (s) and each of the predetermined number (m) of selected row vectors (v1, . . . , vm) resulting in a predetermined number (m) of measurements (y1, . . . , ym) forming the representation (y) of the signal (s).

Abstract: Methods and apparatus, including computer program products, are provided for in-memory simulations. The method may include forming a virtual cube including at least one change value representative of a change to a simulation; forming another cube including online data; and combining the virtual cube and the other cube to form a union cube representative of a result of the simulation, the virtual cube, other cube, and the union cube comprised in an in-memory storage and shared for at least a session associated with the simulation. Related systems, methods, and articles of manufacture are also disclosed.

Abstract: The method and system for modeling RF emissions occurring in a radio frequency band utilizes commercial off-the-shelf (COTS) hardware to perform the steps of converting legacy PDW databases to RF signal I and Q format and storing the I and Q data in a digital I and Q data signal library. Alternatively, real-time RF signals are recorded in I and Q format and routed to the library. Moreover, a synthesizer is provided to form I and Q data and forward the data to the library. I and Q library data is time-tagged. An RF editor includes editing tools to modify the I and Q library accordingly, as required. A channelizer extracts channel information from the I and Q data and sends that channelized data to at least one to vector signal generator. A combiner is used to combine outputs of multiple vector signal generators connected to the channelizer.

Abstract: A method is provided for determining optimum positions in a region for a plurality of sensors that are capable of detecting occurrence of a hazard in the region. The hazard may be a chemical, biological, and/or radiological hazard in solid, liquid or gas form. A “simulation cache” is provided that stores data representing interaction of the hazard with sensors at each of the plurality of candidate locations in the region for each of the plurality of sensor types. Data is then retrieved from the simulation cache as needed for evaluation a particular candidate sensor solution comprising one or more sensors of one or more sensor types at corresponding ones of the candidate locations. An optimization algorithm may be used to select a candidate sensor solution. The data that is retrieved from the simulation cache for a selected candidate sensor solution is evaluated with respect to certain performance criteria.

Abstract: When a wait statement is encountered in an HDL simulation, the simulation kernel executes functions corresponding to other processes while waiting for the wait to mature. However, the preservation of variables and states of each process and procedure in the call chain can be complex and inefficient. An embodiment of the present invention provides a method to suspend procedures in simulation of an HDL circuit design such that processes that call procedures containing wait statements are executed on a secondary runtime stack and can be suspended by saving the state of simulation and switching simulation execution to the primary runtime stack.

Abstract: Systems and methods for a system for automatically building a simulated network environment creating device profiles with device level metadata, segment profiles that utilize one or more of the created device profiles and that includes segment metadata, and a network environment profile that is created from segment profiles and that includes network environment metadata and a hierarchy based on dependencies with other segments within the network environment profile.

Abstract: A method for design simulation includes partitioning a verification task of a design into a first plurality of atomic Processing Elements (PEs) having execution dependencies, each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device, which includes a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.

Abstract: The graphics load of a virtual desktop is estimated to determine the capacity of a virtual desktop system. In one embodiment, the graphics load of a physical desktop is measured by a remoting agent installed on the physical desktop. The graphics load can be used as an estimate of the load that would be created by a deployed virtual desktop. The remoting agent on the physical desktop mimics host operations that are necessary to direct graphics data to a remote site. The remoting agent also measures the graphics load incurred by the host operations to determine a capacity of a virtual desktop system prior to deployment of the virtual desktop system.

Abstract: A simulation method for a P-I-N junction photodiode uses a model that may include a diode model configured to characterize electrical behavior of the P-I-N junction photodiode, and an input for applying a fictitious electrical signal representing optical power received by the P-I-N junction photodiode. A current source model may be coupled to the diode model and may have a transient response to a variation of the fictitious electrical signal, based upon a sum of a first first-order transient response with a time constant based upon to a transit time of carriers in a depletion region of the P-I-N junction, and a second first-order transient response with a time constant based upon a diffusion time of carriers outside of the depletion region. The first and second responses may be respectively weighted by a length of the depletion region and a length of the P-I-N junction outside the depletion region.

Abstract: In one embodiment, a Computer Aided Design (CAD) environment is configured to maintain a model of a system. The CAD environment includes a plurality of predefined transducers, and a graphical user interface configured to permit a user to select one or more of the predefined transducers and connect the selected transducers to portions of the model. The CAD environment further includes a simulation engine to run a simulation of the model. A graphical programming environment is configured to execute a graphical program embodied in a block diagram. The graphical program receives one or more simulated transducer signals from the CAD environment and generates and sends one or more control signals to the CAD environment, to control the simulation.

Abstract: Certain embodiments of the invention may include systems and methods for providing electrical fault restoration. According to an example embodiment of the invention, a method can include sectioning a de-energized region into two or more de-energized areas; simulating opening or closing of one or more circuit switches associated with the two or more de-energized areas; compiling a listing of simulated energized areas and simulated de-energized areas, based on the simulated opening or closing of the one or more circuit switches; evaluating the listing of simulated energized areas and simulated de-energized areas, based at least in part on one or more configurable strategy modules; and generating a restoration plan based at least in part on the evaluation.

Abstract: A method of simulating a design described in HDL is provided. In this method, modules of the design can be partitioned into first modules for simulation by a serial simulation engine and second modules for simulation by a concurrent simulation engine. The first and second modules can be prioritized for simulation based on classes of events consistent with an execution model of the HDL. Simulations of the serial and concurrent simulation engines can be synchronized for each class of events. Synchronizing can include transferring updated interface variable values, which are shared by the second modules and at least a subset of the first modules, between the serial simulation engine and the concurrent simulation engine. This transferring can include translating representations of the updated interface variable values.

Abstract: Embodiments include methods, apparatus, and systems for controlling multiple simulations. One embodiment is a method that includes executing plural architectural simulators being interconnected to form a platform for hardware simulation; placing at least one of the plural architectural simulators into a pause state; and automatically minimizing windows associated with the at least one of the plural architectural simulators.

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

Abstract: User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

Abstract: A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.

Abstract: A process develops controls for microgrid systems. The process models physical systems of increasing complexity. Candidate control algorithms are implemented as state machines that can affect state variables which represent control signals for elements of the physical system. A simulation of the physical system is operated according to the control algorithms.

Abstract: Balancing a simulation platform including a nonlinear aeronautical system, the balancing including servoing of an output value of the system to a recorded value, including a first filter producing an inversion of a simplified model of the system for generating a control for the system based on a model correction information item estimating a modeling error of the simplified model and an information item on difference between the output value and the recorded value, and a modeling corrector looping including a second filter using the simplified model to calculate, based on the control and the output value, the model correction item to be supplied to the first filter.

Abstract: A method and a system for determining the observability of faults in an electronic circuit include a processor that simulates, in a simulation phase, a behavior of the electronic circuit using a simulation model, and that determined, in an analysis phase, based on the simulation, and for each of a plurality of elements of the electronic circuit, time periods in which an occurrent fault could cause a deviation in analysis output signals, where the occurrent fault is determined not to cause any deviation in output signals in other time periods.

Abstract: A method for processing a stream of tuples may comprise receiving a stream of tuples to be processed by a plurality of processing elements operating on one or more computer processors. In addition, the method may include generating a model of performance for processing the stream of tuples at runtime, wherein one or more tuples from the stream of tuples potentially cause adverse performance. Further, the method may comprise predicting a parameter for a tuple from the stream of tuples, the parameter indicating a potential for adverse performance, the predicting including using the model. The method may also include modifying processing of the tuple if the parameter falls outside a threshold.

Abstract: Described herein is a method and system that provides access to numerous connected devices in a device bank and allows remote interaction and control of aspects of the connected devices using a remote management system. In an embodiment, the method comprises the configuring of one or more connected devices in the device bank to mimic an end user's connected device configuration and environment in order to resolve an issue with the end user's connected device. In other embodiments, the connected devices in the device bank can be used by end users such as developers to test and diagnose new applications and by remote support technicians to train themselves on connected devices.

Abstract: A method for processing a stream of tuples may comprise receiving a stream of tuples to be processed by a plurality of processing elements operating on one or more computer processors. In addition, the method may include generating a model of performance for processing the stream of tuples at runtime, wherein one or more tuples from the stream of tuples potentially cause adverse performance. Further, the method may comprise predicting a parameter for a tuple from the stream of tuples, the parameter indicating a potential for adverse performance, the predicting including using the model. The method may also include modifying processing of the tuple if the parameter falls outside a threshold.

Abstract: Novel and non-trivial systems and methods for incorporating virtual network computing (“VNC”) into a cockpit display system (“CDS”) and controlling an aircraft system with a VNC-incorporated CDS are disclosed. A system for incorporating VNC into the CDS is comprised of a VNC server of an aircraft system, at least one first user application (“UA”), a second UA, a pilot input device, and a CDS comprised of, in part, a processing module (“PM”) configured with a corresponding method that employs both an aviation-industry standard protocol (e.g., ARINC 661) and a VNC protocol. A system for controlling an aircraft system with a VNC-incorporated CDS is comprised with a VNC server of an aircraft system, a UA, a pilot input device, a display surface format, and a CDS comprised of, in part, a PM configured with a corresponding method that employs both an aviation-industry standard protocol and a VNC protocol.

Abstract: A tool for enabling a user, such as a programmer and a designer, to identify patterns in a program or model and to determine duplicated portions of the program or model that have the same or similar pattern is disclosed. The pattern may include the connectivity of the elements in the group as well as the attributes and parameters of the elements in the group. The tool may also enable the user to replace the duplicated portions of the program or model with a sub-program or sub-model that can be shared for the duplicated portions. Code for the sub-model may be used for the simulation or generated code for the duplicated portions of the program or model in the simulation or code generation of the program or model.

Abstract: Systems and methods are provided to optimize critical paths by modulating systemic process variations, such as regional timing variations in IC designs. A method includes determining a physical location of an element in the semiconductor chip design within the critical path. The method further includes modulating a systemic process variation of the semiconductor chip design to speed up the critical path based on a polysilicon conductor perimeter density associated with the element.

Abstract: A mechanism is provided for determining connectivity while minimizing wiring in an electronic system. The mechanism identifies a configuration of the electronic system, a location of each module in a plurality of modules within the electronic system and at least one constraint with regard to wiring the electronic system, the location of each module being identified using three-dimensional coordinates. The mechanism routes a separate cable from each module in the plurality of modules to each of the other modules in the plurality of modules without violating any constraints, thereby forming a plurality of cables. The mechanism then generates a cabling list indicating how each cable in the plurality of cables is to be routed in the electronic system in order to not violate any constraints and provide connectivity while minimizing wiring.

Abstract: The performance of a repeater path may be predicted by identifying the parameters of a transmitting earth, a receiving earth station, and the component performance parameters of at least one of the gain, loss and noise figure of at least one of repeater components in the repeater path. The component performance parameters, the transmitting and receiving earth station parameters, and the predicted repeater performance may be communicated and/or displayed via a graphical user interface.

Abstract: A system and methods for battery health diagnostics are disclosed. At least one battery property of a battery is measured in real-time to provide measured data, and at least one measurement time at which the measured data is measured is tracked. A battery history model is provided by adaptively modeling the measured data and the measurement time, and a future state of the battery is estimated based on the battery history model.

Abstract: An embodiment of the present invention provides a method, comprising optimizing the location and configuration of relay stations in a wireless network that includes at least one base station and at least one relay station by taking into account at least one or more of the following: the distinct antenna heights of said at least one base station and said at least one relay station; the data dependency between said at least one relay station and said at least one base station; the service outage of said wireless network; and the network throughput of said wireless network.

Abstract: Provided is a circuit simulation model that can suitably represent capacitor characteristics, thereby realizing accurate circuit design and circuit analysis. A SPICE model is constituted of a capacitor unit in which a capacitor is replaced with a linear voltage dependent current source, a low-pass filter unit that has a function of extracting a DC bias voltage, a calculation circuit unit that is configured by combining an adder, a multiplier, and the like to perform a calculation of a circuit equation derived from an equivalent circuit for a capacitor such as an idealized C circuit model, an RC circuit model, or the like, and a linear voltage dependent voltage source that applies a total voltage applied across the capacitor to the calculation circuit.

Abstract: In an embodiment, the design of a digital circuit may be analyzed to identify which uninitialized memory elements, such as flops, have initial don't care values. The analysis may include determining that that each possible initial value (e.g. zero and one) of the flops does not impact the outputs of circuitry to which the uninitialized flops are connected. For example, a model may be generated that includes two instances of the uninitialized flops and corresponding logic circuitry. The inputs of the two instances may be connected together, and the uninitialized flops may be initialized to zero in one instance and one in the other instance. If the outputs of the two instances are equal for any input stimulus, the initial value of the uninitialized flops may be don't cares. The flops may be safely initialized to a known value for simulation.

Abstract: A testing method and an apparatus applied to an IP phone system for testing an electronic device is provided. The electronic device has a true table and signal ports. The electronic device is connected to a power generating jig and an IP phone simulator via a cable. A power generated by the power generating jig is provided. A first value power command issued by the IP phone simulator is provided. Whether the electronic device is able to correctly control the signal ports in response to the first value power command and the true table is determined. A second value power command issued by the IP phone simulator is provided. Whether the electronic device is able to correctly control the signal ports in response to the second value power command and the true table is determined. If so, it is concluded that the electronic device passes the test.

Abstract: For voltage values (observed noise sequence) in an electronic power line (communication medium) which are obtained at a predetermined interval, initial values of noise characteristics based on a statistic of the observed noise sequence itself are decided by a moment method (S301 to S307), the noise characteristics (state transition probabilities and state noise power) for maximization of the likelihood of the observed noise sequence are obtained from the initial values by MAP (Maximum A Posteriori) estimation using a Baum-Welch algorithm (S309 to S312), a state sequence is estimated from the obtained noise characteristics, and an impulsive noise at each time point is detected.