Simulating Electronic Device Or Electrical System Patents (Class 703/13)
  • Patent number: 8831927
    Abstract: An energy-saving optimizing program works closely with conventional process simulation programs by applying energy saving paradigms embodied in script files that may review data inherent in the simulation program to identify possible energy-saving opportunities. When the script files identify a possible energy savings, they may interact with the simulation program to evaluate the savings potential and present the same to a user. In this way opportunistic energy savings may be provided even for processes that resist close form global optimization.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: September 9, 2014
    Assignee: Rockwell Automation Technologies, Inc.
    Inventor: David Allan March
  • Patent number: 8832645
    Abstract: A palette of representations that can be generated by an application for database, spreadsheet, word processing, and the like, is provided in response to a request for a new object within the application. If the application already has one or more objects open at the time of the request, the representations are also determined based on the context of the data such as from any currently open object(s). The new object is then generated based on the selected representation from the palette, the context of the data, and a structure of data consumed by the application. The layout parameters for the new object are automatically set based on the current context, the structure of the data, and the selected representation.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: September 9, 2014
    Assignee: Microsoft Corporation
    Inventors: Zachary P. Woodall, Dan Hough, Kumar Srinivasamurthy, Nishant Kumar, Pavel R. Karimov, Stephen I. Lesser, Clinton Covington, Michael J. McCormack, Christopher W. Bryant
  • Patent number: 8830845
    Abstract: Packet switch test methods include receiving a first packet from a packet switch, receiving a second packet from processing circuitry configured to model expected behavior of the packet switch, comparing the first packet to the second packet, and, based on the comparing, determining whether the packet switch is operating according to the expected behavior. Packet switch modeling methods include identifying functionality of a packet switch to be modeled, creating, in a packet switch model, a plurality of nodes representing physical and/or logical elements of the packet switch, the nodes being configured to process packet data structures and to respectively model different portions of the functionality of the packet switch relative to one another, and, in the packet switch model, connecting the nodes with pathways by which the packet data structures may be forwarded between the nodes.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: September 9, 2014
    Assignee: Ciena Corporation
    Inventors: Bruce T. Jorgens, Brian R. Town
  • Patent number: 8826219
    Abstract: Disclosed herein are methods and devices used for the physical design validation of integrated circuits. One method used for the physical design validation of integrated circuits includes comparing the original circuit netlist of an integrated circuit and the layout data of the integrated circuit and assigning labels to the input and output terminals of the components in the integrated circuit based on the results of the comparison.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: September 2, 2014
    Assignee: Synopsys, Inc.
    Inventor: Chiu-Yu Ku
  • Patent number: 8825464
    Abstract: One particular implementation takes the form of an apparatus or method for parallelizing a sequential power simulation of an integrated circuit device. The implementation may temporally divide the simulation so that separate time segments of the simulation can be run at the same time, thereby reducing he required time necessary to perform the power simulation. More particularly, a logic simulation may be performed on the integrated circuit and snapshots of the logic devices of the integrated circuit may be taken at a specified period. The separate time segments of the simulation may then be simulated in a parallel manner to simulate power consumption of the integrated circuit. Performing the power simulation on the separate time segments may reduce the required time of a typical power consumption simulation of an integrated circuit.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: September 2, 2014
    Assignee: Oracle America, Inc.
    Inventor: Vijay S. Srinivasan
  • Patent number: 8825462
    Abstract: A method and system for simulating a plurality of devices are disclosed. A simulator configured to simulate a plurality of devices may output simulated device data for the plurality of devices, where the output of the simulated device data may be performed based upon execution of commands by the simulator. The commands may be received from a device abstraction layer in response to a request from the simulator for any commands associated with the plurality of devices. Additionally, the simulated device data may be communicated to a component coupled to the simulator, where a result of the processing of the simulated device data by the component may be used to analyze the performance of the component. Further, other commands may be executed by simulator for changing the frequency at which simulated device data is output, for performing another operation defined during configuration of the simulator, etc.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: September 2, 2014
    Assignee: Accenture Global Services Limited
    Inventors: Michael J. Biltz, Jonathan Hsu, Sean Stauth, Graeme D. MacDonald
  • Patent number: 8825463
    Abstract: A logic simulation method includes causing a physical specification detector to detect physical specifications of an analog circuit (a PLL circuit and a DLL circuit) as a verification object described in a logic library; causing a monitor to monitor whether a signal or setting during a logic simulation satisfies the physical specifications; and causing a warning section to issue a warning when the signal or the setting fails to satisfy the physical specifications.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: September 2, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kenichi Nomura, Hideaki Anbutsu, Cheng Giam Tan
  • Publication number: 20140244231
    Abstract: A method for performing configuration of a control unit test system with hardware components connected thereto, wherein control units can be tested with the test system in an environment simulated by the test system by means of a model, and wherein the test system comprises at least one computer, in particular a computer executing the model, as well as hardware components, connected to one another by means of at least one network, in which at least a portion of the hardware components comprises a dedicated server (MIS) that, by means of communication, provides access to the configuration data associated with the hardware component, in particular stored in the hardware component, and the model and/or the hardware component is adapted, in particular configured, as a function of the configuration data that are made accessible.
    Type: Application
    Filed: February 24, 2014
    Publication date: August 28, 2014
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: Juergen PAULE, Juergen KLAHOLD
  • Publication number: 20140244230
    Abstract: In accordance with aspects of the disclosure, systems and methods are provided for generating one or more potential configurations corresponding to one or more parameters used for computing infrastructure planning by determining a sizing grammar for each of the one or more potential configurations corresponding to the one or more parameters, interpreting the sizing grammar based on one or more grammar rules to output configuration information for each of the one or more potential configurations, and translating the configuration information for each of the one or more potential configurations based on one or more motif descriptions to output resource information for each of the one or more potential configurations.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 28, 2014
    Applicant: BMC Software, Inc.
    Inventor: Sudheer Apte
  • Patent number: 8818783
    Abstract: A method for representing state transitions within a state machine includes representing a set of allowed transitions between states as a transition pair wherein a first value of the transition pair indicates a set of nodes from which to transition and a second value of the pair indicates a set of nodes to which to transition. The nodes represent states within a state machine. The method further includes defining a role of an entity within the state machine by assigning a number of transition pairs to the entity, the value pairs defining how the entity can transition through the state machine.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventor: Marcos Nogueira Novaes
  • Patent number: 8819250
    Abstract: A method for the computer-aided determination of a control variable using context information from one or more units to be controlled is described. This method involves a controller using simulation to ascertain a piece of simulated context information which is used as a control variable, wherein the simulated context information comprises a first variable which represents a presumed state of the one or more units at a given time. The controller compares a received piece of context information, which comprises a second variable which represents the actual state of the unit to be controlled at a time which is before the given time, with the simulated context information and checks whether the simulated context information matches the context information within prescribed limits. In addition, the controller requests a piece of updated context information from one or more units to be controlled if the simulated context information matches the context information at the given time outside the present limits.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: August 26, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventors: Sahin Albayrak, Frank-Uwe Andersen, Changpeng Fan, Ahmet Cihat Toker, Giscard Wepiwé
  • Patent number: 8818767
    Abstract: A method for assisting the construction and validation of an avionics platform uses, on the one hand, a functional description of the platform using avionics functions, software modules suitable for executing these functions, and functional link occurrences between these modules and, on the other hand, a material description of this platform using calculation or communication items of equipment and physical links between these equipment. The method according to the invention enables to generate paths between the various items of equipment by using direct physical links and/or physical links belonging to one or more network(s), and subsequently to associate at least one such path to be each functional link occurrence. It also enables to associate to each software module an item of equipment adapted to host it.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: August 26, 2014
    Assignee: Airbus Operations S.A.S.
    Inventor: Frédéric Minot
  • Patent number: 8816444
    Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Chih-Sheng Chang, Yi-Tang Lin, Ming-Feng Shieh, Ting-Chu Ko, Chung-Hsien Chen
  • Publication number: 20140236560
    Abstract: A method for performing an inventory of the hardware components connected to a control unit test system, wherein control units can be tested with the test system in an environment simulated by the test system by means of a model, and wherein the test system comprises at least one computer) and hardware components that are connected to one another by means of at least one network. For at least a portion of the hardware components, in particular of all simulation-specific hardware components, at least one item of component information that uniquely and digitally identifies the hardware component is read therefrom, and all identifying component information that has been read out is stored.
    Type: Application
    Filed: February 21, 2014
    Publication date: August 21, 2014
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: Thorsten BREHM, Susanne KOEHL, Juergen PAULE, Juergen KLAHOLD, Claus DIENER
  • Publication number: 20140236546
    Abstract: An apparatus has an improved antenna pattern for a cross dipole antenna. Such antennas desirably have an omnidirectional antenna pattern. Conventional cross dipole antennas exhibit nulls in their antenna patterns, which can cause antennas to deviate from a standard or specification. Applicant recognized and confirmed that the connection of a coaxial cable to the antenna arms is a cause of the nulls in the antenna pattern, and has devised techniques disclosed herein to compensate or cancel the effects of the connection. In one embodiment, the arms of the cross dipole antenna that are coupled to a center conductor of the coaxial cable remain of conventional length, but the arms of the cross dipole antenna that are coupled to a shield of the coaxial cable are lengthened by a fraction of the radius of the outer diameter of the coaxial cable.
    Type: Application
    Filed: December 18, 2013
    Publication date: August 21, 2014
    Applicant: VENTI GROUP, LLC
    Inventor: William Ernest Payne
  • Patent number: 8812284
    Abstract: Optionally-mixed highly representative real time simulation of at least part of an avionics system (2). The simulation provides at least a step of translating communications interfaces into the form of models encoded in high level language on the basis of formal files in mark-up language; and dynamically managing descriptions that provide for grouping together, updating, and sharing a database that, for each piece of equipment, incorporates signals that transit via its input and/or output interfaces.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: August 19, 2014
    Assignee: Airbus Helicopters
    Inventors: Nicolas Damiani, Roland Touati, Nicolas Brisset
  • Patent number: 8812283
    Abstract: A time-driven block provided in a block diagram model may be executed in an event domain without user modification. The time-driven block is connected to one or more event-driven blocks using event domain signals. The time-driven block automatically adapts to the execution rules of the event domain modeling and simulation environment. The blocks that are configured to execute in more than one modeling and simulation environments are called polymorphic blocks. The polymorphic blocks are indentified during the compilation stage of the block diagram model taking into consideration the port and line styles of the blocks. The execution rules of the polymorphic blocks are also determined during the compilation stage of the block diagram model.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: August 19, 2014
    Assignee: The MathWorks, Inc.
    Inventors: Wei Li, John Edward Ciolfi, Michael I. Clune
  • Patent number: 8812287
    Abstract: A method and device for preserving the wired-OR nature of the clock signal connection between two devices without a direct analog connection between the lines and in an infinitely scalable fashion. The method includes detecting a logic state at a first connector and a second connector and driving an appropriate connector of the device to an active state in response to determining that a connector is driving an active state. The device includes first and second connectors for communicating logic states and driving active states in response to detected logic states.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventor: Daniel J Barus
  • Publication number: 20140229152
    Abstract: The present invention relates to a diagnostic device (400) for measuring component performance on an automated radiopharmaceutical synthesis device (50).
    Type: Application
    Filed: September 28, 2012
    Publication date: August 14, 2014
    Applicant: GE HEALTHCARE LIMITED
    Inventor: Robert F. Chisholm
  • Patent number: 8805664
    Abstract: In an embodiment, a method of establishing directed relationships between states in a simulation is disclosed. The directed relationships may allow the simulation to proceed from an initial state according to two or more divergent behaviors. The simulation may merge if two or more behaviors result in states that are equivalent. The method may further allow a state of the simulation which has not been stored to be interpolated from one or more states that have been stored. In one embodiment, a system may receive a request to revert to a previous state, and the system may identify a saved state that is closest to the requested state. The system may simulate from the identified state to arrive at the requested state. In one embodiment, the simulation may be a hybrid simulation which is advanced in both discrete and continuous increments.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: August 12, 2014
    Assignee: The MathWorks, Inc.
    Inventors: Zhi Han, Murali Yeddanapudi, Pieter J. Mosterman, Xiaocang Lin, Rajesh Pavan Sunkari
  • Patent number: 8805709
    Abstract: Systems and methods for providing dividends to customers are disclosed. The system includes a database for storing data and a business logic processor for determining a dividend to provide to a customer. The stored data includes eligibility criteria for membership in one of a plurality of group dividend plans, data about customers assigned to the plans, and premium payments associated with the customers. The business logic processor receives eligibility data related to a customer's eligibility for assignment to a group dividend plan. The business logic processor uses the received data to identify a dividend group plan that a customer is eligible to join and assigns the customer to the identified plan. Finally, the business logic processor calculates a dividend to provide to the customer based on the assigned plan.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: August 12, 2014
    Assignee: Hartford Fire Insurance Company
    Inventors: Anthony J. Grosso, Steven P. Rippel, Jacqueline LeSage Krause
  • Patent number: 8806396
    Abstract: Disclosed is a method, system, and computer program product for performing predictions for an electronic design. Embodiments of the invention allow the ability to efficiently update the model predictions at a later time once previously incomplete blocks are completed. Predictions can be efficiently updated after block designs are updated (e.g. after correcting problems detected from model predictions).
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: August 12, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ming Liu, JenPin Weng, Taber Smith
  • Patent number: 8806412
    Abstract: Place-and-route (P&R) includes maintaining a set of local arrival time information and local required time information associated with a circuit layout; determining a candidate fix on a critical path in the circuit layout; statistically determining, using one or more computer processors, a set of one or more adjusted local slacks associated with a region affected by the candidate fix; and in the event that the set of one or more adjusted local slacks indicates that the candidate fix results in a timing improvement, accepting the candidate fix.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 12, 2014
    Assignee: Atoptech, Inc.
    Inventors: Yu-Cheng Wang, Wei-Shen Wang
  • Publication number: 20140222409
    Abstract: A system for mapping a magnetic-field in a volume-of-interest comprising a magnetic-field transmitter, generating a magnetic-field in the volume-of-interest, a freestanding magnetic-field detector operative to freely move within the volume-of-interest, a pose-information-acquisition-module and a processor. The detector acquires measurements of flux of the magnetic-field at a plurality of poses. The pose-information-acquisition-module measures information related to the pose of the detector. The processor determines pose-related-information respective of at least a portion of the measurements according to the information related to the pose of the detector. The processor estimates the entire set of parameters of a magnetic-field model template according to the magnetic-field flux measurement and the respective poses-related-information thereof. The processor incorporates the entire set of parameters into the magnetic-field model template, thereby determining the magnetic-field model.
    Type: Application
    Filed: April 10, 2014
    Publication date: August 7, 2014
    Applicant: ELBIT SYSTEMS LTD.
    Inventors: Ilan EFRAT, Evgeni GUROVICH, Guy MENCEL
  • Publication number: 20140222408
    Abstract: A simulation system for a control system which controls a process running in a technical system is provided. The control system has at least one first process environment embodied as a container and which is also designed to simulate the automatic process to be run in the system and comprises corresponding interfaces to the control system. The simulation system includes a second process environment designed as a container for simulating the hardware of the periphery of the control system and a third process environment designed as a container for the simulation of the process to be run in the technical system. In another embodiment, both process environments can be also be combined to form one process environment. In both embodiments, the interfaces of the second process environment are practically identical to the interfaces of the third process environment and the interfaces of the first process environment.
    Type: Application
    Filed: June 5, 2012
    Publication date: August 7, 2014
    Applicant: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Andreas Rathgeb, Rainer Speh, Michael Unkelbach
  • Publication number: 20140222525
    Abstract: A Radio Frequency IDentification (RFID) simulator system is provided. The RFID simulator system includes a processor effective to receive first data representing a pre-existing system for tracking of objects; simulate an RFID system having at least one RFID reader, at least one RFID antenna, and a plurality of objects connected to RFID tags; simulate a path of the objects; simulate an RFID system environment to produce second data representing simulated RFID tracking of the objects; and compare first data and second data to generate third data; and at least one memory effective to store at least one of the first data, the second data and the third data.
    Type: Application
    Filed: February 6, 2013
    Publication date: August 7, 2014
    Applicant: Portable Technology Solutions, LLC
    Inventors: Howard Harold Heckman, III, Daniel Joseph Peluso, Bradley Joseph Horn
  • Patent number: 8799850
    Abstract: Some embodiments provide a system that performs a simulation within an electronic design automation (EDA) application. During operation, the system obtains a design from a user of the EDA application. Next, the system performs the simulation using the design to create a set of current simulation results associated with the design. The system then automatically saves a current design state of the design which is associated with the current simulation results. Finally, the system enables subsequent access to the current design state and one or more previous design states of the design by the user through a graphical user interface (GUI) associated with the EDA application.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: August 5, 2014
    Assignee: Synopsys, Inc.
    Inventors: Salem L. Ganzhorn, Kristin M. Beggs, Govindaswamy Chithamudali
  • Patent number: 8798964
    Abstract: In one embodiment of the invention, a method of designing the racking configuration for boxes in racks and for determining which connections go between different racks, including: solving a rack select optimization sub-problem to determine racks to use; and solving a rack assign optimization sub-problem to determine which particular rack will hold a particular box. In another embodiment, an apparatus for designing the racking configuration for boxes in racks and for determining which connections go between different racks, including: a machine-readable representation for a racking configuration problem; and a solver that can read that machine-readable representation and that is configured to: solve a rack select optimization sub-problem to determine at least one rack to use; and solve a rack assign optimization sub-problem to determine which particular rack will hold at least one box.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: August 5, 2014
    Assignee: Hewlett-Packard Development Company, L. P.
    Inventors: Richard Edwin Rosenthal, Troy Alexander Shahoumian, Julie Ann Ward, John Wilkes
  • Publication number: 20140214394
    Abstract: A simulation device capable of executing a proper simulation without changing a program, while the definition of virtual peripheral equipment and/or a PLC is not necessary. A signal status setting file, which is separated from a robot program, can be executed in parallel with the program, and includes a command for setting or changing a signal status described corresponding to a line in execution of the program, wherein the status is referenced by executing the line of the program. For example, a command of the file, described corresponding to a fifth line of the robot program, commands inputting a signal which indicates that the opening motion of a door is completed. Therefore, when the simulation is executed, in synchronization with the line in execution of the program, the setting or changing of the signal status, described corresponding to the line in execution, is performed.
    Type: Application
    Filed: January 28, 2014
    Publication date: July 31, 2014
    Applicant: FANUC CORPORATION
    Inventor: Kozo INOUE
  • Publication number: 20140214393
    Abstract: Disclosed herein are an apparatus and method of performing distributed simulation. In the method of performing distributed simulation, a simulation time provision apparatus sets global simulation times synchronized with real times based on the real times. The simulation time provision apparatus distributes the set global simulation times over distributed simulators. Each of the distributed simulators adjusts the interval between local simulation times, during which the continuous or discrete elements of an allocated one of subsystem models that model subsystems forming a hybrid system will be analyzed, based on the global simulation times. The distributed simulator performs simulation to analyze the continuous or discrete elements of the subsystem model during a period corresponding to the adjusted interval between the local simulation times.
    Type: Application
    Filed: December 10, 2013
    Publication date: July 31, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jin-Myoung KIM, Hae-Young LEE, In-Geol CHUN, Won-Tae KIM
  • Publication number: 20140214392
    Abstract: A cloud computing system according to various embodiments can include a computing cloud comprising at least one processing unit and at least one database and a plurality of users in communication with the computing cloud. The computing cloud is configured to receive a request to select a product and define a model of an infrastructure system associated with the selected product. The computing cloud generates a first model of the infrastructure system including a first control system, and generates a second model of the infrastructure system including a second control system. The cloud computing simulates a first control operations of the first model of the infrastructure system in operation with the first control system and simulates a second control operations of the second model of the infrastructure system in operation with the second control system. The cloud computing compares results of the first and second control operations.
    Type: Application
    Filed: January 28, 2013
    Publication date: July 31, 2014
    Applicant: GE INTELLIGENT PLATFORMS, INC.
    Inventor: Daniel Halvard MILLER
  • Patent number: 8793116
    Abstract: A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of the part pieces having known design data, the part pieces including at least one first layout part piece comprising a given number of single transistor cells, and adjusting the specified design power level of the first vertical MOS power transistor by using the known design data of the part pieces and based on the layout combination of the part pieces.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: July 29, 2014
    Assignees: X-Fab Semiconductor Foundries AG, Alpha microelectronics GmbH
    Inventors: Ralf Lerner, Wolfgang Miesch
  • Patent number: 8793115
    Abstract: Providing a unified view of multiple computer system simulations. A simulation process has a simulation thread that executes a plurality of computer system simulations. The simulation process also has a debug support thread that provides a unified view of the simulations. To provide the unified view, the debug support thread has an external interface, an internal interface to each of the simulations, and an interface converter that converts between the external interface and the internal interfaces. Thus, the external interface provides a unified view of the simulations. The external interface allows a single debugging platform to control and observe the simulations.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: July 29, 2014
    Assignee: Synopsys, Inc.
    Inventors: Niels Vanspauwen, Tom Michiels, Karl Van Rompaey
  • Patent number: 8793628
    Abstract: The present patent document relates to a method and apparatus for maintaining coherency in a memory subsystem of an electronic system modeled in dual abstractions. The portions of the memory subsystem shared between the first abstraction and the second abstraction are shadowed in both abstractions, allowing either abstraction to coherently access memory written by the other. The memory subsystem can also reside solely in a first abstraction, where the second abstraction will synchronize to the first abstraction to access the memory subsystem. Flags associated with memory pages of the memory subsystem are set to indicate which abstraction has most recently updated the memory page. Prior to accessing a memory page, the system will check the flags, copying the contents of the memory in the other abstraction as needed to maintain coherency. The abstractions can operate either synchronously or asynchronously.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: July 29, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventor: Ashutosh Varma
  • Publication number: 20140204577
    Abstract: The present disclosure provides an LED based light unit that produces an output lighting pattern that meets desired lighting characteristics using a reduced number of LED elements. The present disclosure provides a number of point sources that are directed into a desired direction such that, when combined with other point sources, a synthesized light output is provided that minimizes the LED headcount.
    Type: Application
    Filed: January 21, 2014
    Publication date: July 24, 2014
    Applicant: EVOLUCIA LIGHTING, INC.
    Inventors: RICK KAUFFMAN, DONALD SIPES, DONALD VANDERSLUIS, ROBERT FUGERER
  • Patent number: 8788255
    Abstract: A delay analysis device composed of a storage device and a data processing device analyzes a chip fabricating a semiconductor integrated circuit. Delay calculation is performed via an RC simulation with reference to a layout-implemented macro net list, macro layout data, and a cell timing library, thus producing macro delay information. An initial stage of a macro is annotated by the global clock path delay information including the edge information so as to produce a global clock delay-annotated macro net list, which is then converted into a macro delay-annotated net list. Based on the macro delay-annotated net list and timing constraint, the delay analysis device calculates delay times of signal paths and clock paths as well as clock skews with a high precision. It checks whether or not the relationship between the delay times of signal paths and clock paths meets the timing constraint, thus producing delay analysis information.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: July 22, 2014
    Assignee: NEC Corporation
    Inventor: Koji Kanno
  • Patent number: 8788254
    Abstract: A system with a dynamic temporal dimension for monitoring and control of contact centers, comprising: a scalable simulation service configured with a virtual environment that replicates and is maintained in synchrony with a production contact center environment; an analysis manager; a persistent query service; and a visualizer. The persistent query service receives data from contact center systems and updates virtual tables based on the updates; the analysis manager, sends real-time updates to the visualizer, and the visualizer updates a visualization provided to a user by displaying the real-time updates as a set of past states; and the scalable simulation service performs a time-warped simulation to compute at least a future state of one of the virtual environments and sends a second plurality of updates to the visualizer, and the visualizer updates the visualization provided to the user by displaying the second plurality of real-time updates as a projected future state.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: July 22, 2014
    Assignee: Aria Solutions, Inc.
    Inventor: Paul Peloski
  • Patent number: 8788253
    Abstract: Embodiments of the invention relate to methods and systems for providing haptic feedback to a user interacting with a simulated (or “virtual”) pet, so as to enhance the realism of the user's relationship with the virtual pet. In one embodiment, a method of providing haptic feedback to a user interacting with a virtual pet comprises: receiving a signal relating to a biological status of the virtual pet, and outputting a haptic effect based on the received signal on a user.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: July 22, 2014
    Assignee: Immersion Corporation
    Inventor: Louis B. Rosenberg
  • Patent number: 8781809
    Abstract: Systems and methods are provided for collecting and aggregating a plurality of power flow measurements from a plurality of devices in a power management system. The error bounds of the aggregated power flow measurement are then determined using at least one error model. Systems and methods are also provided for inferring AC power flows from DC power flows. A device having at least one DC power flow sensor is augmented with at least one AC power flow sensor AC and DC power flows through the device are measured using the sensors over a range of operating points. An inference model of AC power flow in the device as a function of DC power flow is then built, wherein the error of the model is bounded. DC power flow through the device and in similar devices can then be then measured and used to infer AC power flow for the device.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: July 15, 2014
    Assignee: GridPoint, Inc.
    Inventor: Seth W. Bridges
  • Patent number: 8781808
    Abstract: The simulation consists of a front-end simulation and a back-end simulation. The front-end simulation can use an equivalent model at different abstraction level, or a simulation model for the back-end simulation. The back-end simulation uses the simulation result of front-end simulation so that it can run one or more simulation runs sequentially or in parallel. Alternatively, models at lower level of abstraction are simulated together with a model at higher level of abstraction in parallel using two or more simulators.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 15, 2014
    Inventor: Sei Yang Yang
  • Patent number: 8775148
    Abstract: Software for controlling processes in a heterogeneous semiconductor manufacturing environment may include a wafer-centric database, a real-time scheduler using a neural network, and a graphical user interface displaying simulated operation of the system. These features may be employed alone or in combination to offer improved usability and computational efficiency for real time control and monitoring of a semiconductor manufacturing process. More generally, these techniques may be usefully employed in a variety of real time control systems, particularly systems requiring complex scheduling decisions or heterogeneous systems constructed of hardware from numerous independent vendors.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: July 8, 2014
    Assignee: Brooks Automation, Inc.
    Inventors: Patrick D. Pannese, Vinaya Kavathekar, Peter van der Meulen
  • Patent number: 8774948
    Abstract: There is a method to model large electric power consuming facilities for power system studies. A general facility model, for example a template, is created for different types of industrial or commercial facilities. A template includes all necessary and general electric system information such as the common electric network configuration of a specific type of facilities. The template, stored in a database, is then scaled and adjusted based on the power demand level of the case-specific facility to be modeled based on facility specific parameters acquired for the facility. The result is a full, case-specific model of the facility to be modeled. The case-specific model is simplified into an equivalent model with varying details according to a user's specification. The results are the case-specific facility model of interest to the user. The model is normally included into the power system model of the utility network for power system simulation studies.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: July 8, 2014
    Inventor: Wilsun Xu
  • Patent number: 8775147
    Abstract: An algorithm and architecture are disclosed for performing multi-argument associative operations. The algorithm and architecture can be used to schedule operations on multiple facilities for computations or can be used in the development of a model in a modeling environment. The algorithm and architecture resulting from the algorithm use the latency of the components that are used to process the associative operations. The algorithm minimizes the number of components necessary to produce an output of multi-argument associative operations and also can minimize the number of inputs each component receives.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: July 8, 2014
    Assignee: The MathWorks, Inc.
    Inventors: Alireza Pakyari, Brian K. Ogilvie
  • Patent number: 8776003
    Abstract: The disclosure provides leakage power recovery that considers side transition times of multi-input cells. In one embodiment, a leakage power recovery system is disclosed that includes: (1) a power recovery module that considers side transitions when making a first conditional replacement of a cell in a path of a circuit design with a lower leakage cell and estimates delays and slack of the at least one path of the circuit design, and (2) a speed recovery module that makes a second conditional replacement of a slower lower leakage cell of the path with a higher leakage cell when there is a timing violation with respect to the path, determines if any other cells of the at least one path has a slower input transition and makes a third conditional replacement of a driver thereof to a higher leakage cell when the driver is one of the slower lower leakage cells.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: July 8, 2014
    Assignee: LSI Corporation
    Inventors: Bruce E. Zahn, Donald J. Wingate
  • Patent number: 8775124
    Abstract: A method for generating a set of analytical redundancy relations representative of a system with which a plurality of sensors is associated for the observation of variables indicative of operating conditions and adapted to enable detection and discrimination of faults. A complete set of analytical redundancy relations of the system is built from a set of intermediate relations established between observable and non-observable variables of the system, wherein each intermediate relation is generated by combining two predetermined relations Rj, Rk, each of which is expressed in an implicit form as a tuple (i) of a subset Sj of system variables, (ii) of the set Cj of the support components for said relation, and (iii) of the set Tj of the primary relations used to derive said intermediate relation.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: July 8, 2014
    Assignee: Fondazione Istituto Italiano di Technologia
    Inventors: Amir Fijany, Farrokh Vatan
  • Patent number: 8775588
    Abstract: A physical service and policy model of a service-oriented architecture system is generated from a logic model. Web service policies are transformed from the logical model to the physical model. The logical model includes a plurality of logical service components and logical dependency relationships among the logical service components. At least one of the logical service components has been specified with logical policies. The physical model includes physical components and physical dependency relationships associated with the service components and tire logical dependency relationships among the service components in the logical model. Effective logical policies are calculated for each of the logical service components and mapped to associated physical components in the physical model.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xin Peng Liu, Yu Chen Zhou
  • Patent number: 8775149
    Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: July 8, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventor: Kenneth S. Kundert
  • Publication number: 20140188451
    Abstract: Information for determining a data transfer route which maximizes a total amount of data processed on all of processing servers per unit time is generated.
    Type: Application
    Filed: July 31, 2012
    Publication date: July 3, 2014
    Applicant: NEC CORPORATION
    Inventors: Masato Asahara, Shinji Nakadai
  • Patent number: 8769452
    Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
  • Patent number: 8768675
    Abstract: A method for simulating an effect of at least one electrical/electronic load includes: providing a controllable power supply unit that is connected to at least one terminal of a control unit; and simulating a first current theoretically flowing through a simulated load at the at least one terminal by drawing a second current from the control unit by the controllable power supply unit or impressing a third current on the control unit by the controllable power supply unit.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: July 1, 2014
    Assignee: Dspace Digital Signal Processing and Control Engineering GmbH
    Inventors: Joerg Bracker, Marc Dolle