Simulating Electronic Device Or Electrical System Patents (Class 703/13)
  • Patent number: 10516579
    Abstract: Techniques are disclosed herein for reconciling planned data for a network (such as a fiber optic network) with data describing the deployed network. Network probing and planning components obtain a snapshot of the deployed network and organize the snapshot into three “layers”: the “link layer,” which represents the physical links that underlie the network, the “digital layer,” which includes optical channel groups that divide the total capacity of the physical links, and the “service layer,” which includes the services delivered over the network. The techniques involve comparing the planned data to the deployed data in the order of link layer, digital layer, and service layer. Differences considered to be “minor” are reconciled automatically. Differences that are “major” are reconciled after receiving instructions from a planner or administrator regarding whether to update the planned data based on what was originally in the planned data or what is in the deployed network.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: December 24, 2019
    Assignee: Infinera Corporation
    Inventors: Jayaram Hanumanthappa, Naresh Kumar, Naresh Srinivasulu Jayam, Arijit Mandal, Gounda Mohammed Nabi Saheb, Alok Jain, Steven Joseph Hand
  • Patent number: 10509866
    Abstract: An apparatus includes a memory; and a processor coupled to the memory and configured to: specify a shape type of an opening including a series of planes detected from planes of a plurality of second virtual rectangular parallelepipeds obtained by dividing a first virtual rectangular parallelepiped internally containing a virtual object in a simulated space based on a first shape of a first line obtained by projecting the series of planes from a direction based on a specific plane of the first virtual rectangular parallelepiped onto a projection plane which is perpendicular to the direction and located at a position more distant from the specific plane than the series of planes, calculate a resonance frequency of a wave leaking through the opening, based on the specified shape type of the opening; and present the calculated resonance frequency on a display.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: December 17, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Koji Demizu, Kai Nojima
  • Patent number: 10504802
    Abstract: A method of overlay control in silicon wafer manufacturing comprises firstly locating a target comprising a diffraction grating on a wafer layer; and then measuring the alignment of patterns in successive layers of the wafer. The location of the target may be done by the pupil camera rather than a vision camera by scanning the target to obtain pupil images at different locations along a first axis. The pupil images may comprise a first order diffraction pattern for each location. A measurement of signal intensity in the first order diffraction pattern is then obtained for each location. The variation of signal intensity with location along each axis is then analyzed to calculate the location of a feature in the target.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: December 10, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Naomi Ittah, Nadav Gutman, Eran Amit, Vincent Immer, Einat Peled
  • Patent number: 10503851
    Abstract: In example implementations, a method executed by a processor is provided. The method receives a simulated photonic data input based on a theoretical photonic design that meets a target specification. A complementary metal-oxide semiconductor (CMOS) circuit design is designed based on the simulated photonic data input using a pre-layout simulation. An experimental photonic data input based on a fabricated photonics device that meets the target specification is received. The CMOS circuit is designed based on the experimental photonic data input using a post-layout simulation. A physical circuit CMOS circuit design and a layout that includes detailed physical dimensions associated with the physical CMOS circuit design that is based on the pre-layout and the post-layout are transmitted to a CMOS foundry.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: December 10, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Tsung-Ching Huang, Chin-Hui Chen, Marco Fiorentino, Raymond G. Beausoleil
  • Patent number: 10503855
    Abstract: Methods and systems for SDA of mixed signal electronic circuitry including embedded software designs for creating ASICs, sub-systems, and SoCs. The SDA system described extends IP reuse beyond the circuit and stand-alone verification capabilities that are common practice today which limit the benefits of reuse. By solving the integration problem first in a loosely coupled manner, complex mixed signal SoC devices may achieve higher levels of IP reuse with push button ease through the cloud, significantly improving time to market, design resource limitations, risks for first time silicon success, and the tasks of managing business multiple relationships of IP providers. SDA generated designs use a multi-agent method of operation, creating powerful and flexible designs that provide both NOC (Network on a Chip) and NBC (Network Beyond the Chip) for distributed system operation, and enhanced non-intrusive in-system monitoring for mission critical and safety related applications.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: December 10, 2019
    Inventors: Robert Charles Ledzius, Robert James Stoddard, Greg Allen Hupp, Shalini Batra Sahni
  • Patent number: 10503844
    Abstract: A Discrete Event System model created or provided in a time domain modeling and simulation environment and/or an event domain modeling and simulation environment may be divided into multiple independent regions, e.g. “subgraphs”, to achieve interleaved execution of the components from different domains. The subgraphs are automatically identified by the modeling and simulation environment during the compilation. Each subgraph consists of one or more interconnected event-driven components. Each subgraph is associated with an event calendar that controls the execution of the associated subgraph. Such multiple event calendar design enables multi-domain simulation, where event-driven components modeled by an event domain modeling environment and time-driven components modeled by a time domain modeling environment are simulated in an integrated fashion.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: December 10, 2019
    Assignee: The MathWorks, Inc.
    Inventors: Wei Li, John Edward Ciolfi, Michael I. Clune
  • Patent number: 10495691
    Abstract: A method, system, and architecture (100) for adaptively field testing for hardware faults on an integrated circuit device includes a central quality assurance server (121) which receives specified hardware metric data (131) monitored at an integrated circuit device (110) in the field, identifies prioritized built-in self-test (BIST) fault detection tests (134) based on the specified hardware metric data, securely downloads the prioritized BIST fault detection tests (132) to the integrated circuit device for execution to identify a first hardware fault at the integrated circuit device, and then receives diagnosis information (133) identifying the first hardware fault from the integrated circuit device which is used to update the prioritized BIST fault detection tests.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: December 3, 2019
    Assignee: NXP USA, Inc.
    Inventors: Xiao Sun, Wen Chen, Jayanta Bhadra
  • Patent number: 10489039
    Abstract: An electronic device and an operation method for operating the electronic device are provided to display at least one condition line based on notification conditions; determine at least a part of a section as an activation section for activating at least one object in the at least one condition line; and configure the activation section corresponding to the notification conditions.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: November 26, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Young-Jae Meen
  • Patent number: 10488835
    Abstract: A method for configuring a tester equipped for testing an electronic control unit, wherein a software model of a technical system is executed on the tester and communicates electronically through an input/output interface of the tester with a device connected to the tester. A configuration system is coupled to a modeling system, and a software model characterized by function blocks that are connected to one another is present in the modeling system. The tester is configured in the configuration system by interconnected configuration elements such that physical characteristics of the input/output interface and/or the connection of the input/output interface with the software model are defined via the configuration elements. The configuration system is coupled to the modeling system such that the software model is provided to the configuration system via a coupling interface at the run time of the modeling system.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: November 26, 2019
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventor: Joerg Hagendorf
  • Patent number: 10481990
    Abstract: Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a debug and test access port to debug and test the device circuit, and a switching circuit to switch a debug and test mastership between the debug and test access port and a data access port to the device circuit that is not dedicated to debug and test.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Patrik Eder, Rolf H. Kuehnis, Enrico D. Carrieri
  • Patent number: 10481817
    Abstract: Methods, apparatus, systems and articles of manufacture to optimize dynamic memory assignments in multi-tiered memory systems are disclosed. An example computer readable storage medium comprises instructions to, during an offline profiling run of a computer application: responsive to a first malloc function call, perform a first backtrace to identify a first path preceding the first malloc function call and identify a size of a buffer in memory allocated to the first path; and determine an indicator corresponding to a temperature of the buffer allocated to the first path; and during runtime: responsive to a second malloc function call, perform a second backtrace to identify a second path preceding the second malloc function call; and responsive to the second path corresponding to the first path, allocate memory from a tier of memory based on the indicator.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Kshitij Doshi, Andreas Kleen, Harshad Sane
  • Patent number: 10482213
    Abstract: According to one embodiment, a circuit design support apparatus includes: a first specifying unit that specifies a first element generating negative potential; a second specifying unit that specifies a criterion of a current flowing to a substrate from an electrode of a second element arranged in a peripheral area of the first element due to a parasitic element; a calculation unit that calculates a criterion violation rate under a condition where a location of the second element has been shifted to one of a plurality of places; and a display processing unit that displays, on a display, information indicating the criterion violation rate such that the information is superimposed on a layout.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: November 19, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventor: Sachio Hayashi
  • Patent number: 10482194
    Abstract: Described are techniques for processing a request. Data storage system configuration information is provided which is used by a simulator that simulates a data storage system configuration of a data storage system. A request is received to perform an operation with respect to the data storage system configuration being simulated. The request identifies an object included in the data storage system configuration information used to simulate the data storage system configuration. First processing is performed to simulate servicing the request using the data storage system configuration information and the first processing includes determining, at run time while processing the request, whether the object includes a first object property that is a reference to an embedded object.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: November 19, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Donald E. Labaj, Norman M. Miles, Scott E. Joyce, Timothy J. Cox
  • Patent number: 10474487
    Abstract: A method, system, apparatus and device for managing resources of virtual machines are disclosed by the present disclosure. The method includes obtaining monitoring data of a virtual machine at a client. The method also includes matching the monitoring data with a pre-determined match rule to generate a match result, wherein the match rule determines whether the monitoring data satisfies a match condition of the match rule. The method further includes executing an action for the virtual machine based upon a processing strategy corresponding to the match result.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: November 12, 2019
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Yijun Zhu, Xing Hong
  • Patent number: 10474557
    Abstract: Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for receiving source code of an application, providing intermediate code based on the source code, the intermediate code including at least one instruction for profiling at least one line of the source code, providing profiling data by processing the intermediate code, processing the profiling data based on one or more of a latency model and an energy model to respectively provide at least one latency metric and at least one energy metric of the at least one line, and storing modified source code that is provided based on a modification of the at least one line of source code.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: November 12, 2019
    Assignee: SAP SE
    Inventor: Ahmad Hassan
  • Patent number: 10474775
    Abstract: A method provides modeling a DUT and generating a simulated response. The method includes receiving a first portion of a stimulus signal generated by a signal generator, a second portion of the stimulus signal being input to the DUT; receiving a response signal output by the DUT in response to a second portion of the stimulus signal; digitizing the received first portion and the received response signal; correcting the digitized signals; measuring training input series data of the digitized first portion of the stimulus signal and training output series data of the digitized response signal; and utilizing kernel adaptive filtering for extracting a device model from the training input and output series data, and for generating simulated responses of the DUT to subsequent stimulus inputs, respectively. The kernel adaptive filtering may include a kernel least mean squares algorithm, a kernel Affine projection algorithm or a recursive least squares algorithm.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: November 12, 2019
    Assignee: Keysight Technologies, Inc.
    Inventors: Sho Okuyama, Junichi Iwai
  • Patent number: 10469330
    Abstract: Methods and apparatus for a client account versioning metadata manager for cloud computing environments are disclosed. A system includes a plurality of resources, a plurality of service managers coordinating respective multitenant network-accessible services, and a metadata manager. The metadata manager receives a multi-service account state view request. The metadata manager generates a representation of an administrative state of a client account indicated by the request with respect a plurality of services accessible by the client account, as of a time indicated in the request. The administrative state with respect to a particular service comprises an indication of an assignment to the client account of resources participating in implementation of the particular service.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: November 5, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Gregory B. Roth, James E. Scharf, Jr., Rajiv Ramachandran, Anders Samuelsson, Keith A. Carlson
  • Patent number: 10466976
    Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: November 5, 2019
    Assignee: Cavium, LLC
    Inventors: Ajeer Salil Pudiyapura, Kishore Badari Atreya, Ravindran Suresh
  • Patent number: 10459345
    Abstract: A method to improve a lithographic process of processing a portion of a design layout onto a substrate using a lithographic apparatus, the method including: adjusting a first processing parameter among processing parameters of the lithographic process to cause the processing to be more tolerant to perturbations of at least one of the processing parameters during processing; and adjusting a second processing parameter among processing parameters of the lithographic process to cause the processing to be more tolerant to perturbations of at least one of the processing parameters during processing.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: October 29, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Stefan Hunsche, Chiou-Hung Jang, Marinus Jochemsen, Vito Tomasello
  • Patent number: 10459828
    Abstract: A method for application testing recommendation includes deploying a software application to first testers having first system configurations, and receiving testing coverage data describing (i) a first subset of features of the software application being tested by the first testers and (ii) information describing the first system configurations. The method further includes deploying the software application to a marketplace, and receiving market coverage data describing (i) a second subset of features being used by market users and (ii) second system configurations of the market users. The method further includes comparing the market coverage data and the testing coverage data to identify a coverage discrepancy, selecting second testers to test the software application based on the coverage discrepancy, and deploying the software application to the second testers.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: October 29, 2019
    Assignee: Google LLC
    Inventors: Jeffrey Seibert, Jr., Wayne Chang
  • Patent number: 10452393
    Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: October 22, 2019
    Assignee: Montana Systems Inc.
    Inventors: Vivian Chou, Julien Lamoureux, Sherman Lee
  • Patent number: 10453110
    Abstract: A method is disclosed that includes identifying an inventory item corresponding to a product configuration. The product configuration is defined using a feature map. The inventory item is also defined using the feature map. Each entry of the feature map corresponds to one of a number of features of a product.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: October 22, 2019
    Assignee: Versata Development Group, Inc.
    Inventors: Grant M. Emery, Arpan Shah
  • Patent number: 10434415
    Abstract: The subject matter discloses a method performed by a computerized server communicating with multiple computerized devices, at least some devices are wearable devices associated with users, for planning a real world location. The method comprises receiving information concerning a real world location, modeling the real world location into a virtual location, receiving a plurality of requests for modifying said virtual location from the users via wearable devices, the requests comprise operations, selecting an operation for modifying the virtual location, processing said selected operation for modifying said virtual location and transmitting the selected operation to a computerized device of a person, thereby instructing the person to modify said real world location according to the selected operation.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: October 8, 2019
    Inventor: Yaacov Barki
  • Patent number: 10425320
    Abstract: Methods, systems, and computer readable media for network diagnostics are disclosed. According to one method, the method occurs at a diagnostics controller implemented using at least one processor. The method includes configuring a plurality of diagnostics nodes to observe traffic behavior associated with a system under test (SUT). The method also includes observing, using the diagnostics nodes, traffic behavior associated with the SUT. The method further includes detecting, using the traffic behavior, a SUT issue. The method also includes identifying, using SUT topology information, a network node in the SUT associated with the SUT issue. The method further includes triggering one of the diagnostics nodes to obtain node related information from the network node, wherein the diagnostics node uses at least one communications protocol to poll the network node for the node related information. The method also includes diagnosing, using the node related information, the SUT issue.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: September 24, 2019
    Assignee: KEYSIGHT TECHNOLOGIES SINGAPORE (SALES) PTE. LTD.
    Inventors: Marius Pavel Nistor, Silviu Ionut Niculescu, Alexandru-Bogdam Stefan
  • Patent number: 10423740
    Abstract: Some embodiments of the present invention provide techniques and systems for simulating a circuit design so that the simulation follows hardware semantics. Specifically, some embodiments ensure that the simulation follows hardware semantics by properly handling race conditions in state elements and/or glitches in clock trees that can occur during logic simulation. Each logic simulation cycle can include two stages: a stimuli application stage in which the system evaluates signal values of the circuit design which do not depend on a clock signal, and a clock propagation stage in which the system evaluates signal values that depend on a clock signal. Some embodiments of the present invention sample signal values during the stimuli application stage, and use the sampled signal values during the clock propagation stage to handle race conditions in state elements and/or glitches in clock trees that may occur during logic simulation.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: September 24, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Alexander Rabinovitch, Ramesh Narayanaswamy
  • Patent number: 10424120
    Abstract: The quality of service one may expect from a given network is often hard to determine in advance. Further, given agreements between network service providers and a variety of content providers, the complexity inherent in selecting a given available network is increasing for consumers. Embodiments described herein provide mechanisms for creating an augmented reality presentation of networks and the service quality of those networks. The presentation may display information regarding a variety of factors including content transit agreements with content providers, quality-of-service or prioritization guarantees for certain types of content, or low-level Wi-Fi signal quality. These presentations allow users to ascertain where in a given spatial area good quality is available for whichever services they intend to use.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: September 24, 2019
    Assignee: PCMS Holdings, Inc.
    Inventor: Keith Edwards
  • Patent number: 10423742
    Abstract: A method and apparatus for on chip variation path-based pessimism reduction and improving analysis of a hierarchical integrated circuit design in an electrical circuit. The circuit has one or more block circuit levels and a top circuit level. The method in one embodiment comprises characterizing the top circuit level to produce a context function, the context function used by the block circuit level for evaluation.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: September 24, 2019
    Assignee: Synopsys, Inc.
    Inventors: Qiuyang Wu, Martin Ranke, Min Li
  • Patent number: 10423884
    Abstract: Methods and devices for providing and using a technical computing environment (TCE) for receiving a TCE model that, when executed, simulates behavior of a dynamic physical system, and that represents one or more physical components and their respective reliability information in a block diagram model. Applications of the model include automated system-level datasheet and bill of materials generation, component reliability information discovery, fault and stress assertions, and identification of emergent faults.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: September 24, 2019
    Assignee: The MathWorks, Inc.
    Inventors: Richard Hyde, Ebrahim M. Mestchian
  • Patent number: 10417239
    Abstract: Profiling data characterizing a data streaming application is used to predict data which will need to be retrieved by a processing element during execution of the data streaming application. Data is retrieved responsive to the prediction, in advance of actual demand by the processing element which requires it. Prediction may be based at least in part on upstream tuple contents, and could include other historical data retrieval patterns. In some embodiments, retrieval of predicted data may be delayed so that data is retrieved just in time.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: September 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric L. Barsness, Daniel E. Beuch, Michael J. Branson, John M. Santosuosso
  • Patent number: 10409938
    Abstract: According to one embodiment, a method, computer system, and computer program product for creating a plurality of process parameters in a circuit design is provided. The present embodiment of the invention may include receiving one parasitic extraction per layer of a circuit is used to obtain a resistance base factor and a capacitance base factor. The embodiment may further include performing Monte Carlo simulations to determine distributions of capacitance and resistance for each metal layer of the circuit, and creating scalars that scale each of the resistance base factor and the capacitance base factor to a minimum and maximum process limit. Additionally, the embodiment may include defining at least one delay corner using the created scalars, and receiving the results of one or more timing analyses performed using the resistance base factor and the capacitance base factor, and the defined delay corner to determine a delay variability per layer.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: September 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric Foreman, Ning Lu, Jeffrey Hemmett
  • Patent number: 10401818
    Abstract: A method and apparatus for automatic recognition of similarities between perturbations in a network, the apparatus includes a memory unit for storing a first data array of multiple perturbation data snapshots each recorded in response to a perturbation observed in the network; a generation unit adapted to generate by machine learning a data model of perturbations trained on the first data array, wherein the trained data model provides a latent vector representation for each of the perturbations; a recording unit adapted to record a perturbation data snapshot if a perturbation is observed during operation of said network and adapted to provide a corresponding second data array for the recorded perturbation data snapshot; and a processing unit adapted to derive a latent vector representation for the observed perturbation from the second data array using the trained data model of perturbations.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: September 3, 2019
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Denis Krompaß, Andreas Litzinger, Sebnem Rusitschka, Volker Tresp
  • Patent number: 10402526
    Abstract: Design of a power delivery network (PDN) is integrated with a digital logic design flow.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: September 3, 2019
    Assignee: Chaoyang Semiconductor Jiangyin Technology Co., Ltd.
    Inventors: Taner Dosluoglu, Anatoly Gelman
  • Patent number: 10394991
    Abstract: An offloading engine integrated circuit that includes soft processors may be implemented using an aggregated profiler and a soft processor system generation tool. In particular, the aggregated profiler may generate a suggested configuration for soft processors within the integrated circuit. The soft processor system generation tool may use inputs based on the suggested configuration to generate a configuration bit stream that is used to configure the integrated circuit. Soft processors within the integrated circuits may be arranged in soft processors columns. Parameters for the soft processors and the soft processor columns may be dynamically reconfigured. The parameters may include sizes for each soft processor column, a number of soft processor columns, types (e.g., processor architecture types) of each processor. Multiple soft processor columns may also be grouped together to complete a single task. Interface circuitry may regulate information flow to and from the soft processor columns.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: August 27, 2019
    Assignee: Altera Corporation
    Inventors: Chee Nouk Phoon, Chee Hak Teh, Kenneth Chong Yin Tan, Kah Wai Lee
  • Patent number: 10394999
    Abstract: A computer-implemented method includes identifying a noise cluster, representing the noise cluster according to a variational model, projecting the variational model onto one or more corners to yield a projected noise cluster, and determining a computed noise for the projected noise cluster. Optionally, the noise cluster includes one or more noise cluster elements, and each of the noise cluster elements are expressed as one or more circuit element terms, according to a canonical form. Optionally, at least one of the corners is a bounding corner. For the bounding corner, the projected noise cluster is generated by maximizing the circuit element terms for those noise cluster elements that tend to increase noise, and by minimizing the circuit element terms for those noise cluster elements that tend to decrease noise, whereby noise is maximized for the canonical form. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Kurtz, Mark A. Lavin, Ronald D. Rose, Richard W. Taggart, Vladimir Zolotov
  • Patent number: 10397081
    Abstract: The invention relates to a method for forcing fail-silent behavior of a periodically functioning, distributed real-time computer system, which real-time computer system comprises at least two redundant NSCFCUs. At the beginning of a frame, the at least two redundant NSCFCUs (110, 111) are supplied with the same input data, wherein each of the redundant NSCFCUs calculates a result, preferably by means of a deterministic algorithm, particularly from the input data, and wherein this result is packed into a CSDP with an end-to-end signature, and wherein the CSDPs of the NSCFCUs (110, 111) are transmitted to an SCFCU (130), and wherein the SCFCU (130) checks whether the bit patterns of the received CSDPs are identical, and, if disparity of the bit patterns is found, prevents further transmission of the CSDPs, particularly those CSDPs in which disparity was found. Furthermore, the invention relates to a periodically functioning, distributed real-time computer system.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: August 27, 2019
    Assignee: TTTech Auto AG
    Inventors: Stefan Poledna, Hermann Kopetz
  • Patent number: 10394226
    Abstract: A control parameter optimizing system and an operation optimizing apparatus equipped therewith are provided, the system being applicable to an existing plant without modifying the control panel or equipment of the plant, the system further being capable of optimizing the operation control of the plant in accordance with diverse operational requirements. The system includes an objective function setting section, a plant model, and a control parameter optimizing section. The control parameter optimizing section includes an optimization control parameter selecting section and an optimization control parameter adjusting section. The optimization control parameter selecting section selects as an optimization control parameter the control parameter for optimizing an objective function based on control logic information extracted from a power plant.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: August 27, 2019
    Assignee: Mitsubishi Hitachi Power Systems, Ltd.
    Inventors: Yasuhiro Yoshida, Takuya Yoshida, Takaaki Sekiai, Yuya Tokuda, Kazunori Yamanaka, Atsushi Yamashita, Norihiro Iyanaga
  • Patent number: 10387205
    Abstract: A system and method for optimizing runtime environments for applications by running the applications in a plurality of runtime environments and iteratively selecting and creating new runtime environments based on a fitness score determined for the plurality of runtime environments.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: August 20, 2019
    Assignee: PAYPAL, INC.
    Inventor: Shlomi Boutnaru
  • Patent number: 10386394
    Abstract: A measuring device providing a display device. The operation of the measuring device can be adapted by a user. In this context, operation includes the input and output of parameters in dialogs and the switching between dialogs. The display device displays the dialogs and can display several dialogs simultaneously. The input of given values in given dialogs effects the opening and/or closing of at least one respectively associated further dialog. The content and/or the position and/or the form and/or the linking of the dialogs are adapted. The operation of the measuring device is functional during the adaptation. Exclusively the currently-displayed dialogs are adaptable.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: August 20, 2019
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventor: Joachim Eibl
  • Patent number: 10380796
    Abstract: A system for computer vision is disclosed. The system may comprise a processor and a non-transitory computer-readable storage medium coupled to the processor. The non-transitory computer-readable storage medium may store instructions that, when executed by the processor, cause the system to perform a method. The method may comprise obtaining a first and a second images of at least a portion of an object, extracting a first and a second 2D contours of the portion of the object respectively from the first and second images, matching one or more first points on the first 2D contour with one or more second points on the second 2D contour to obtain a plurality of matched contour points and a plurality of mismatched contour points, and reconstructing a shape of the portion of the object based at least in part on at least a portion of the matched points and at least a portion of the mismatched contour points.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: August 13, 2019
    Assignee: uSens, Inc.
    Inventors: Gengyu Ma, Yuan Wang, Yue Fei
  • Patent number: 10379524
    Abstract: A method and apparatus for managing a display of an assembly model. The assembly model is displayed in an initial state within a first display area in a graphical user interface. A first display state of an item of the assembly model is changed to a second display state within the first display area in response to receiving a first type of input. The second display state of the item of the assembly model is changed to a third display state within the first display area in response to receiving a second type of input. An entry is added to an assembly hierarchy within a second display area in the graphical user interface in response to the second display state of the item changing to the third display state.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: August 13, 2019
    Assignee: The Boeing Company
    Inventors: Christopher J. Senesac, David J. Kasik
  • Patent number: 10373214
    Abstract: A method includes generating a delta price and generating a final price using the delta price. A process and system provide an ability to determine a product's final price with a selected set of features in which multiple configurations are to be generated. The ability to determine such final prices can be based on the ability to determine the change in price between one configuration of a product and that of another product configuration (e.g. the product configured with the desired feature(s)). A customer is able to select one or more features, and so view the effect on the product's final price, as well as compare the prices (and incremental price differences) between various configurations of a given product. This increases the likelihood of the purchase being made, because it provides the potential purchaser with the final price earlier in the sales cycle.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: August 6, 2019
    Assignee: Versata Development Group, Inc.
    Inventors: Thomas J. Carter, III, Meetesh M. Karia, August R. Buerkle, Boris Motik, Ramanathan Ramadass, Reuben Swartz
  • Patent number: 10374907
    Abstract: Disclosed are a fine-grained resource control method and apparatus. The method includes: defining, for a function of which resource usage is needed to be restricted, a license item in a license file, wherein the license item is used for representing a resource restriction number for supporting the function; and judging whether a preferential support command is preset for resources of the function, if presetting, controlling the resources of the function according to the preferential support command, a value of the license item and an actual resource number for supporting the function, otherwise, controlling the resources of the function directly according to the value of the license item and the actual resource number for supporting the function.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: August 6, 2019
    Assignee: ZTE CORPORATION
    Inventor: Longbin Hu
  • Patent number: 10372584
    Abstract: While the effectiveness of a model inspection method as a means for detecting software defects is known, large-scale software cannot be handled due to great amounts of calculation required for inspection. According to the present invention, after a model inspection problem of software is attributed to be a satisfiability determination problem, the problem is converted to a type that can be solved by a solver used for solving a notification optimization problem having constrained conditions, and the satisfiability is determined in a numerically analytical manner.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: August 6, 2019
    Assignee: HITACHI, LTD.
    Inventor: Masataka Nishi
  • Patent number: 10372576
    Abstract: A storage unit stores a trace file obtained by simulating an operation of an object. A reception unit receives a forward direction reproduction instruction. A reproduction unit reads each piece of trace data from the trace file. The reproduction unit determines a timing for updating a graphic display, based on a new display time corresponding to an occurrence time included in new trace data read this time and an old display time corresponding to an occurrence time included in old trace data read last time. A display unit changes a state of the object displayed by the graphic display to a state indicated by a new state value included in the new trace data, at the determined timing.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: August 6, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hirokazu Suzuki
  • Patent number: 10366195
    Abstract: Any primitive cells or blocks can be represented physically by a Barycenter compact model (or Barycenter model), and any black box model can also be physically represented by a Barycenter compact model physically. A hierarchical boundary condition between blocks is formulated by the Barycenter compact model. Hierarchical boundary condition problems between blocks can be limited within two levels only if using the Barycenter compact model.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: July 30, 2019
    Assignee: Worldwide Pro Ltd.
    Inventor: William Wai Yan Ho
  • Patent number: 10366542
    Abstract: A method comprising: causing display of a sound-source virtual visual object in a three-dimensional virtual visual space; causing display of a multiplicity of interconnecting virtual visual objects in the three-dimensional virtual visual space, wherein at least some of the multiplicity of interconnecting virtual visual objects interconnect visually a sound-source virtual visual object and a user-controlled virtual visual object, wherein a visual appearance of each interconnecting virtual visual object, is dependent upon one or more characteristics of a sound object associated with the sound-source virtual visual object to which the interconnecting virtual visual object is interconnected, and wherein audio processing of the sound objects to produce rendered sound objects depends on user-interaction with the user-controlled virtual visual object and user-controlled interconnection of interconnecting virtual visual objects between sound-source virtual visual objects and the user-controlled virtual visual obje
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: July 30, 2019
    Assignee: Nokia Technologies Oy
    Inventors: Arto Lehtiniemi, Antti Eronen, Jussi Leppänen, Juha Arrasvuori
  • Patent number: 10367591
    Abstract: An optical driver is disclosed, including a PMOS pull-up circuit, an NMOS pull-down circuit, and an inductive circuit. The PMOS pull-up circuit may include a first terminal to receive a first input signal based on a received data signal, and a P output terminal coupled to the inductive circuit. The NMOS pull-down circuit may include a second input terminal to receive a second input signal based on the received data signal, and an N output terminal coupled to the inductive circuit. The inductive circuit may include an L output terminal to output an output signal, a P coil coupled between the P output terminal and the L output terminal, and an N coil coupled between the N output terminal and the L output terminal.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: July 30, 2019
    Assignee: XILINX, INC.
    Inventor: Mayank Raj
  • Patent number: 10360077
    Abstract: For measuring component utilization in a computing system, a server energy utilization reading of a statistical significant number of servers out of a total number of servers located in the datacenter is obtained by measuring, at predetermined intervals, a collective energy consumed by all processing components within each server. The collective energy is measured by virtually probing thereby monitoring an energy consumption of individual ones of all the processing components to each collect an individual energy utilization reading, where the individual energy utilization reading is aggregated over a predetermined time period to collect an energy consumption pattern associated with the server utilization reading.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruchi Mahindru, John A. Bivens, Koushik K. Das, Min Li, HariGovind V. Ramasamy, Yaoping Ruan, Valentina Salapura, Eugen Schenfeld
  • Patent number: 10353719
    Abstract: A system, method, and computer-readable medium are disclosed for performing a validation precomputation operation for use with a configurator, comprising: identifying a plurality of webpages within a configurator, the plurality of webpages allowing a user to configure a system, each webpage of the plurality of webpages enabling the user to select an option from a plurality of options; performing a validation precomputation operation on each of the plurality of webpages, the validation precomputation operation identifying invalid combinations of options from the plurality of options; storing the invalid combinations of options within an array; and, associating the array storing the invalid combinations of options with a respective webpage within the configurator.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: July 16, 2019
    Assignee: Dell Products L.P.
    Inventors: Rajesh B. Kaimal, Evan P. Hashemi
  • Patent number: 10356116
    Abstract: An Identity Based Behavior Measurement Architecture (such as the BMA) and related technologies are described herein. In an exemplary embodiment, the BMA can be derived from an IMA and use an identity model to express a deterministic measurement value for platform behavior.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: July 16, 2019
    Assignee: IDfusion, LLC
    Inventors: Gregory Henry Wettstein, Scott Byron Stofferahn, Richard William Engen, Johannes Christian Grosen