Simulating Electronic Device Or Electrical System Patents (Class 703/13)
  • Patent number: 10353745
    Abstract: Systems and methods are described for accurately determining the performance of a networked computing environment relative to the predicted performance of a target computing environment. The computing environment performance for a particular workload are related to each other by determining a coefficient of equivalency. The coefficient of equivalency may be determined based on the time, cost, or other criteria associated with executing the workload, and may be determined by assessing the relative performance of various computing resources (such as central processing units and computer-readable media) in the respective environments and assessing the demand placed upon these resources by the particular workload. The coefficient of equivalency may further be determined based in part on capacity limitations and substitutions of one computing resource for another in the respective computing environments.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: July 16, 2019
    Assignee: Amazon Technologies, Inc.
    Inventor: Abdul Sathar Sait
  • Patent number: 10338895
    Abstract: In one embodiment, a graphical user interface (GUI) is established for an Internet of Things (IoT) integrated developer environment (IDE) with one or more visual developer tools. Real and/or virtual nodes are provided within the IoT IDE having connectivity and functionality, and a plurality are connected as a logical and executable graph for a flow-based programming framework virtualized across one or more IoT layers. The nodes may then be programmed based on respective connectivity and functionality, such that the logical and executable graph has real and/or virtual inputs, real and/or virtual processing functions, and real and/or virtual actions. Upon deploying the node programming to one or more corresponding platform emulators configured to execute the node programming, the logical and executable graph may be simulated by executing the node programming to produce the one or more actions based on the one or more inputs and the one or more processing functions.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: July 2, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Yajun Zhang, Haihua Xiao, Rizhi Chen, Ashutosh A. Malegaonkar, Wael Kamel, Aikepaer Abuduweili, Susie Wee
  • Patent number: 10338117
    Abstract: Methods and systems are provided for determining the surface electromagnetic impedance of a conductive element and applying the diffuse field reciprocity principle using that surface electromagnetic impedance to determine electric fields induced in the conductive element. An exemplary method involves determining a surface electromagnetic impedance matrix for the conductive element based on its physical dimensions and an excitation frequency for an incident electromagnetic wavefield, applying diffuse field reciprocity to determine a metric indicative of an induced field based on the surface electromagnetic impedance matrix and an energy metric for the incident electromagnetic wavefield, and displaying a graphical representation of the metric on a display device.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: July 2, 2019
    Assignees: Dassault Systemes Simulia Corp.
    Inventor: Robin Stewart Langley
  • Patent number: 10331547
    Abstract: The present disclosure relates to a method for reusing a debugging workspace in an electronic design environment. Embodiments may include performing, using a processor, a verification of an electronic design and identifying at least one triggered property associated with the electronic design. Embodiments may further include identifying at least one fan-in signal associated with the at least one triggered property of the electronic design. Embodiments may also include determining a start point debug location based upon, at least in part, the at least one fan-in signal, wherein the start point debug location includes at least one of signal information, cycle information, and event time information. Embodiments may further include generating a debug workspace, wherein generating includes adding at least one additional debug location and storing a cycle of the additional debug location as a relative cycle that is relative to another debug location associated with the debug workspace.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: June 25, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chien-Liang Lin, Chung-Wah Norris Ip
  • Patent number: 10331825
    Abstract: A disclosed system of an emulation environment performs a simulation to construct a waveform of a target signal based on signals traced by an emulator for a time frame including multiple clock cycles. In one embodiment, a simulation is performed in a manner that an input of the logic gate, in a first duration of the time frame at which an output of the logic gate depends on the input, is analyzed to obtain the output, and the input of the logic gate, in a second duration of the time frame at which the output of the logic gate is independent, is omitted. In one aspect, the input of the logic gate is simulated for the first duration based on a periodicity in a waveform of the input in the first duration.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: June 25, 2019
    Assignee: Synopsys, Inc.
    Inventors: Johnson Adaikalasamy, Gagan Vishal Jain, Stanislav Margolin
  • Patent number: 10331821
    Abstract: A method, apparatus and computer readable medium for performing a computer simulation a physical object, includes receiving at least one selection by a user with respect to usage of a simpler model or a more complex model to be used to model at least one attribute of the physical object; performing a computer simulation of the physical object based on the at least one selection received from the user; and rerunning the computer simulation a plurality of times using results obtained from earlier run computer simulations, to obtain an accurate representation of the physical object.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: June 25, 2019
    Assignee: MSC.Software Corporation
    Inventors: Douglas Brennan, Douglas James Neill, Herbert Dennis Hunt, Kunaseelan Kanthasamy
  • Patent number: 10331824
    Abstract: A system-level simulation includes generating netlist information including component library information, which describes instances of the hardware components, and component instance information, which describes component dynamic libraries that include models of hardware components. The simulation is generated at simulation run-time based on the netlist information. Component dynamic libraries corresponding to the component library information are loaded based on the component library information. A simulation dynamic library referenced by the component dynamic libraries is loaded. One or more interlibrary adapters corresponding to the component dynamic libraries are loaded to provide compatibility between the component dynamic libraries and an application binary interface of the simulation dynamic library. Instances of hardware components are instantiated based on the component instance information, and the instantiated instances of the hardware components are connected to form the simulation.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: June 25, 2019
    Assignee: Synopsys, Inc.
    Inventors: Olivier P. F. Dumont, Thomas M. Philipp
  • Patent number: 10325788
    Abstract: A manipulated variable calculator having a plurality of control loops and configured to calculate manipulated variables to be respectively given to a plurality of temperature adjusters includes: a reference model output generator configured to generate a reference model that generates a response output until reaching a temperature setpoint when, in the plurality of control loops, a manipulated variable of a control loop having the slowest response speed is defined as 100%; a simulator configured to sequentially search for a switching time to determine a manipulated variable pattern; a reference model configured to generate a reference model output based on the searched switching time; and a reference model selecting unit configured to select the reference model depending on a heating responsiveness and a cooling responsiveness of the temperature adjusters.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: June 18, 2019
    Assignee: KELK Ltd.
    Inventor: Kazuhiro Mimura
  • Patent number: 10320579
    Abstract: An index generating apparatus acquires values corresponding to a plurality of respective attributes of a number that appears in a piece of target text data. The index generating apparatus then maps the values corresponding to the respective attributes to value ranges of the respective attributes. The index generating apparatus then generates a bitmap index indicating bitmap data in which a position at which the number appears is mapped to each of a plurality of value ranges.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 11, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Masahiro Kataoka, Toshihiro Nishimura, Yukari Hakamata
  • Patent number: 10316625
    Abstract: Methods, computer-readable media, and computing systems for maintaining a well production model. The method includes receiving an update to a parameter of the model of a well, and updating the model based on the update. The method also includes splitting the model into at least two submodels after updating the model, and running the submodels to obtain results. The method further includes determining that the results obtained by running the submodels do not match, and in response to determining that the results obtained by running the submodels do not match, calibrating the model based on the update.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: June 11, 2019
    Assignee: Schlumberger Technology Corporation
    Inventors: Carlos Arturo Garcia Zurita, Franz Fuehrer, Riku Vilkki, Henry David Torres Rincon
  • Patent number: 10317461
    Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: June 11, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10318692
    Abstract: Some embodiments can receive a netlist for the circuit design, wherein the netlist is divided into a set of blocks and a top-level netlist. Next, the embodiments can create (1) a top-level netlist abstraction based on the top-level netlist, and (2) for each block in the set of blocks, create a block abstraction based on a portion of the netlist that is in the block and create virtual pin cells in the block, wherein each virtual pin cell corresponds to a connection that crosses a boundary of the block. The embodiments can then place the top-level netlist abstraction in the layout area, the set of blocks in the layout area, the block abstractions in corresponding blocks, and the virtual pin cells in corresponding blocks. The placed circuit abstraction can then be used to drive standard cell placement in the circuit design.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: June 11, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Douglas Chang, Balkrishna R. Rashingkar
  • Patent number: 10318678
    Abstract: A three-dimensional optoelectrical simulation includes generating a process simulation result including a doping profile of a silicon substrate of image sensor, a structure simulation result with respect to a back end of line structure, and a merged result generated by merging a process simulation result and a structure simulation result, selectively extending the merged result to an extended result by using a process simulation result or a structure simulation result, generating a segmented result for each pixel based on a merged result or an extended result, an optical crosstalk simulation result of image sensor based on a structure simulation result and an optical mesh, and a final simulation result including an electrical crosstalk simulation result of the image sensor based on a segmented result for each pixel and an optical crosstalk simulation result.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wook Lee, Han-Gu Kim, Young-Keun Lee, Jong-Sung Jeon
  • Patent number: 10310881
    Abstract: A method for managing a virtual infrastructure is described. The method includes: generating a configuration information model representing a virtual infrastructure based on known virtual machines and network settings thereon; querying one or more sources of truth other than the known virtual machines, wherein the one or more sources of truth includes a data storage that stores at least one data object that answers a particular question; and comparing the data from the one or more sources of truth with a store of configuration model information, wherein the configuration model information comprises a time stamp and a source identifier; based on the comparing, generates a set of rules; and based on the set of rules, updates the configuration information model.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: June 4, 2019
    Assignee: VMware, Inc.
    Inventors: David Byard, Wit Riewrangboonya, Nick Tenczar
  • Patent number: 10304256
    Abstract: Methods for cleaning a point cloud using an electronic computing device are presented, the method including: causing the electronic computing device to decompose the point cloud into a number of cell voxels; removing a number of outlier cell voxels; subsampling the point cloud; removing a first number of outlier points; removing a number of double surfaces; and removing a second number of outlier points. In some embodiments, method further include outputting a clean point cloud to file. In some embodiments, the causing the electronic computing device to decompose the point cloud further includes: reading into memory a number of points corresponding with the point cloud; specifying a cell voxel size; creating a cell grid to chunk the point cloud into a number of smaller sets; sorting the number of points into the number of cell voxels; and merging all point clouds.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: May 28, 2019
    Assignee: INDOOR REALITY INC.
    Inventor: Damian Mrowca
  • Patent number: 10303832
    Abstract: A specification editing unit edits a hardware specification file in order to replace a plurality of arrays used in a plurality of processes with a shared array. If a post-edit hardware specification file does not satisfy constraint, a specification transforming unit transforms the hardware specification file so that the plurality of processes are executed in a parallel manner. An architecture generating unit generates an architecture file expressing an architecture of an SoC (System On Chip) having hardware corresponding to the hardware specification file.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: May 28, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Naoya Okada, Ryo Yamamoto, Koki Murano, Yoshihiro Ogawa, Noriyuki Minegishi
  • Patent number: 10304131
    Abstract: Market data is recorded from a real live exchange. The recording data can be played back in real time or delayed, in any manner, to simulate the recorded market. Moreover, one or more users can participate in the simulated market just as if they were participating in a real-live market. The system provides a realistic trading environment without the associated risks of trading in a live-market such as losing money and the cost of making trades. The system may be used for training purposes and for purposes of testing and analyzing various trading strategies. Software developers and testers may also utilize the realistic environment to develop trading products or applications. Additionally, the system provides a means for demonstrating trading application products.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: May 28, 2019
    Assignee: Trading Technologies International, Inc.
    Inventors: Sagy P. Mintz, Robert West, Christos Kondilis
  • Patent number: 10296450
    Abstract: The present disclosure involves systems, software, and computer implemented methods for testing applications on multiple system landscapes. In one example, a method may include identifying instructions to test a plurality of system landscapes, executing a test of a first system landscape from the plurality of system landscapes, validating a response received from the first system landscape by a user associated with the testing, executing tests of at least a subset of the remaining plurality of system landscapes which includes sending requests including the predefined input to the entry point of each of the subset of the remaining plurality of system landscapes, receiving responses from the subset of the remaining plurality of system landscapes, and comparing each received response to the validated response from the first system landscape, and in response to the comparison, generating a result set of the comparison of each received response to the validated response.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: May 21, 2019
    Assignee: SAP Portals Israel Ltd
    Inventor: Vitaly Vainer
  • Patent number: 10296671
    Abstract: A method and apparatus for performing a simulation by using a plurality of N processors in parallel include dividing the simulation scenario into N parts to distribute a simulation scenario to each of the processors; performing a high-detail simulation by using a first processor to which a part that includes a beginning part of the divided simulation scenario is distributed, from among the N processors; performing a fast simulation by using each of N?1 processors, other than the first processor; and performing a high-detail simulation based on a snapshot that is generated after the fast simulation is finished, by using each of the N?1 processors.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: May 21, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Tai-song Jin
  • Patent number: 10296669
    Abstract: A method for estimating grid properties of a power grid coupled to a generator at a point of common coupling is provided. First, a voltage VPCC at the point of common coupling is measured. Second, a current IPCC at the point of common coupling is measured. Third, the grid properties are estimated by a grid model using as input parameters the measured voltage VPCC at the point of common coupling, the measured current IPCC at the point of common coupling and the determined phase angle. Advantageously, the absolute phases of the voltage and the current at the point of common coupling are not necessary, which makes the present method less prone to errors due to measurement noise. Further, a device and a computer program product are provided.
    Type: Grant
    Filed: June 28, 2014
    Date of Patent: May 21, 2019
    Assignee: Siemens Aktiengesellschaft
    Inventors: Bjorn Andresen, Per Egedal, Dragan Obradovic, Ruxandra Scheiterer, Andrei Szabo
  • Patent number: 10291641
    Abstract: Assessment of threat risks associated with a given mobile device application (app) on a device type specific basis, so that the threat assessment is specific to a particular device type that is suitable for running the given app. The assessed device-type-specific risk is represented as device-type-specific risk metadata, which is associated as metadata with the given app. For example, the metadata may be stored along with the given app in a common repository that includes many apps. In some embodiments, the device-type-specific risk metadata is generated and stored comprehensively for all apps and device types used in an enterprise. The device-type-specific risk assessment, and corresponding device-type-specific risk metadata, may be based upon run time behavior of the given app on a given device type.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Vikas B. Desai, Carsten Hagemann, Christopher J. Hockings, Mark D. Johnston
  • Patent number: 10290048
    Abstract: A virtual reality operation platform structure comprises a main virtual frame, a virtual reality operation processing module, a menu module, an output checking module, a clearing module, and an accounting module. The menu module is built-in the main virtual frame and includes a housing menu defaulted a plurality of housings, a motherboard menu defaulted a plurality of motherboards, and a heat dissipation assembly menu defaulted a plurality of elements. Each element is virtually electrically coupled to the motherboard with the virtual reality operation processing module. The output checking module is connected to the menu module for checking an output performance of the motherboard and then generating a performance form. The clearing module is connected to the menu module for processing the re-selection of the menu module. The accounting module is connected to the menu module and generates a list.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: May 14, 2019
    Assignee: Bitspower International Co., Ltd.
    Inventor: Vincent Yu
  • Patent number: 10275409
    Abstract: A metadata management system receives metadata changes and automatically updates a metadata architecture which maps the data. The metadata changes may be received through a simple user interface by a user or administrator. Once received, the system may automatically update schemas and data transformation code to process data according to the new data mapping preference. The system may handle metadata updates in a multi-tenant system having one or more applications per tenant, and may update data for a single tenant and 1 or more tenant applications in a multitenancy.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: April 30, 2019
    Assignee: DELL PRODUCTS L.P.
    Inventors: David Tung, Hon Yuk Chan, Ketan Bengali, Sasmita Patra, Ming Chang
  • Patent number: 10270251
    Abstract: An emulator apparatus that emulates entities included in a microgrid is described herein. The emulator apparatus emulates a load with time-varying inductance/resistance or an energy storage device or combination of energy storage devices. The emulator apparatus is electrically coupled to a system or device that is desirably tested/maintained/designed. The emulator apparatus emulates a particular device, and response of the system of device to the emulated device is monitored for purposes of design, testing, or maintenance.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: April 23, 2019
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Jason C. Neely, Steven F. Glover
  • Patent number: 10263106
    Abstract: A power mesh-on-die apparatus includes a solder trace that enhances current flow for a power source trace between adjacent power bumps. The solder trace is also applied between power drain bumps on a power drain trace.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 16, 2019
    Assignee: Intel IP Corporation
    Inventors: Bernd Waidhas, Sonja Koller, Georg Seidemann
  • Patent number: 10263879
    Abstract: An aspect includes input/output (I/O) stack modeling. A processor determines a client configuration of a client I/O stack that includes layers with configurable parameters to control storage and retrieval of data between an uppermost layer and lowest layer. A model of the client I/O stack is built on a layer basis that defines input workload characteristics, output workload characteristics, and layer configuration parameters for the layers of the model based on the client configuration. Workload characteristics of the uppermost layer of the client I/O stack are fed to the model. The processor determines a statistical distribution of workload characteristics associated with each of the layers of the client I/O stack. I/O performance results are captured for layers of the model based on feeding the workload characteristics of the uppermost layer.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dean Hildebrand, Ramani R. Routray, Vasily Tarasov
  • Patent number: 10255163
    Abstract: Embodiments are disclosed for analyzing data storage devices. The present disclosure employs a “canary” test that selects multiple storage devices and tests the same for a predetermined period of time. By analyzing the statuses of the storage devices monitored and recorded during the applicable tests, the present disclosure can generate an analytical result regarding the characteristics of the storage devices. The analytical result can be presented to an operator in a meaningful way so as to enable him or her to make an informed decision when utilizing a storage device with characteristics similar to the tested storage devices.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: April 9, 2019
    Assignee: Facebook, Inc.
    Inventors: Darryl Edward Gardner, Yashar Bayani, Zhanhai Qin
  • Patent number: 10254395
    Abstract: A device and methods are provided for determining data points with an integrated radar sensor. In one embodiment, a method includes determining position of a device, scanning one or more objects, wherein scanning includes detecting data points by an integrated radar sensor of the device and capturing image data of the one or more objects, and determining data points for one or more objects based on the scanning. The method may also include correlating data points to one or more portions of the image data, assigning correlated data points to one or more portions of the image data, and storing, by the device, image data with data points. The device and methods may advantageously be employed for one or more of mapping, modeling, navigation and object tracking.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: April 9, 2019
    Assignee: Trimble Inc.
    Inventors: Mark Edward Nichols, Gregory Craig Wallace
  • Patent number: 10254826
    Abstract: A system and method of operating an audio visual system generating a virtual immersive experience may include an electronic user device in communication with a tracking device that may track a user's physical movement in a real world space and translate the tracked physical movement into corresponding movement in the virtual world generated by the user device. The system may detect when a user and the user device are approaching a boundary of a tracking area and automatically initiate a transition out of the virtual world and into the real world. A smooth, or graceful, transition between the virtual world and the real world as the user encounters this boundary may avoid disorientation which may occur as a user continues to move in the real world, while motion appears to have stopped upon reaching the tracking boundary.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 9, 2019
    Assignee: GOOGLE LLC
    Inventors: Manuel Christian Clement, Alexander James Faaborg
  • Patent number: 10248385
    Abstract: A mobile application workflow extraction method, system, and computer program product include extracting functional elements from a design file to create a database of design screens, generating a flow graph of the design screens and the functional elements in the design file, creating a transition graph that details how to move from each of the design screens to another, and analyzing, for each of the design screens, a relatability of each design screen to a previously analyzed design screen in the database and generating a tag that represents a workflow.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyungmin Lee, David M. Lubensky, Marco Pistoia, Stephen Wood
  • Patent number: 10248977
    Abstract: A management server and method for performing resource management operations in a distributed computer system takes into account information regarding multi-processor memory architectures of host computers of the distributed computer system, including information regarding Non-Uniform Memory Access (NUMA) architectures of at least some of the host computers, to make a placement recommendation to place a client in one of the host computers.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: April 2, 2019
    Assignee: VMware, Inc.
    Inventors: Aashish Parikh, Puneet Zaroo, Ganesha Shanmuganathan
  • Patent number: 10230325
    Abstract: Electrical component location is provided. Employed location techniques may include providing a cycling signal, having components to be located sense the cycling signal at the same time, report back the sensed signal, and determining relative locations for one or more of the components using the sensed signals reported by the components.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: March 12, 2019
    Assignee: Enphase Energy, Inc.
    Inventors: Patrick L Chapman, Fernando Rodriguez, Philip Rothblum, Anant K Singh
  • Patent number: 10222776
    Abstract: A motor control wizard implements a simple workflow for creating an application-specific program for operation of a motor control system. The wizard prompts for selection of an application area, which sensitizes the system to tune certain motor control parameters in accordance with the demands of the selected application area. The wizard also prompts for selection of a target devices, such as a particular type of motor with a set of basic operating parameters. With the target device and application area known, the wizard runs an automatic adaptation step without requiring additional user-settable parameters. The adaptation step yields an adapted motor control program based characteristics of the motor control system obtained via the adaptation step. The wizard then confirms operation of the motor using the adapted program. Additional features allow the user to fine tune parameters beyond this set of initial configuration parameters.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: March 5, 2019
    Assignee: LINESTREAM TECHNOLOGIES
    Inventors: Adam Reynolds, Chris Knaack, Boris Eligulashvili, David Stopher
  • Patent number: 10222852
    Abstract: In an approach for determining voltage and frequency pairs, the computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design. The computer receives a number n that defines the number of at least one alternate voltage within the voltage range. The computer analyzes the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range. The computer calculates a nominal slack. The computer calculates one or more clock periods based on the calculated nominal slack. The computer provides a report based on the calculated one or more clock periods.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric A. Foreman, Stephen G. Shuma
  • Patent number: 10222850
    Abstract: In an approach for determining voltage and frequency pairs, the computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design. The computer receives a number n that defines the number of at least one alternate voltage within the voltage range. The computer analyzes the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range. The computer calculates a nominal slack. The computer calculates one or more clock periods based on the calculated nominal slack. The computer provides a report based on the calculated one or more clock periods.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric A. Foreman, Stephen G. Shuma
  • Patent number: 10216877
    Abstract: The present embodiments relate to methods for simulating the behavior of an IP core that has an encrypted simulation model. The encrypted simulation model of the IP core may include a plurality of probes, which a debug option may activate selectively, if desired. The encrypted simulation model may collect data during a simulation as selected by the activated probes of the plurality of probes. The encrypted simulation model may perform smart diagnosis of the collected data based on a set of rules and generate feedback messages that may suggest corrective action in the event of a simulation failure.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: February 26, 2019
    Assignee: Altera Corporation
    Inventors: Vishwas Tumkur Vijayendra, Bo Zhou
  • Patent number: 10216252
    Abstract: In an approach for determining voltage and frequency pairs, the computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design. The computer receives a number n that defines the number of at least one alternate voltage within the voltage range. The computer analyzes the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range. The computer calculates a nominal slack. The computer calculates one or more clock periods based on the calculated nominal slack. The computer provides a report based on the calculated one or more clock periods.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric A. Foreman, Stephen G. Shuma
  • Patent number: 10210070
    Abstract: A model checking apparatus able to reduce redundant search in a model checking is provided. The model checking apparatus is configured to: accept verification information representing a state transition model and a verification content; obtain an execution path by causing a transition in the state transition model; analyze, between transitions on the execution path, a dependence relation relating to data set determination processing for determining a data set being a set of representative values of data used in a transition with data use; perform a re-search using a data set in which data already used in a previous search in the transition is excluded from the data set obtained by the data set determination processing, when performing a re-search from a backtrack point based on the dependence relation relating to the data set determination processing; and provide a verification result of the verification content based on the search result.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: February 19, 2019
    Assignee: NEC CORPORATION
    Inventor: Yutaka Yakuwa
  • Patent number: 10211778
    Abstract: A photovoltaic power generation system includes at least one photovoltaic power generation microgrid and a central server configured to communicate with the photovoltaic power generation microgrid via Internet.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: February 19, 2019
    Assignees: HUBEI UNIVERSITY FOR NATIONALITIES, HUBEI YONGHENG SOLAR CO., LTD.
    Inventors: Jianjun Tan, Jinqiao Yi, Xianbo Sun, Yong Huang, Tao Hu, Shangyun Ding
  • Patent number: 10204025
    Abstract: Embodiments are generally directed to a mechanism to provide back-to-back testing of memory controller operation. An embodiment of an apparatus includes a test controller including a specialized self-testing mechanism for memory control testing, the memory control testing including testing with back-to-back transactions; and a memory controller, the memory controller including one or more transaction arbiters, one or more arbiter queues for memory transactions, an auto response mechanism to provide a response to a read transaction, and a switching mechanism to switch the memory control between a functional mode and an auto response mode. The test controller is to generate test transactions and transfer the test transactions to the memory controller. The memory controller is to block the one or more transaction arbiters, place the plurality of test transactions in the one or more arbiter queues, and to unblock the transaction arbiters upon an event.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventor: Lakshminarayana Pappu
  • Patent number: 10198540
    Abstract: The present disclosure relates to a computer-implemented method for electronic design simulation using a profiler. The method may include simulating, using a computing device, an electronic design associated with a programming language. The method may further include recording a first time corresponding to a first user-defined point in the simulation. The method may also include recording a second time corresponding to a second user-defined point in the simulation. The method may further include determining a difference in time between the first and second times and displaying a visualization including at least one of the first time, the second time, a value of a variable at the first time, a value of the variable at a second time, and the difference in time.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 5, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Daniel Asher Cohen
  • Patent number: 10198539
    Abstract: Systems, methods, and products implementing a dynamic register transfer level (DRTL) monitor are disclosed. The DRTL monitor may be rapidly constructed and implemented in one or more emulator devices during the runtime of the emulation of a device under test (DUT). The systems may receive monitor modules and corresponding monitor instances in high level hardware description language and compile the monitor modules and instances to generate a monitor within the one or more emulator devices. The systems may then connect one or more input ports of the monitor to one or more signal sources in the DUT. The systems may further allow removal of the monitor, addition or more monitors, and/or modification of the monitor during the run time of the emulation of the DUT.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: February 5, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tsair-Chin Lin, Jingbo Gao, Alon Kfir, Long Wang, Wei Zeng, Zhao Li
  • Patent number: 10196878
    Abstract: Embodiments of machines, systems, computer-implemented methods, and computer program products certify oil and gas well equipment. Embodiments identify a selected well equipment device, a device test specification, and testing sequences to be performed by a corresponding testing apparatus. Embodiments select a testing sequence responsive to the selected device. Embodiments control the testing apparatus for the selected testing sequence so that the corresponding testing apparatus performs the sequence responsive to the device test specification. Embodiments generate testing data for the selected testing sequence and link the testing data for the selected testing sequence to the device identifier for the device so that a certificate can be generated. Embodiments generate a certificate for the selected device responsive to the testing sequences having been performed upon the selected device and link the certificate for the selected device to the device identifier so that the certificate can be readily recalled.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: February 5, 2019
    Assignee: S.P.M. FLOW CONTROL, INC.
    Inventor: Scott Hunter
  • Patent number: 10182355
    Abstract: A method for testing an air interface device by simulating multi-UE uplink virtual MIMO includes receiving, by a multi-UE simulator, a downlink signal transmission from an air interface device under test. The method further includes decoding, by the multi-UE simulator, the downlink signal transmission to identify simulated UEs with uplink resource block grants. The method further includes assigning, by the multi-UE simulator, uplink data transmissions for the simulated UEs with uplink resource block grants to antennas or cables such that uplink data transmissions for simulated UEs with overlapping uplink resource block grants are assigned to different antennas or cables. The method further includes testing, by the multi-UE simulator, uplink virtual MIMO processing capability of the air interface device under test by generating and transmitting uplink signals from the simulated UEs with the overlapping uplink resource block grants to the air interface device under test using the different antennas or cables.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: January 15, 2019
    Assignee: KEYSIGHT TECHNOLOGIES, INC.
    Inventors: Zhiyong Yan, Roger Alan Slyk
  • Patent number: 10177049
    Abstract: Techniques for measuring and testing a semiconductor wafer during semiconductor device fabrication include designating a test area on the top surface of the wafer and etching a first rectangular trench and a second rectangular trench on the top surface of the wafer in the test area. The trenches are oriented such that a length of the first trench is perpendicular to a length of the second trench, and positioned such that the length of the first trench, if extended, intersects the length of the second trench. A silicon-germanium compound is deposited into the first trench and the second trench, and a test pad is removed from the test area of the wafer. The test pad includes a side surface where both the first trench and the second trench are exposed. The side surface of the test pad is scanned with a transmission electron microscope to take measurements of the silicon-germanium.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: January 8, 2019
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Haifeng Zhou, Jun Tan
  • Patent number: 10176285
    Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and identifying at least one property violation associated with the electronic design. Embodiments may further include generating a sensitivity path from an input to the at least one property violation. Embodiments may also include analyzing the electronic design to identify one or more of a portion of the electronic design that caused the at least one property violation, a portion of the electronic design that did not cause the at least one property violation, and a portion of the electronic design that has not been analyzed. Embodiments may further include applying at least one of a depth analysis and a breadth analysis to the sensitivity path.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: January 8, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Lars Lundgren
  • Patent number: 10176078
    Abstract: The present disclosure relates to a system and method for capturing log messages in a post-processing debugging environment. Embodiments may include receiving a processor model associated with an electronic design and generating, using one or more processors and the processor model, a complete view of the state of the memory. Embodiments may further include writing, using one or more processors and the processor model, a log message whenever a designated message logging function is reached within the complete view of the state of the memory.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: January 8, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vincent Motel, Andrew Robert Wilmot, Tal Tabakman, Yonatan Ashkenazi
  • Patent number: 10169545
    Abstract: Improved computer-implemented tools for use in modeling/simulating spatial charge distributions for electrophysiological systems are provided. The improvements are in three areas: (1) the use of solid angles to calculate quantities of free charge and/or bound charge in calculation cells and/or the movement of quantities of free charge across one or more faces of a calculation cell; (2) the use of flattened calculations cells having only two faces with substantial areas as seen from the free charge and/or the bound charge of the electrophysiological system; and (3) the use of at least two spatial charge distributions, specifically, at least one for bound charge and at least one for free charge, so as to include the effects of relative dielectric constants greater than 1.0 for part or all of an electrophysiological system. The three improvements can be used individually or in combinations.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: January 1, 2019
    Inventor: Maurice M. Klee
  • Patent number: 10164997
    Abstract: A first computer is selected for testing. Information sent from a second computer system to the first computer is intercepted. The information is modified to be noncompliant with a communication protocol, thereby producing noncompliant information. A determination is made whether the first computer device has failed to provide a particular response to receipt of the noncompliant information, and an operation is performed based at least in part on the determination.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: December 25, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Nima Sharifi Mehr, Christopher Dunn, Alexis Floyd, David James Kane-Parry, Volker Helmut Mosthaf, Christopher Gordon Williams
  • Patent number: 10164859
    Abstract: A method for implementing software application monitoring techniques is provided.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: December 25, 2018
    Assignee: salesforce.com, inc.
    Inventors: Christopher Patrick McNair, Tuhin Kanti Sharma