Abstract: Embodiments of the present disclosure provide a method, a computer program product and a computing device for software test by wherein a computing device, wherein at least one virtual hardware component, each virtual hardware component simulating a behavior of a hardware component associated with a to-be-tested software, and testing the to-be-tested software based on the behavior simulated by the at least one virtual hardware component.

Abstract: A device includes: a memory; and a processor coupled to the memory and configured to execute a process of managing data on a first subgraph that is included in a graph including vertices indicating computing resources of a system and edges indicating links between the computing resources and is provided for a first computing resource to which a first job are assigned, or data on a second subgraph that is included in the graph and connected to the first subgraph through a vertex indicating a computing resource to which none of the first job is assigned in the graph and that is provided for a second computing resource to which a second job is assigned, and a process of using the data to determine, based on the first subgraph, whether a third computing resource to which a third job is to be assigned exists.

Abstract: A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source latches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.

Abstract: The described techniques implement electronic designs with thermal analyses of the electronic design and its surrounding medium by performing thermal modeling that determines at least a thermal RC network for an electronic design. These techniques further generate a thermal network for the electronic design and one or more surrounding media of the electronic design and generate or modify the electronic design with an implementation process at least by guiding the implementation process based in part or in whole upon results of performing one or more thermal analysis on the thermal network.

Abstract: Methods and apparatus are provided for provisioning an operating system image from a server (2) to an untrusted user terminal (4) via a data communications network (3). A trusted device (5) such as a pocket USB device has tamper-resistant storage (9) containing bootloader logic, for controlling booting of a user terminal, and security data. On connection of the trusted device (5) to an untrusted user terminal (4), the user terminal is booted via the bootloader logic on the trusted device. Under control of the bootloader logic, a connection is established to the server (2) via the network (3) and the server is authenticated using the security data on the trusted device (5). An operating system boot image is received from the server (2) via this connection. The boot image is used to provision an operating system image from the server (2) to the user terminal (4) for execution of the operating system at the user terminal (4).

Abstract: In the present invention the issue of SSTA in multi-phase sequential circuit with cross-talk in consideration of non-uniform timing constraint and process variations up to the 2nd order is proposed. Use forward breadth first search to calculate the accumulated probabilities at each node for clock phases and edge probability with respect to input and output clock phases, followed by backward depth first traversal to find all critical paths with their probabilities greater than user specified threshold. A method is proposed to pre-characterize the timing library including second order variations. For cross-talk, the poles and residues of admittance matrix and voltage transfer are carried out to 2nd order variations. Effective capacitances and waveforms at interconnect input or driver's immediate output are calculated to 2nd order variations. Delays at victim outputs are then calculated to 2nd order variations and fed back to SSTA, the probability of path occurrence can be calculated accurately.

Abstract: A computer-implemented method for using multi-dimensional geometry in simulations of packet flows through network devices, is provided. The computer-implemented method includes receiving an input object for traffic simulation of network devices, comprising a source and destination host ranges and source and destination port ranges, and protocol, application and vulnerability ranges, targeted for the destination host ranges. The computer-implemented method further includes representing blocked traffic of the simulated traffic by an intersection of at least two n-dimensional cuboids in n-dimensional space. The computer-implemented method further includes subtracting an access control list shape from an input shape to obtain a concave form representing permitted host, port, protocol, application, and vulnerability combinations of ranges. The computer-implemented method further includes decomposing the obtained concave shape into multiple convex shapes that satisfy a set of predetermined input conditions.

Abstract: Various disclosed embodiments include methods and systems for managing lock or latch chains in concurrent execution of database queries. A method includes receiving a plurality of transactions, each transaction associated with one or more queuing requests. The method includes, for each transaction, determining one or more partition sets. Each partition set corresponds to one or more database partitions needed for the transaction. The one or more database partitions are included within a partitioned database. The method includes, for each transaction, determining one or more queues needed for the transaction and storing a bitmap representation of the one or more queues needed for the transaction. The one or more queues needed for the transaction correspond to the one or more database partitions needed for the transaction.

Abstract: A method, system and computer-usable medium are disclosed for using travel-related cognitive graph vectors.

Abstract: A FIR filter includes segment cells, each of which is configurable as an interpolation filter, a decimation filter, a symmetric filter, or an asymmetric filter. Two or more of the segment cells are configurable to be cascaded to form an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, or a complex asymmetric filter. The FIR filter includes registers corresponding to the segment cells for storing coefficient values of the corresponding segment cells. The FIR filter further includes control circuits corresponding to the segment cells for generating control signals.

Abstract: Embodiments relate to pre-silicon device testing using a persistent command table. An aspect includes receiving a value for a persistent command parameter from a user. Another aspect includes determining whether the value of the persistent command parameter is greater than zero. Another aspect includes based on determining whether the value of the persistent command parameter is greater than zero, selecting a number of commands equal to the value of the persistent command parameter from a regular command table of a driver of a device under test. Another aspect includes adding the selected commands to the persistent command table of the driver. Another aspect includes performing testing of the device under test via the driver using only commands that are in the persistent command table of the driver.

Abstract: A method of generating executable code for a target platform in a neural network includes receiving a spiking neural network description. The method also includes receiving platform-specific instructions for one or more target platforms. Further, the method includes, generating executable code for the target platform(s) based on the platform-specific instructions and the network description.

Abstract: A test system including an embodiment having a sensor array adapted to test one or more devices under test in learning modes as well as evaluation modes. An exemplary test system can collect a variety of test data as a part of a machine learning system associated with known-good samples. Data collected by the machine learning system can be used to calculate probabilities that devices under test in an evaluation mode meet a condition of interest based on multiple testing and sensor modalities. Learning phases or modes can be switched on before, during, or after evaluation mode sequencing to improve or adjust machine learning system capabilities to determine probabilities associated with different types of conditions of interest. Multiple permutations of probabilities can collectively be used to determine an overall probability of a condition of interest which has a variety of attributes.

Abstract: In a method for modeling electromagnetic effects in a planar circuit that employs a plurality of through-silicon vias in a domain, a region around each through-silicon via is described in terms of a cylindrical accumulation mode basis function. The cylindrical accumulation mode basis function is incorporated into an equivalent circuit that describes selected electrical characteristics of each through-silicon via. A plurality of localized intervals around each through-silicon via is selected. A multilayer Green's function is approximated for IMNzz? (wherein M and N identify selected layers and wherein zz? designates layer boundaries in a layer through which the through-silicon via passes) in each localized interval without approximating the Green's function over the entire domain. Coefficients IMNzz? are approximated over a predetermined range of frequencies (?). Admittance parameters based on of IMNzz? are calculated over a frequency sweep.

Abstract: An industrial automation component that may receive data associated with at least one other industrial automation component in an industrial automation system. The industrial automation component may contextualize the data with respect to the industrial automation system and recognize a relationship between the industrial automation component and the at least one other industrial automation component based on the contextualized data. The industrial automation component may then store the relationship between the industrial automation component and the at least one other industrial automation component in a memory.

Abstract: In an example embodiment, data communications to a first database intercepted and divided based on tenant. For each tenant of multiple tenants sharing the first database, the commands to update the one or more records in the first database within the data communications corresponding to the tenant are translated into commands to update one or more records in a second database of a different type than the first database, the translated commands corresponding to the tenant are replayed against a copied version of the first database in the second database, and the performance of the second database in handling the translated commands during the replaying is tracked. Serialization and timely execution, among the translated commands corresponding to the tenant, of execution of the translated commands is maintained during the replaying and synchronization of execution of translated commands between multiple tenants is maintained.

Abstract: An automated method is provided for suppressing spurious signals in a direct digital synthesized signal. To determine magnitudes of local oscillator (“LO”) feedthrough and image frequency signal components, a digitally synthesized RF signal is digitally analyzed. To reduce the magnitude of the LO feedthrough signal component, one or more first parameters of at least one digital-to-analog converter is automatically adjusted using a first search pattern. To reduce the magnitude of image frequency signal component, at least one second parameter of the at least one digital-to-analog converter is automatically adjusted and at least one third parameter of a phase compensation network is automatically adjusted using a second search pattern. The automatically adjusting for the LO feedthrough signal component and for the image frequency signal component can be iterated.

Abstract: A computer implemented system and method of identification of useful untested states of an electronic design, comprising, parsing at least one netlist of a representation of the electronic design comprised at least in part of at least one analog portion, determining at least one instrumentation point based on the at least one netlist, generating at least one instrumented netlist based on the at least one instrumentation point and determining an analog verification coverage utilizing the at least one instrumented netlist.

Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.

Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.

Abstract: Enabling communication between real and simulated elements of a process control system. Software instructions stored in a memory device are executed by a processor to represent a virtual switch. The virtual switch connects to a real element of a process control system and to a simulated element of a process control system. The virtual switch receives communication from the real element intended for the simulated element and forwards the communication to the proper simulated element. The virtual switch receives communication from the simulated element intended for the real element and forwards the communication to the proper real element.

Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.

Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.

Abstract: A device connectable to a control device for simulating an effect of at least one electrical or electronic load being connected to at least one terminal of the control device includes: a processing unit configured to at least one of compute and make available a control variable corresponding to the effect of the at least one electrical or electronic load that is to be simulated, and a power supply device: The power supply device includes at least one auxiliary voltage source configured to form at least one of a current source and a current sink and configured to receive the control variable from the processing unit. The at least one auxiliary source is configured to draw a current from the control device or impress a current on the control device based on the received control variable.

Abstract: Methods and apparatuses for repairing a broken object. A processor retrieves information describing the size and shape of a broken object. A processor retrieves information describing the size and shape of an intact object, wherein the intact object includes a part missing from the broken object. A processor generates a first three-dimensional model of the broken object based, at least in part, on the information describing the size and shape of the broken object. A processor generates a second three-dimensional model of the intact object based, at least in part, on the information describing the size and shape of the intact object. A processor generates a third three-dimensional model based, at least in part, on a difference between the first and second three-dimensional model. A processor sends one or more instructions to a three-dimensional printer to create an object based, at least in part, on the third three-dimensional model.

Abstract: A computer-implemented method for using multi-dimensional geometry in simulations of packet flows through network devices, is provided. The computer-implemented method includes receiving an input object for traffic simulation of network devices, comprising a source and destination host ranges and source and destination port ranges, and protocol, application and vulnerability ranges, targeted for the destination host ranges. The computer-implemented method further includes representing blocked traffic of the simulated traffic by an intersection of at least two n-dimensional cuboids in n-dimensional space. The computer-implemented method further includes subtracting an access control list shape from an input shape to obtain a concave form representing permitted host, port, protocol, application, and vulnerability combinations of ranges. The computer-implemented method further includes decomposing the obtained concave shape into multiple convex shapes that satisfy a set of predetermined input conditions.

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

Abstract: An emulation environment includes a host system and an emulator. The host system configures the emulator to emulate a design under test (DUT) and the emulator emulates the DUT accordingly. During emulation, the emulator traces limited signals of the DUT and stores values of the traced signals. When values of certain signals of the DUT are needed for analysis or verification of the DUT but the signals were not traced by the emulator, the host system simulates one or more sections of the DUT to obtain values of the signals. Signals traced by the emulator are used as inputs to simulate the one or more sections.

Abstract: A method and system for automatically integrating component logs is provided. The method includes retrieving from a software application, high level log identification values representing transactions executed by the software application. Compiled machine language identification values representing compiled code associated with the software application and the hardware device are retrieved from an agent and a high level log identification value of the high level log identification values is identified. The high level log identification value is associated with an instruction set processed by a central processing unit (CPU). An instruction set identification value is correlated with the compiled machine language identification values. The compiled machine language identification values are converted into decompiled machine language identification values and the decompiled machine language identification values are correlated with log levels associated with the high level log identification values.

Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.

Abstract: The invention provides a computer simulation system for simulating a data centre. The simulation system uses a logical representation of the data centre to perform the simulation. This logical representation includes a plurality of nodes representing devices in the data center. Each node has an input for applied load and outputs for electrical power drawn and losses in the form of heat output. Each node also has a function for calculating the outputs from the inputs. A first set of connections between the nodes represent electrical power drawn by one device in the data center from another device in the data center. A second set of connections between the nodes represent a thermal load applied by one device in the data center to another device in the data center. The simulator can be run for a series of different operating conditions to map data center efficiency, for example, or to assess the impact of different IT devices on the data center.

Abstract: Method and systems for a storage system are provided. Simulated cache blocks of a cache system are tracked using cache metadata while performing a workload having a plurality of storage operations. The cache metadata is segmented, each segment corresponding to a cache size. Predictive statistics are determined for each cache size using a corresponding segment of the cache metadata. The predictive statistics are used to determine an amount of data that is written for each cache size within certain duration. The process then determines if each cache size provides an endurance level after executing a certain number of write operations, where the endurance level indicates a desired life-cycle for each cache size.

Abstract: Implementing circuitry from an application can include determining a data flow of an application including a producer function, a loop construct, and a consumer function and creating a new function including contents of a body of the loop construct. A circuit design can be generated from the application including a producer function circuit block, a new function circuit block, and a consumer function circuit block. Control circuitry for each circuit block can be included within the circuit design. The control circuitry of the new function circuit block can initiate operation of the new function circuit block according to a loop induction variable of the loop construct.

Abstract: Techniques for generating a hollow model from a medical image are disclosed herein. In an example, a hollow model may be created within a medical imaging visualization application through the generation of a mask of an interior space of a segmented anatomical structure, the extrusion of a shell mask from the mask of the interior space, and the generation of a visualization of the shell mask within the medical imaging visualization application. For example, the mask may be provided as a layer in the medical imaging visualization application, allowing a user to visualize the produced shell mask of the hollow model from the perspective of the medical imaging. In further examples, the hollow model generation techniques may be used with techniques for shell region modifications, variable shell thickness, multiple shell layer, and trimming of shell endpoints.

Abstract: A method for a system that runs a platform simulation and a network simulation of a radio network comprises probing the network simulation to determine effects produced between transmitter-receiver pairs represented within the network simulation; computing communication effects in response to the probing and saving the communication effects for later use; and when a communication event involving a transmitter-receiver pair occurs in the platform simulation, using the saved communication effects to simulate the communication effects for that event.

Abstract: Systems and methods for a sequential decompressor which builds equations predictably provide a first-in, first out (“FIFO”) shift register which is fed by a first XOR decompressor and provides outputs to a second XOR decompressor.

Abstract: Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.

Abstract: Systems and methods efficiently bring additional variables into a Pseudo-Random Pattern Generator (“PRPG”) in the early cycles of an automatic test pattern generation (“ATPG”) process without utilizing any additional hardware or control pins. Overscanning (e.g., scanning longer than the length of the longest channel) for some additional cycles brings in enough variables into the PRPG. Data corresponding to earlier cycles of the ATPG process is removed.

Abstract: A video acquisition method and device. The method includes setting a video acquisition class in a programming language framework layer. With the video acquisition class inherits a class in a video acquisition underlying library and registers a callback function for the video acquisition underlying library. The video acquisition class sends a video acquisition command to the video acquisition underlying library and the video acquisition underlying library acquires video data according to the video acquisition command. The callback function is applied to acquire the video data from the video acquisition underlying library and the video data is sent to a coder for video data coding.

Abstract: Methods, systems, and computer program products are hereby claimed for including and distinguishing independent variables that denote lifespan in multivariable binary regression analyses of mortality and survivorship. These methods, systems, and computer program products are demonstrated here by including and distinguishing lifespan in multivariable binary regression analyses of humans' and medflies' mortality and survivorship, revealing advantages for the description, specification, measurement, analysis, explanation, and prediction of mortality and survivorship.

Abstract: In accordance with the teachings of the present disclosure, a method of assessment of cloud hosting suitability for multiple applications is disclosed. The method may include creating a second synthetic application definition based on a first synthetic application definition, wherein creating the second application definition comprises defining, in the second synthetic application definition, a second plurality of resource consumptions, wherein the second plurality of resource consumptions are equivalent to consumptions by the candidate application at a second level of user demand. The method may also include consuming, based on the second synthetic application definition, a plurality of quantities of resources of the computing system and evaluating the computing system. The present disclosure additionally includes associated systems and apparatuses.

Abstract: A method and apparatus for service quality monitoring in a wireless network is provided. The network has both wired and wireless connections, and has at least one access point capable of providing wireless connectivity to client devices. Wireless connectivity is provided to client devices from the access point with at least one client-serving radio transceiver. Radio test signals are generated for network testing from a testing transceiver at the access point.

Abstract: Methods, computer-readable media, software, and apparatuses provide a system for implementing a tool that allows users to test a webpage. The system may include a computing device configured to use the tool to parse a request that is transmitted in response to, for example, a selection to load the webpage. The tool may also generate a user interface comprising variables of the request. The variables may be displayed so that they may be selected by a user. For each selected variable, the computing device may generate a column within a table. The table may include the values for each selected variable. The computing device may also generate a second table with corresponding values for corresponding variables. Further, the computing device may compare corresponding values to execute regression testing. Also, the computing device may allow a user to select criteria for certain variables to generate rules and apply rules against requests.

Abstract: Responsive to a request to retrieve or store a file, a transformation pipeline may be created to efficiently transform file data one unit at a time in memory. The transformation pipeline includes a sequence of transformation streams, each containing a write method, a read method, and a transformation to be applied. The write method moves a unit of data, for instance, from a memory buffer into an associated stream. The read method reads the unit of data from the stream, calls an associated transformation, and passes the unit of data thus transformed to the next stream or a destination. This process is repeated until all desired and/or required transformations such as compression, encryption, tamper protection, conversion, etc. are applied to the unit of data.

Abstract: In accordance with the teachings of the present disclosure, a method of assessment of service level agreement compliance is disclosed. The method may include defining, in a synthetic application definition, a plurality of resource consumptions, wherein the plurality of resource consumptions are equivalent to consumptions by a candidate application, and distributing the synthetic application definition to a synthetic application in a node of a computing system. The method may further include consuming, with the synthetic application and based on the synthetic application definition, a plurality of quantities of resources of a plurality of nodes of the computing system. The method may additionally include recording a performance of the synthetic application, and comparing the recorded performance to a requirement of a service level agreement (SLA). The present disclosure additionally includes associated systems and apparatuses.

Abstract: Generating a set of attempted external contacts associated with a malware sample is disclosed. A malware sample is executed, in an accelerated computing environment. In the accelerated computing environment, a guest time is advanced more quickly than a time by which a host time is advanced. A set of one or more attempted external contacts generated by the executing malware sample is recorded. The set of attempted external contacts is provided as output.

Abstract: In accordance with the teachings of the present disclosure, a method of application-specific assessment of cloud hosting suitability is disclosed. The method includes distributing synthetic applications to nodes of the computer system. The method further includes consuming quantities of resources of nodes based upon a synthetic application definition. The method additionally includes measuring a performance characteristic of the synthetic applications, and evaluating performance of the synthetic applications. The present disclosure also includes associated systems and apparatuses.

Abstract: Systems and techniques for identifying potential problems associated with deploying a software package in a computing system are described. The software package may include multiple components that are installed in various locations in the computing system. Multiple agents that perform mock activities emulating the activities of the multiple components may be deployed in the computing system. Activity data may be gathered when the multiple agents are performing the mock activities and used to identify potential problems.

Abstract: A peripheral integrated circuit (IC) device for providing support to a data processing IC device. The peripheral IC device comprises a fault detection component arranged to detect an occurrence of fault conditions within the data processing IC device. The peripheral IC device further comprises a safe state control component. Upon detection of a fault condition occurring within the data processing IC device by the fault detection component, the safe state control component is arranged to cause at least one I/O cell of the data processing IC device to be configured into at least one scan-chain, and cause at least one predefined control signal to be scanned into the at least one scan-chain to configure the at least one I/O cell into a state corresponding to the predefined control signal.

Abstract: Identifying state inconsistency in edge-based software defined networks is disclosed. A verification server may receive controller network configuration data from a controller of an edge-based software defined network (SDN) and end-host network configuration data from at least one end-host of the SDN. The verification server may parse the controller network configuration data into a network state representation and the end-host network configuration data into the network state representation. The network state representation of the controller network configuration data and the end-host network configuration data may be compared to identify state inconsistency in the SDN. Responsive to identifying the state inconsistency, an alert and/or a report may be generated and transmitted to an administrator user interface.