Abstract: A cellular communication device has one or more access modes which allow reading and writing of data, for example to change its settings, for example passwords and even the entire operating system and also permitting access to personal information such as the user's telephone book. To prevent cloning and like illegal access activity, the device is configured by restricting access to such data access modes using a device unique security setting. The setting may be a password, preferably a one-time password, or it may be a unique or dynamic or one time configuration of the codes for the read and write instructions of the data mode. There is also disclosed a server, which manages the security settings such that data mode operates during an active connection between the device and the server, and a secure communication protocol for communicating between the server and the cellular device.

Abstract: An integrated modeling and analysis system (IMAS) receives documents containing information relating to an overall operations system from a number of integrated product teams (IPTs). The IMAS creates a model architecture of the overall system the information received from the participating IPTs. The IMAS automatically imports the information without any interaction from support personnel. A discrete event modeling (DES) application in communication with the IMAS creates a DES model based on the model architecture in the IMAS. The DES application runs a simulation on the model generating statistical data relating to the overall system for analysis. The statistical data generates output reports in a format compatible with the analysis tools of the user. The IMAS includes a customizable user interface which allows a stakeholder to link and control the modeling information received from all other participating IPTs. Prior simulations and results can be archived for later reference.

Abstract: Embodiments relate to pre-silicon device testing using a persistent command table. An aspect includes receiving a value for a persistent command parameter from a user. Another aspect includes determining whether the value of the persistent command parameter is greater than zero. Another aspect includes based on determining whether the value of the persistent command parameter is greater than zero, selecting a number of commands equal to the value of the persistent command parameter from a regular command table of a driver of a device under test. Another aspect includes adding the selected commands to the persistent command table of the driver. Another aspect includes performing testing of the device under test via the driver using only commands that are in the persistent command table of the driver.

Abstract: A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.

Abstract: Systems and methods disclosed herein provide for generating extra variables for an ATPG system utilizing compressed test patterns in the event an ATPG process is presented with faults requiring a higher number of care-bits than can be supported efficiently by the current hardware. The systems and methods provide for a multi-stage decompressor network system with an embedded serializer-deserializer. The systems and methods use a XOR decompressor in a first stage and a serializer-deserializer in conjunction with a second XOR decompressor in a second stage.

Abstract: Provided is a virtual-machine managing device including: a model acquiring unit that acquires, for each server device, a performance model indicative of plural correspondent relationships between a workload amount and performance information on a workload; a performance-information acquiring unit that acquires the performance information on a virtual machine to be moved running on a current server device; a conversion unit that converts the performance information on the virtual machine to be moved into a combination of the workload amount and the workload characteristic value concerning the virtual machine to be moved, by using the performance model of the current server device; and an estimating unit that estimates performance information on the virtual machine to be moved on a destination server device serving as a candidate for a destination of movement of the virtual machine to be moved, by applying the combination converted by the conversion unit to the performance model of the destination server device

Abstract: A computer-readable memory device may include instructions to store data describing a state machine model including source states and destination states. The device may also include instructions to store, for each of the source states, a condition field identifying a condition upon which, when satisfied, the state machine model transitions from the source state to one of the destination states. The device may also include instructions to store, for each of source states, a destination field identifying the one of the destination states. Each of at least two of the source states may identify an identical destination state in the corresponding destination field. Each of at least two of the source states may identify an identical condition in the corresponding condition field.

Abstract: Various embodiments scalable statistical library characterization for electronic designs by identifying an electronic design, performing circuit simulations on strongly connected components on a component-by-component basis, performing the logic cone analysis on the entire electronic design, and performing combinations of influences on the electronic design caused by variations of parameters. Some embodiments perform simulations on one or more stronger parameters or the strongest parameter of a circuit component and use the simulation results to calibrate the predicted behaviors of one or more remaining circuit components of the electronic design. Various statistical or mathematical techniques may be used for performing the combinations of influences on the electronic design caused by variations of parameters. The techniques described are scalable with the increase in complexities and sizes of electronic designs while reducing or minimizing the impact on sensitivity accuracy.

Abstract: The invention relates to a method and system for discovering and documenting the business knowledge contained in the functions of each program of existing software applications as expressed in the source code of each program using a novel method of dynamic business rule extraction that overcomes the inherent limitations of previous methods. The novelty of the method results from the deterministic relationship between program functions and the program code executed to perform each function as revealed by empirical analysis of the actual code execution, hence “dynamic” business rule extraction. This compares to previous methods which utilized a manual process, a fully automated process, and/or a process of analysis against the non-executing source code of each programs in which the analyst must infer the execution path, hence “static” business rule extraction. Furthermore, dynamic business rule extraction can deliver results without errors or omissions and document forensically that it has done so.

Abstract: A system and method are disclosed for rationalizing configurations associated with one or more products. The system includes a database associated with one or more customers. The system further includes an order analysis system coupled with the database. The order analysis system is capable of rationalizing the differences between configurations of various combinations of options that are stored in the database.

Abstract: A computer implemented method and system for exclusion of entities from a metric driven verification analysis score. The method includes using a processor, and performing the following steps: parsing a source code simulating a device under test and modeling the source code into a model that includes entities of one or a plurality of metric driven entity types; identifying in the source code entities of the same metric driven entity type of said one or a plurality of metric driven entity types that are logically linked and saving information on the identified entities that are logically linked; receiving from a user a selection of an entity to be excluded from the metric driven verification analysis score; and excluding all instances of the selected entity and all instances of the identified entities that are logically linked to the selected entity from a calculation of the metric driven verification score.

Abstract: One aspect is a method that includes analyzing, by a processor of an analysis system, an instruction set architecture of a targeted processor to generate an instruction set profile for each instruction of the instruction set architecture. A combination of instruction sequences for the targeted processor is determined from the instruction set profile that corresponds to a desired stressmark type. The desired stressmark type defines a metric representative of functionality of interest of the targeted processor. Performance of the targeted processor is monitored with respect to the desired stressmark type while executing each of the instruction sequences. One of the instruction sequences is identified as most closely aligning with the desired stressmark type based on performance results of execution of the instruction sequences with respect to the desired stressmark type.

Abstract: One aspect is a method that includes analyzing, by a processor of an analysis system, an instruction set architecture of a targeted processor to generate an instruction set profile for each instruction of the instruction set architecture. A combination of instruction sequences for the targeted processor is determined from the instruction set profile that corresponds to a desired stressmark type. The desired stressmark type defines a metric representative of functionality of interest of the targeted processor. Performance of the targeted processor is monitored with respect to the desired stressmark type while executing each of the instruction sequences. One of the instruction sequences is identified as most closely aligning with the desired stressmark type based on performance results of execution of the instruction sequences with respect to the desired stressmark type.

Abstract: A method, system, and computer program product include electronic design automation (EDA) tools used with standard CMOS processes to design and produce radiation-hardened (rad-hard) integrated circuits (ICs) having a predictable level of radiation hardness while maintaining a desired level of performance and tracking circuit area. The tools include rad-hard design rule checking (DRC) decks, rad-hard SPICE models, and rad-hard cell libraries. A rad-hard parasitic components extraction process makes use of rad-hard DRC rules to locate occurrences of parasitic devices, calculate their effects on circuit performance, and return this information to layout and circuit simulation tools. Changes to the layout are suggested and implemented with varying degrees of automation. Some of these tools can be provided as components of a rad-hard process design kit (PDK). They can be used in conjunction with commercial EDA tools to facilitate the incorporation of rad-hard features into new or existing IC designs.

Abstract: An LCD panel includes multiple data lines, multiple scanning lines, multiple pixels, and multiple control transistors. Each pixel connected with a corresponding one of the data lines and one of the scanning lines. Gate electrodes of the control transistors are connected with a same scanning line. A source electrode of each control transistor is connected with a corresponding one of the data lines. Drain electrodes of the control transistors are connected with each other. A black picture insertion method for the LCD panel displayed in a 3D mode is also disclosed. Accordingly, a refresh frequency of the driving circuit is one half of the prior art. The power consumption and cost are reduced. Besides, a black picture is inserted into one frame during a blank time domain of the one frame such that the brightness is increased and the charge time of the liquid crystal capacitor is increased.

Abstract: In an example embodiment, updated repository instances are typically developed on a development system, transferred to a testing system, and after testing, transferred to a production system. Such an updated instance may comprise content, sources and a data dictionary. As an updated instance is moved from one system to another, the change is applied to an original instance. A shadow copy of content is kept for the original instance. In another example embodiment, a shadow copy of content is created as part of the change process. The sources and data dictionary may have their own versioning mechanism. To undo the applied change, the sources and data dictionary are rolled back to their pre-change state. The content is retrieved from the shadow copy and restored to the original instance. Finally, stranded data is restored according to appropriate policies.

Abstract: Data is identified that represents a path of a transaction that includes a plurality of transaction fragments associated with a plurality of software components. The plurality of software components includes a first software component to communicate in the transaction with a second software component over an interface. A transaction boundary is determined between the first and second software components based at least in part on the data. A virtual model is generated to simulate at least a particular one of the plurality of software components based on the identified transaction boundary.

Abstract: The vehicle mobile microgrid is a vehicle on-board electrical grid dedicated to supplying all supplemental electrical needs for the vehicle utilizing recovered energy from internal combustion engine heat, vehicle motion and auxiliary electrical power generator, chemical and mechanical storage systems and electrical power from incident light energy. Unlike electrical grids that serve wide population areas, the vehicle on-board electrical grid is not meant to serve electrical demand beyond that utilized by the vehicle. This on-board electrical grid is therefore very small by comparison, and the term microgrid is meant to convey this comparative size. The microgrid utilizes a common-mode bidirectional microgrid to efficiently capture, store and distribute electrical power depending on the vehicle's demand for electrical power.

Abstract: Systems and methods receive a model of a physical system. The model includes a virtual mechanical component that represents a physical mechanical component of the physical system, and a virtual transducer that represents a physical transducer of the physical system. The systems and methods include generating a wiring diagram that includes information for connecting the physical mechanical component or the physical transducer to a data processing device or an embedded system. The model may be executed by the data processing device or the embedded system to interact with the physical mechanical component or the physical transducer as part of Hardware-in-the Loop (HIL), Processor-in-the-Loop (PIL), or other simulation or testing.

Abstract: A system and method are provided for maintaining alignment of timing signals of a source synchronous interface between driver and receiver portions of an electronic system in a behavioral model based simulation environment. The system comprises a memory unit, an analysis controller unit coupled to the memory unit, and a timing alignment unit coupled to the analysis controller unit. The timing alignment unit is executable responsive to the analysis controller unit to generate behavioral models for mutually assigned first and second nets which transmit respective timing signals between the driver and receiver portions, and actuates transient simulation on the behavioral models to simulate transmission of the timing signals through the first and second nets. A timing skew between respective transmissions of the timing signals through the first and second nets is measured responsive to the simulated transmission for compensation during a general simulation of the source synchronous interface.

Abstract: Systems and methods for creating and presenting sensory stimulating content in a cyber reality environment. One aspect of the disclosure allows a composer to associate audio content with one or more virtual triggers, and to define behavior characteristics which control the functioning of each virtual trigger. Another aspect of the disclosure provides a variety of user interfaces through which a performer can cause content to be presented to an audience.

Abstract: A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. Additionally, post processing may be performed on GDS layers to provide a realistic fill of the empty space so as to resemble structural elements found in a functional circuit.

Abstract: Technologies for software testing include a computing device having persistent memory that includes a platform simulator and an application or other code module to be tested. The computing device generates a checkpoint for the application at a test location using the platform simulator. The computing device executes the application from the test location to an end location and traces all writes to persistent memory using the platform simulator. The computing device generates permutations of persistent memory writes that are allowed by the hardware specification of the computing device simulated by the platform simulator. The computing device replays each permutation from the checkpoint, simulates a power failure, and then invokes a user-defined test function using the platform simulator. The computing device may test different permutations of memory writes until the application's use of persistent memory is validated. Other embodiments are described and claimed.

Abstract: Embodiments disclosed herein provide a system, method, and computer readable storage medium storing computer instructions for implementing a Socialware architecture encompassing a suite of applications for continuously and adaptively monitoring and filtering traffic to and from social networking sites, particularly useful in an enterprise computing environment. In some embodiments, an appliance may be coupled to a proxy server for providing a plurality of Socialware services, including analyzing, logging, and reporting on traffic to and from social networking sites. Some embodiments may allow a user to report, identify, and prevent malicious and potentially malicious content and/or activity by another user. Some embodiments may encrypt outgoing traffic to and decrypt incoming traffic from social networking sites. Some embodiments may provide an enterprise user to define and restrict certain social networking activities outside of the enterprise computing environment.

Abstract: Data are refreshed in a nonvolatile solid-state device to significantly reduce the likelihood of data retention errors. Test data are written in a region of the nonvolatile solid-state device when user data are stored in the nonvolatile solid-state device, and are subsequently read to detect the possibility of data retention errors occurring when the associated user data are read. The test data may be a portion of the user data or a predetermined test pattern. To increase sensitivity to incipient charge leakage that may compromise the user data, the test data may be written using a modified write process and/or read with a modified read operation. The nonvolatile solid-state device may be employed as part of a solid-state drive or as the flash-memory portion of a hybrid hard disk drive.

Abstract: Methods and apparatus to automatically configure monitoring of a virtual machine are disclosed. An example method includes identifying a virtual machine in an application definition, automatically installing an agent on the virtual machine when the virtual machine is identified as having a designated configuration, automatically identifying, via the agent, a resource associated with the virtual machine and, based on the resource, applying a monitoring policy to the virtual machine to be executed by the agent.

Abstract: Converting data for an application ported from an operating system (OS) platform of a first computer to an OS platform of a second computer. Configuration information associated with ported application including the first computer's OS platform is stored on the second computer. The ported application executing on the second computer receives first data encoded in a first code set. The OS of the second computer receives a request to convert the first data to a second data encoded in a second code set, locates a first-code-set-to-second-code-set mapping based on at least maintained code set mappings of the OS of the first computer, and converts the first data to the second data using the located first-code-set-to-second-code-set mapping. The second data is compatible for processing on the second computer and output from converting the data on the second computer is equivalent to an output from converting the data on the first computer.

Abstract: A system. The system includes a computing device having a processor, and a causality checker module communicably connected to the processor. The causality checker module is configured to utilize a rational function approximation to a frequency response to determine if a transfer function of a linear time invariant system is causal.

Abstract: This application relates to systems, methods, and apparatus for testing operability of a mobile device with a reader device. In some embodiments, a testing system is set forth for automatically placing the mobile device proximate to the reader device in order to initiate a wireless transaction between the mobile device and the reader device. Depending on whether the mobile device is determined to be operable with the reader device, the testing system can automatically place the mobile device proximate to another reader device for testing. In this way, reductions in testing time can be manifested as a result of automating the testing process.

Abstract: A system for extracting a 3D shape of a hot metal surface, includes: a light source unit emitting four types of light, i.e. two types of light each having different wave bandwidths that are different from a wave bandwidth emitted by a hot target object, and two other types of light having the same wave bandwidths as the above-described two types of light, respectively, so that the types of light having the same bandwidths are polarized in different directions so as not to interfere with one another; an image acquisition unit simultaneously emitting the four types of light, polarized from the light source, onto the target object so as to acquire 2D images of the target object; and an image processing unit using a photometric stereo technique so as to combine the 2D images acquired by the image acquisition unit and extract a 3D shape of the surface of the target object.

Abstract: A computer-implemented modeling-and-simulation coordination module is provided for coordinating components by exchanging and sequencing instructions. The module includes a scenario file generator, a plug-in loader, an interface loader, a module classifier, an event detector, a response initiator, a simulation processor, a model request processor, an instance receiver, and an output provider. The scenario file generator creates a blank scenario file. The plug-in loader loads plug-in modules. The interface loader loads GUIs into corresponding containers. The classifier sets a classification to a highest rank plug-in module. The event detector monitors updating events. The response initiator prompts the operator to select an experimental plug-in module. The simulation processor executes a simulation in response to the operator loading a scenario, setting experimental parameters, and selecting the simulator plug-in.

Abstract: A simulation apparatus includes a discrete events simulation section to perform a discrete type simulation of components of a configured model as defined based on attribute information that is information on parts of the components of the defined configured model and connection information showing a connectional relationship among the components of the defined configured model; and a soft error rate computation processing section to compute a soft error rate of the defined configured model based on the simulation result of the discrete events simulation section and data on soft error rates in the attribute information.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a plurality of solid-state non-volatile memory cells. A controller communicates a first command having address information and a first operation code. The first operation code identifies a first action to be taken by the memory module in relation to the address information. The controller subsequently communicates a second command having a second operation code without corresponding address information. The memory module takes a second action identified by the second command using the address information from the first command.

Abstract: A device simulation system performs a set of tests by applying, for each test in the set, a corresponding test stimulus to a simulation of the electronic device. In response to each test stimulus, the simulation generates corresponding output information which the device simulation system compares to a specified expected outcome to identify a test result for that test stimulus. In addition, for each test stimulus, the device simulation system generates test coverage information indicating the particular configuration of the simulated electronic device that resulted from the stimulus. The device simulation system correlates the coverage information with the test results to identify correlation rules that indicate potential relationships between test results and configurations of the simulated device.

Abstract: Systems and methods are provided to generate and exchange pricing information by a pricing engine. According to one embodiment, a pricing graph having a plurality of inter-dependent nodes is constructed. The pricing graph includes at least one input pricing information node and output pricing information node. In addition, at least one node provides information that effects information received by that node. A frame is established with at least one input pricing information slot and output pricing information slot. The pricing graph is then executed via a pricing engine in substantially real time. As a result, a value in the input pricing information slot is provided to the input pricing information node and a value for the output pricing information slot is received from the output pricing information node.

Abstract: Liveness verification of a logic design is performed using various shadow abstraction refinement techniques. An initial subset of state elements are included in the shadow abstraction, and verification is performed (liveness-to-safety conversion) using this initial subset. If a liveness counterexample is detected, the shadow abstraction is refined by designating a second subset of the state elements different from the initial subset for inclusion in a refined abstraction. The initial subset can be designated by choosing all registers in a combinational fan-in of a liveness property of the design. High-performance algorithms for abstract liveness-to-safety conversion can be based upon simulation and counterexample refinement, bounded model checking and counterexample refinement, bounded model checking and proof-based refinement, proofs obtained during bounded model checking of a precise liveness checking problem, a hybrid of counterexample-based refinement and proof analysis, and proofs obtained.

Abstract: The disclosed embodiments relate to a system for analyzing the performance virtual machines. During operation, the system obtains hypervisor data for a set of virtual machines, wherein the hypervisor data was received from one or more hypervisors while the set of virtual machines was running on the hypervisors. The system also obtains operating system data for the set of virtual machines, wherein the operating system data was received from a set of operating systems while the set of operating systems was running on the set of virtual machines. Next, the system correlates hypervisor data for a virtual machine with corresponding operating system data for the virtual machine. Finally, the system presents the correlated hypervisor data and operating system data for the virtual machine to a user.

Abstract: Any primitive cells or blocks can be represented physically by a Barycenter compact model, and any black box model can also be physically represented by a Barycenter compact model physically. A hierarchical boundary condition between blocks is formulated by the Barycenter model or Barycenter compact model. Hierarchical boundary condition problems between blocks can be limited within two levels only if using the Barycenter model or Barycenter compact model.

Abstract: Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device.

Abstract: Liveness verification of a logic design is performed using various shadow abstraction refinement techniques. An initial subset of state elements are included in the shadow abstraction, and verification is performed (liveness-to-safety conversion) using this initial subset. If a liveness counterexample is detected, the shadow abstraction is refined by designating a second subset of the state elements different from the initial subset for inclusion in a refined abstraction. The initial subset can be designated by choosing all registers in a combinational fan-in of a liveness property of the design. High-performance algorithms for abstract liveness-to-safety conversion can be based upon simulation and counterexample refinement, bounded model checking and counterexample refinement, bounded model checking and proof-based refinement, proofs obtained during bounded model checking of a precise liveness checking problem, a hybrid of counterexample-based refinement and proof analysis, and proofs obtained.

Abstract: Methods and systems for managing resources in a networked storage environment are provided. One method includes using a queuing model for a resource that processes a plurality of requests at a networked storage environment for predicting a relationship between latency and utilization of the resource. The queueing model uses inter-arrival time and service time to determine latency, where inter-arrival time is a duration that tracks when requests arrive at the resource and the service time tracks a duration for servicing the requests by the resource. The method further includes identifying optimum utilization of the resource using the predicted relationship between latency and utilization, where the optimum utilization is an indicator of resource utilization beyond which throughput gains for a workload is smaller than increase in latency; and determining available performance capacity for the resource using the optimum utilization and actual utilization of the resource.

Abstract: An optimized version of a binary and a non-optimized debuggable version of a binary for each compiling unit in the source code program are generated. The optimized versions of binaries of all compiling units are loaded into memory for debugging, which is monitored. In response to determining that a first compiling unit in the source code program is to be debugged, the non-optimized debuggable version of the binary is loaded into a memory location that was previously used by the optimized version of the binary. In response to determining that debugging of a second compiling unit in the source code program is to be cancelled, the optimized version of the binary of the second compiling unit is loaded into a memory location that was previously used by the non-optimized debuggable version of the binary.

Abstract: According to embodiments of the present invention, a multi-lines cable simulator is provided which is able to simulate also crosstalk between lines. The multi-lines cable simulator is comprised in a modular unit configured to simulate increased number of lines by means adding further modular units. According to further embodiments, the modular unit is configured to also simulate increased line length by means of adding further modular units.

Abstract: In an embodiment, a method for interactively changing allocation of an application including multiple algorithm components executing on a heterogeneous target environment (HTE) provides a user interface in a co-simulation design environment. The user interface is associated with the application having multiple algorithm components executing on the HTE that includes multiple computing devices with different processing capabilities. The method also sets attributes of the allocation scheme of the application using the user interface. The setting occurs when the application is executing. The method further receives data associated with the executing of the application in the co-simulation design environment when the application is executing subsequent to the setting of the attributes of the allocation scheme.

Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The method includes performing a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget. The method also includes computing power assertions, performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, and reducing a weighting of the power assertions relative to the timing constraints based on the degradation. The executing the performing the re-synthesis, the comparing, and the reducing are done iteratively until the degradation is below a threshold value.

Abstract: A calculated factoring ratio is determined as a weighted ratio of current nominal data to physical data. A maximal nominal estimated space in the computing storage environment is calculated. A remaining space, defined as the maximal nominal estimated space minus a current nominal space in the computing storage environment, is calculated. Data replication operations are accepted and stored in the computing storage environment if the remaining space is below a predetermined threshold of space for backup operations.

Abstract: Provided are scatterometry model optimizations for evaluating a diffracting structure. In one embodiment, a method includes identifying one or more parameters to test for inclusion in the model. The method includes computing a difference between modeled data generated with the one or more parameters and measured data. The one or more parameters are included in the model in response to a reduction in the difference between the modeled data and the measured data compared to previous modeled, and passing a statistical hypothesis test. In one embodiment, the one or more parameters pass the statistical hypothesis test in response to the probability of obtaining the reduction in the difference is less than a significance level. In one embodiment, the significance level is a function of an alpha wealth value. In one embodiment, the method includes ordering the plurality of parameters for testing according to one or more criteria.

Abstract: The invention provides a computer system and a method for testing hardware device based on virtual machine. The computer system comprises a virtual machine device installed with a guest operating system. The guest operating system comprises a guest driver and a hypervisor having an expansion test module. When the computer system is intended for testing the hardware device, the guest driver will issue a sequence of test instructions to a real hardware or a virtual hardware via the expansion test module. The real hardware or the virtual hardware processes the test instructions so as to generate at least one response signal and transmit the response signal to the guest driver via the expansion test module. The guest driver is capable of detecting the response signal in order to verify the correctness of the real hardware or the virtual hardware processing the test instructions.

Abstract: Converting data for an application ported from an operating system (OS) platform of a first computer to an OS platform of a second computer. Configuration information associated with ported application including the first computer's OS platform is stored on the second computer. The ported application executing on the second computer receives first data encoded in a first code set. The OS of the second computer receives a request to convert the first data to a second data encoded in a second code set, locates a first-code-set-to-second-code-set mapping based on at least maintained code set mappings of the OS of the first computer, and converts the first data to the second data using the located first-code-set-to-second-code-set mapping. The second data is compatible for processing on the second computer and output from converting the data on the second computer is equivalent to an output from converting the data on the first computer.

Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. Each violation monitor comprises a violation information detector for detecting one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determining information representing the respective violation; a violation score unit for calculating, for each violation of the respective violation rule, a violation score in dependence on the information representing the violation and on a violation rule-specific scheme, and a rule score unit for determining, for the respective violation rule, a rule score from the violation scores of the one or more violations during the simulation.