Circuit Simulation Patents (Class 703/14)
  • Patent number: 8732649
    Abstract: A method and a system for determining the observability of faults in an electronic circuit include a processor that simulates, in a simulation phase, a behavior of the electronic circuit using a simulation model, and that determined, in an analysis phase, based on the simulation, and for each of a plurality of elements of the electronic circuit, time periods in which an occurrent fault could cause a deviation in analysis output signals, where the occurrent fault is determined not to cause any deviation in output signals in other time periods.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: May 20, 2014
    Assignee: Robert Bosch GmbH
    Inventor: Robert Hartl
  • Patent number: 8731894
    Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 20, 2014
    Assignee: Jasper Design Automation, Inc.
    Inventors: Kathryn Drews Kranen, Chung-Wah Norris Ip, Rajeev Kumar Ranjan, Lawrence Loh, Beth C. Isaksen, Yann Alain Antonioli, Craig Franklin Deaton
  • Patent number: 8731737
    Abstract: A microcontroller having a computing unit and a logic circuit. The microcontroller carries out computations for a regulation or control in a vehicle. The computing unit is connected to the logic circuit, and the logic circuit has an arrangement for computing an exponential function and is configurable.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: May 20, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Felix Streichert, Tobias Lang, Heiner Markert, Axel Aue, Thomas Kruse, Udo Schulz, Thomas Richardsen, Michael Saetzler, Ulrich Schulmeister, Nico Bannow, Holger Ulmer, Matthias Schreiber
  • Patent number: 8731893
    Abstract: An arithmetic device calculates the surface potential of a silicon layer by performing computation based on a mathematical expression and device parameters stored in a storage device. Likewise, the arithmetic device calculates the surface potential of a bulk layer under a buried oxide film when the silicon layer is in a partially depleted state and when the silicon is in a fully depleted state. The arithmetic device then performs computation based on the calculated surface potential of the silicon layer, the calculated surface potential of the bulk layer, and mathematical expressions stored in the storage device, and obtains the surface potential of the bulk layer by iterative calculation. The arithmetic device performs computation based on the surface potential of the bulk layer obtained by iterative calculation and mathematical expressions stored in the storage device, and calculates the lower surface potential of the silicon layer.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: May 20, 2014
    Assignee: Hiroshima University, a National University Corporation of Japan
    Inventors: Mitiko Miura-Mattausch, Norio Sadachika, Shunta Kusu, Takaki Yoshida
  • Publication number: 20140136177
    Abstract: A critical path emulating apparatus includes a critical path emulator (CPE) and an interconnection circuit. The CPE is capable of emulating a critical path of a target device, and supporting a plurality of speed information detection modes. The interconnection circuit is capable of supporting a plurality of interconnection arrangements, wherein when the interconnection circuit is configured to have a first interconnection arrangement, the CPE is capable of being used in a first speed information detection mode, and when the interconnection circuit is configured to have a second interconnection arrangement, the CPE is capable of being used in a second speed information detection mode.
    Type: Application
    Filed: November 9, 2012
    Publication date: May 15, 2014
    Applicant: MEDIATEK INC.
    Inventors: Ming-Hsien Lee, Shih-Tsung Hsiao, Hsin-Chen Chen
  • Patent number: 8726210
    Abstract: Systems and methods are provided to optimize critical paths by modulating systemic process variations, such as regional timing variations in IC designs. A method includes determining a physical location of an element in the semiconductor chip design within the critical path. The method further includes modulating a systemic process variation of the semiconductor chip design to speed up the critical path based on a polysilicon conductor perimeter density associated with the element.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: May 13, 2014
    Assignee: International Business Machines Corporation
    Inventors: Albert M. Chu, Manikandan Viswanath
  • Patent number: 8725484
    Abstract: Redundancy extraction in electromagnetic simulation of an electronic device/system includes discretizing first and second spaced conductive layers of a computer model of an electronic device/system into first and second meshes M1 and M2. For each edge between cells of each mesh, a current flow across the edge in response to application of an exemplary bias to the geometry is determined. A square impedance matrix Z* is determined which, for each instance of equal magnitude and opposite direction current flows (EMODCF) in edges E1 and E2 of M1 and M2, has one less row and one less column than the total number of edges in M1 and M2. A voltage column vector V* is also determined which, for each instance of EMODCF, has one less row than the total number of edges in M1 and M2. A current column vector [I*]=[V*]/[Z*] is then determined.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: May 13, 2014
    Assignee: Physware, Inc.
    Inventors: Vikram Jandhyala, Swagato Chakraborty, Dipanjan Gope
  • Publication number: 20140129203
    Abstract: A simulation method to cause an information processing device to calculate, including: reversely tracing a first flux incident on any position on a surface of a workpiece subject to processing treatment from the position; when the first flux strikes another position on the workpiece surface as a result of the reverse tracing of the first flux, calculating a second flux to be the first flux by scattering at the another position and reversely tracing the second flux from the another position; and, by repeating calculation and reverse tracing of flux, when the reversely traced flux no longer strikes the workpiece surface, carrying out comparison of the flux with an angular distribution of a flux incident on the workpiece, and when the current flux is within the angular distribution, obtaining an amount of flux having contributed to the scattering for a flux group from the first flux to the current flux.
    Type: Application
    Filed: October 30, 2013
    Publication date: May 8, 2014
    Applicant: Sony Corporation
    Inventors: Nobuyuki Kuboi, Takashi Kinoshita
  • Publication number: 20140129202
    Abstract: Before supplying a series of instructions to a circuit simulator, methods and systems cache the series of instructions and partition the series of instructions into an active portion and an inactive portion. Instead of supplying the entire series of instructions to the circuit simulator, the methods and systems supply only the instructions directed to the active portion of the integrated circuit to the circuit simulator. Thus, the circuit simulator creates a reduced circuit simulation from just the instructions directed to the active portion (instead of a full integrated circuit that would have been simulated with the entire series of instructions). The reduced circuit simulated by these systems and methods has less circuit elements relative to any integrated circuit that would have been simulated with the entire series of instructions. Thus, this reduced circuit is only a portion of the integrated circuit that would have been simulated.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Sadigh, David W. Winston
  • Patent number: 8718999
    Abstract: The present invention provides a circuit simulation method of executing a high-precision circuit simulation. A voltage fluctuation analysis step at a gate level is executed (step S2). The voltage fluctuation analysis step at the gate level is executed on an entire chip TP. Next, a step of obtaining waveforms of power supply voltage and ground voltage (Vss) according to the voltage fluctuation analysis step is executed (step S4). Subsequently, a signal analysis step at a transistor level is performed (step S6). The signal analysis step at the transistor level is performed in an area narrower than the entire chip TP, for example, on one or more functional modules. After that, a step of obtaining a signal analysis result according to the signal analysis step is executed (step S8).
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: May 6, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Genichi Tanaka
  • Patent number: 8719000
    Abstract: An apparatus and method for performing periodic noise (Pnoise) simulation with full spectrum accuracy is disclosed herein. Noise contributions of a circuit under consideration are identified and separated for different computation treatment. The different computation treatment results in computational efficiency without sacrificing accuracy of simulation results.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: May 6, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Xiaolue Lai, Yu Zhu
  • Patent number: 8718986
    Abstract: A method of generating an ion implantation distribution by a computer is disclosed. The method includes calculating ion implantation distribution regions in a case of generating the ion implantation distribution with a large tilt angle and generating an analytical model of the ion implantation distribution in correspondence with each of the ion implantation distribution regions by using a Gauss distribution model, in which the ion implantation distribution regions have different influence on a channel region depending on a gate structure formed on the ion distribution regions.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: May 6, 2014
    Assignee: Fujitsu Limited
    Inventor: Kunihiro Suzuki
  • Patent number: 8718987
    Abstract: Provided is a circuit simulation model that can suitably represent capacitor characteristics, thereby realizing accurate circuit design and circuit analysis. A SPICE model is constituted of a capacitor unit in which a capacitor is replaced with a linear voltage dependent current source, a low-pass filter unit that has a function of extracting a DC bias voltage, a calculation circuit unit that is configured by combining an adder, a multiplier, and the like to perform a calculation of a circuit equation derived from an equivalent circuit for a capacitor such as an idealized C circuit model, an RC circuit model, or the like, and a linear voltage dependent voltage source that applies a total voltage applied across the capacitor to the calculation circuit.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: May 6, 2014
    Assignee: Taiyo Yuden Co., Ltd.
    Inventor: Xiangying Wu
  • Patent number: 8713489
    Abstract: A parameter correction method includes: obtaining, from a variability-aware simulation, a simulation result value of a predetermined product performance for a reference candidate value set concerning statistics of predetermined product characteristics; calculating a likelihood by substituting the reference candidate value set, the obtained simulation result value, statistics of measurement values of the predetermined product characteristics and a measurement value of the predetermined product performance into a likelihood function that is defined from a probability density function for the statistics of the predetermined product characteristics and a probability density function for the predetermined product performance, and is a function to calculate a combined likelihood of the statistics of the predetermined product characteristics and the predetermined product performance; and searching for a reference candidate value set in case where the calculated likelihood becomes maximum, by carrying out the obtaini
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: April 29, 2014
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Higuchi, Hidetoshi Matsuoka
  • Patent number: 8712751
    Abstract: In a particular embodiment, a first digital function module is created that represents a first analog circuit and a second digital function module is created that represents a second analog circuit. A first value representing a first analog signal is transmitted from the first digital function module to the second digital function module while concurrently or substantially currently, the second digital function module transmits a second value representing a second analog signal to the first digital function module. In a particular embodiment, the first digital function module is a current signal related to an output of the first analog circuit and the second analog signal from the second digital function module is a voltage signal related to an output of the second analog circuit. The values may be transmitted along a bidirectional analog data bus capable of communicating real floating point numbers.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: April 29, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: Jesse Eugene Chen
  • Patent number: 8713492
    Abstract: There is provided a data processing apparatus (1) including a logic circuit (10) that is reconfigurable in each cycle and a library (2) that stores hardware control information (20). The hardware control information (20) includes a plurality of pieces of cycle-based mapping information (21) for individually mapping a plurality of cycle-based circuits, which each realize a function in each cycle for executing an application, onto the logic circuit (10) and configuration selection information (22) for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application. The data processing apparatus (1) includes a control unit (11) that reconfigures at least part of the logic region (10) using at least one of the plurality of pieces of cycle-based mapping information (21) according to a request in each cycle based on the configuration selection information (22).
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: April 29, 2014
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Hiroki Honda
  • Publication number: 20140114636
    Abstract: Systems and methods related to fast simulation of power delivery networks are described. A method is provided for simulating the time-domain responses of a plurality of points of a multi-layer power delivery network, comprising selecting a model of the power delivery network of a circuit, parsing the characteristic data describing the power delivery network, forming a circuit matrix relating to said circuit characteristic data, creating a preconditioner matrix with a specialized structure that allows solution by a Fast Transform solver, simulating the circuit using said circuit and preconditioner matrices by a computer, including a non-transitory computer readable storage medium and at least one processor, but preferably multiple processors, and reporting the responses at selected nodes and branches of the power delivery network.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 24, 2014
    Applicant: NANOTROPIC S.A.
    Inventors: KONSTANTIS DALOUKAS, NESTORAS EVMORFOPOULOS, PANAGIOTA TSOMPANOPOULOU, GEORGIOS STAMOULIS
  • Patent number: 8707221
    Abstract: Embodiments of the invention include systems and methods for automatically predicting production yield for a circuit assembly according to attributes of its components and defect data mapped thereto. Embodiments receive a proposed design specification for a circuit assembly, including bill of materials (BOM) and schematic data, at a yield prediction environment. The yield prediction environment maps a set of attributes to each component in the BOM and maps a set of possible defects to each component according to its attributes. Defects may be further mapped to a manufacturing process assigned to populate each component in the circuit assembly. The defects are associated with predicted frequencies of occurrence, which can be used to roll up a yield prediction for the circuit assembly. Embodiments further allow “what-if” analyses to be performed so that different yield prediction results can be compared according to different form factor options and/or different manufacturing process options.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: April 22, 2014
    Assignee: Flextronics AP, LLC
    Inventor: Michael Anthony Durkan
  • Patent number: 8706467
    Abstract: Embodiments of a computer system for simulating a circuit are described. During a first mode of the simulation, the computer system stores primary signals and circuit relationships between primary signals and secondary signals associated with a portion of the circuit in a file, where the primary signals are independent of gate outputs in the portion of the circuit, and the secondary signals are driven by gates in the portion of the circuit. Moreover, during a second mode of the simulation, the computer system stores dynamic changes in additional relationships between signals to the file, where the signals can include primary signals, secondary signals, or both.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: April 22, 2014
    Assignee: Synopsys, Inc.
    Inventors: Alexander Rabinovitch, Manish Shroff
  • Patent number: 8706453
    Abstract: Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: April 22, 2014
    Assignee: Synopsys, Inc.
    Inventors: Gunnar Braun, Olaf W. J. Zerres, Achim Nohl, Andreas Hoffmann
  • Patent number: 8706468
    Abstract: Circuit component connectivity evaluation and validation method provides comparing and validating the correctness of electrical phase connectivity at connection nodes between conducting components within a circuit model of a power distribution network or other circuit. Phase connectivity requirements of each connected component/device/equipment in a particular circuit are obtained from a Common Interface Model (CIM) file containing parameter data describing the circuit. XML data strings obtained from the CIM file are parsed into enumerated data objects representing each component's phase connectivity requirements and assigned unique four bit binary phase connectivity mask values indicative of the particular electrical phase connectivity requirements of each component.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: April 22, 2014
    Assignee: General Electric Company
    Inventor: Blaine Madison Mucklow
  • Patent number: 8706837
    Abstract: An SAS domain map is automatically generated at an SAS concentrator switch by a virtual mapping device that presents itself as a target for discovery by SAS devices interfaced with the concentrator, such as information handling systems and storage devices. During the SAS protocol discovery process, the virtual mapping device generates the SAS domain map by acquiring the device name and the device port for each concentrator port that interfaces with a device. A management application running on the concentrator applies the SAS domain map to provide network functions, such as zoning or diagnostics.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: April 22, 2014
    Assignee: Dell Products L.P.
    Inventors: Rohit Chawla, Gaurav Chawla, Farzad Khosrowpour
  • Publication number: 20140107998
    Abstract: Systems and methods for prediction of in-plane distortions (IPD) due to wafer shape in semiconductor wafer chucking process is disclosed. A process to emulate the non-linear finite element (FE) contact mechanics model based IPD prediction is utilized in accordance with one embodiment of the present disclosure. The emulated FE model based prediction process is substantially more efficient and provides accuracy comparable to the FE model based IPD prediction that utilizes full-scale 3-D wafer and chuck geometry information and requires computation intensive simulations. Furthermore, an enhanced HOS IPD/OPD prediction process based on a series of Zernike basis wafer shape images is also disclosed.
    Type: Application
    Filed: January 7, 2013
    Publication date: April 17, 2014
    Applicant: KLA-TENCOR CORPORATION
    Inventor: KLA-Tencor Corporation
  • Patent number: 8700377
    Abstract: A method and system for performing analog and RF simulation is disclosed that balances the need for accuracy with the desire for increased simulation speed by using two different circuit descriptions, one description is used during the simulation where needed for accuracy and the other circuit description is used where needed to speed the simulation. For example, one circuit description may include parasitic information and is used where necessary to maintain accuracy and, whereas a reduced circuit description (with at least some parasitic information removed) can be used to enhance speed. This combined solution that uses two different, but related, circuit descriptions has substantially increased the speed of simulation with minimal sacrifice of accuracy.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: April 15, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Pascal Bolcato, Gerard Eichenmueller
  • Patent number: 8700378
    Abstract: A graphical model is received and includes a plurality of entities and connectivity information between the entities. The entities include properties, behavioral descriptions, and optionally behavioral constraints. A symbolic expression is received. The symbolic expression represents a property of a first entity in the graphical model. A second entity is identified. The second entity includes the property represented by the symbolic expression. The second entity is identified based on at least one of the connectivity information, a behavioral description, or a behavioral constraint. The symbolic expression is propagated to the second entity. The second entity is expressed in terms of the propagated symbolic expression. An updated graphical model is generated.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: April 15, 2014
    Assignee: The MathWorks, Inc.
    Inventor: Xiaocang Lin
  • Patent number: 8701066
    Abstract: Some embodiments of the invention provide a method for verifying an integrated circuit (IC) design. The method receives a process description file that specifies a process technology for building the IC. The process description file describes a particular device type in which a first conductor overlaps a second conductor by recessing from the second conductor in one or more cut-outs. Based on the process description file, the method finds a section of the IC design that matches the particular device type and uses the description of the particular device type to compute a capacitance value and a resistance value for the section of the IC design.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: April 15, 2014
    Assignee: Cadence Design Systens, Inc.
    Inventors: Chi-Yuan Lo, Mikhail Khapaev
  • Publication number: 20140100837
    Abstract: A verification system for an integrated device includes a plurality of detailed subsystem virtual prototypes, a plurality of fast subsystem virtual prototypes, and a test controller. The plurality of detailed system virtual prototypes include simulation information for core functionality of subsystems of the device. The plurality of fast system level prototypes include simulation information to facilitate overall functionality of the combined subsystems of the device.
    Type: Application
    Filed: October 8, 2012
    Publication date: April 10, 2014
    Inventors: Stefan Heinen, Juergen Brock, Sindhura Radhakrishnan, Rajshekhar N. Paragond, Shrinivas Rao K. Gowde, Ragu T. Ramachandrarao, Jonas Hoelscher, Goran Magerl
  • Patent number: 8694302
    Abstract: Any primitive cells or blocks can be represented physically by a Barycenter compact model (or Barycenter model), and any black box model can also be physically represented by a Barycenter compact model physically. A hierarchical boundary condition between blocks is formulated by the Barycenter compact model. Hierarchical boundary condition problems between blocks can be limited within two levels only if using the Barycenter compact model.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: April 8, 2014
    Assignee: Worldwide Pro Ltd.
    Inventor: William Wai Yan Ho
  • Patent number: 8694950
    Abstract: Disclosed are a method, system, and computer program product for implementing electronic circuit designs with electrical awareness. The method or the system updates the schematic level tool(s) and physical design tool(s) with electrical parasitic data or electrical characteristic data associated with electrical parasitics so both schematic and physical design tools are aware of the electrical parasitic or characteristic data in performing their functions such as extraction based simulations. The methods or systems are also aware of EM or IR-drop constraint(s) while implementing or creating a partial layout less than a complete layout. The method or the system also provides a user interface for a design tool to provide in situ, customizable, real-time information for implementing electronic circuit designs with electrical awareness. The methods or systems also support constraint verification for electronic circuit design implementation with electrical awareness.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: April 8, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Michael McSherry, David White, Ed Fischer, Bruce Yanagida, Prakash Gopalakrishnan, Keith Dennison, Akshat Shah
  • Publication number: 20140095138
    Abstract: A method for checking for reliability problems includes simulating a circuit having at least one MOS transistor that includes a first MOS transistor. Based on the results of this simulation of the circuit, a gate-to-bulk voltage (Vgb) for the first MOS transistor is calculated. A voltage limit based on the length of the channel of the first MOS transistor is selected. If Vgb is greater than the voltage limit, a warning message is generated.
    Type: Application
    Filed: March 15, 2013
    Publication date: April 3, 2014
    Applicant: LSI CORPORATION
    Inventors: Bonnie E. Weir, David Averill Bell, Stephen C. Kuehne
  • Publication number: 20140095141
    Abstract: A computer identifies a storage element in a simulation model of an integrated circuit design that, during simulation of the integrated circuit design using the simulation model, is subject to having its value forced. In response to identifying the storage element, an indication of the storage element and the associated clock signal are stored in a database. In response to receiving an input indicating the value of the storage element is to be forced during simulation, a determination is made by reference to the database whether or not forcing of the value is mistimed with reference to the associated clock signal. In response to a determination that the forcing of the value as indicated by the input is mistimed with reference to the associated clock signal, an indication that forcing of the value is mistimed is output.
    Type: Application
    Filed: December 6, 2013
    Publication date: April 3, 2014
    Inventors: SANTOSH BALASUBRAMANIAN, AARON C. BROWN, DAVID W. CUMMINGS, AMBALATH MATAYAMBATH ROOPESH
  • Publication number: 20140095139
    Abstract: A method for checking for reliability problems that includes simulating a circuit having at least one MOS transistor. The circuit includes at least a first MOS transistor. Based on the results of the simulation of the circuit, a bulk-to-source voltage (Vbs) is calculated for the first MOS transistor. Based on the calculated Vbs for the first MOS transistor, a threshold voltage (Vth) for the first MOS transistor is calculated. Based on the Vth, an effective Vgs for the first MOS transistor is calculated. And, based on the effective Vgs, a reliability indicator associated with the first MOS transistor is calculated.
    Type: Application
    Filed: March 15, 2013
    Publication date: April 3, 2014
    Applicant: LSI CORPORATION
    Inventors: Bonnie E. Weir, David Averill Bell
  • Publication number: 20140095140
    Abstract: A method of determining a saturation current degradation that includes measuring, for a MOS integrated circuit fabrication process, a first dependence of a saturation current (Idsat) degradation with gate voltage (Vgs) at a level that causes Idsat degradation by bias temperature instability (BTI). A second dependence of the saturation current (Idsat) recovery versus gate voltage (Vgs) is also measured for the MOS integrated circuit fabrication process. A recovery voltage threshold value is determined. The recovery voltage threshold value is indicative of Vgs voltages below which BTI recovery occurs. A circuit having at least one MOS transistor that includes a first MOS transistor is simulated. Based on the results of the simulation, a BTI recovery factor is calculated based on an amount of time the Vgs of the first MOS transistor is below the recovery voltage threshold value.
    Type: Application
    Filed: March 15, 2013
    Publication date: April 3, 2014
    Applicant: LSI CORPORATION
    Inventors: Bonnie E. Weir, Kausar Banoo, Cynthia Lee, David Averill Bell
  • Publication number: 20140096096
    Abstract: An analog circuit simulator includes a processor that is configured to search design data for analog circuits and an analog node connecting the analog circuits; collect variable information that concerns voltage and current variables and is related to input to and output from the analog node; convert the variable information into time functions; and compute the time functions upon each occurrence of a given event and execute simulation of the analog node.
    Type: Application
    Filed: December 3, 2013
    Publication date: April 3, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Satoshi MATSUBARA
  • Patent number: 8689018
    Abstract: An apparatus and method is described herein for reducing noise in a power distribution network for an interface. The power distribution network is characterized. And based on that characterization, worst case patterns for the interface are predicted and avoided. As one example, characterization includes providing a stimulus, such as a step function stimulus, and determining a mathematical function response, such as a step function response. Then, based on the step function response, a resonant frequency for the power distribution network is determined; from which patterns that cause the resonant frequency are identified/predicted. And when identified patterns are detected, they are scrambled or manipulated to avoid causing a worst-case noise scenario in an interface's power distribution network.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: April 1, 2014
    Assignee: Intel Corporation
    Inventors: Satish Prathaban, Ramaswamy Parthasarathy, Maynard C. Falconer
  • Patent number: 8688429
    Abstract: A system for making real-time predictions about an arc flash event on an electrical system is disclosed. The system includes a data acquisition component, an analytics server and a client terminal. The data acquisition component is communicatively connected to a sensor configured to acquire real-time data output from the electrical system. The analytics server is communicatively connected to the data acquisition component and is comprised of a virtual system modeling engine, an analytics engine and an arc flash simulation engine. The arc flash simulation engine is configured to utilize the virtual system model to forecast an aspect of the arc flash event.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: April 1, 2014
    Assignee: Power Analytics Corporation
    Inventors: Adib Nasle, Ali Nasle
  • Patent number: 8689220
    Abstract: A computer program product including computer usable program code embodied on a computer usable medium, the computer program product comprising: computer usable program code for identifying job performance data for a plurality of representative jobs; computer usable program code for running a simulation of backfill-based job scheduling of the plurality of jobs at various combinations of a run-time over-estimation value and a processor adjustment value, wherein the simulation generates data including energy consumption and job delay; computer usable program code for identifying one of the combinations of a run-time over-estimation value and a processor adjustment value that optimize the mathematical product of an energy consumption parameter and a job delay parameter using the simulation generated data for the plurality of jobs; and computer usable program code for scheduling jobs submitted to a processor using the identified combination of a run-time over-estimation value and a processor adjustment value.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Giridhar M. Prabhakar, Rajan Ravindran, Chiranjib Sur
  • Publication number: 20140088948
    Abstract: A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original repeaters connected between at least one source and at least one sink, performing a power optimization analysis on the plurality of original repeaters to change the plurality of original repeaters to low-power repeaters based on predetermined optimization parameters, performing a crosstalk analysis on the model of the circuit including the low-power repeaters to determine whether a crosstalk timing violation exists, and changing at least one of the low-power repeaters to a higher-power repeater when it is determined that a crosstalk violation exists, and leaving the low-power repeaters in the model of the circuit when it is determined that a crosstalk violation does not exist.
    Type: Application
    Filed: November 26, 2013
    Publication date: March 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Paul D. Kartschoke, Adam P. Matheny, Jose L. Neves
  • Publication number: 20140088947
    Abstract: Disclosed is an integrated circuit (IC) chip with a built-in self-test (BIST) architecture that allows for in the field accelerated stress testing. The IC chip can comprise an embedded processor, which selectively alternates operation of an on-chip test block between a stress mode and a test mode whenever the IC chip is powered-on such that, during the stress mode, the test block operates at a higher voltage level than an on-chip functional block and such that, during the test mode, the test block operates at a same voltage level as the functional block and is subjected to testing. Also disclosed are a system, method and computer program product which access the results of such testing from IC chips in a variety of different types of products in order model IC chip performance degradation and to generate IC chip end of life predictions specific to the different types of products.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 27, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Theodoros E. Anemikos, Douglas S. Dewey, Pascal A. Nsame, Anthony D. Polson
  • Patent number: 8682625
    Abstract: Method, system, and computer readable medium are disclosed for analyzing electrical properties of a circuit. The method may comprise: providing a network model including at least one network parameter, the network parameter being defined over a frequency range; converting the network parameter into an intermediate network parameter having first and second portions; identifying first and second frequencies defining a frequency sub-range; replacing the first portion of the intermediate network parameter with a DC value when a frequency associated with the intermediate network parameter is lower than the first frequency; replacing the first portion of the intermediate network parameter with a transitional value when the frequency associated with the intermediate network parameter is within the frequency sub-range; and converting the intermediate network parameter with the replaced first portion into an updated network parameter.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: March 25, 2014
    Assignee: Sigrity, Inc.
    Inventors: Jian Liu, Kaiyu Mao, Jiayuan Fang
  • Patent number: 8682631
    Abstract: A design specifications-driven platform (100) for analog, mixed-signal and radio frequency verification with one embodiment comprising a client (160) and server (150) is presented. The server comprises an analog verification database (110), a code and document generator (1020), a design to specifications consistency checker (103), a symbol generator (104), a coverage analyzer (105), a server interface (106), a web server (111), and an analog verification server application (101). The client comprises a web browser (130), generated datasheets and reports (120), generated models, regression tests, netlists, connect modules, and symbols (121), generated simulation scripts (122), a client interface (124), design data (131), simulators (132), and a design data extractor (123).
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: March 25, 2014
    Inventors: Henry Chung-herng Chang, Kenneth Scott Kundert
  • Patent number: 8682634
    Abstract: Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Saeed Bagheri, Fook-Luen Heng, Rajiv Vasant Joshi, Kafai Lai, David Osmond Melville, Saibal Mukhopadhyay, Alan E Rosenbluth, Rama N. Singh, Kehan Tian
  • Patent number: 8683400
    Abstract: A apparatus and method for conducting fault sensitivity analysis of the analog portions of a mixed signal circuit design includes simulating the fault free circuit design, inserting a fault into the analog portion of the circuit design, simulating the circuit design with the fault during a fault interval time period, and determining whether the fault is detectable.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: March 25, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, Ilya Yusim, Zhipeng Liu
  • Patent number: 8682466
    Abstract: A method to enable wafer result prediction includes collecting manufacturing data from various semiconductor manufacturing tools and metrology tools; choosing key parameters using an autokey method based on the manufacturing data; building a virtual metrology based on the key parameters; and predicting wafer results using the virtual metrology.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: March 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Francis Ko, Chih-Wei Lai, Kewei Zuo, Henry Lo, Jean Wang, Ping-Hsu Chen, Chun-Hsien Lim, Chen-Hua Yu
  • Patent number: 8682637
    Abstract: In accordance with embodiments, there are provided mechanisms and methods for comparing results of performing a plurality of operations with results of simulating the plurality of operations. These mechanisms and methods for comparing results of performing a plurality of operations with results of simulating the plurality of operations can enable optimized performance of operations, reduced processing time, increased confidence in processing results, etc.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: March 25, 2014
    Assignee: salesforce.com, inc.
    Inventors: Punit Jain, Yongsheng Wu, Yanik Grignon, Shitij Agarwal
  • Patent number: 8676559
    Abstract: A system and method for providing schematic reviews is provided. The method includes providing a schematic design, selecting a signal, where the signal is a graphical representation, previewing the signal, obtaining relevant information on components constituting the signal, and controlling the signal to obtain relevant information on the components. Controlling the signal comprises activating a link to a data compilation related to the signal component, and activating the data compilation comprises creating a link to a datasheet. The graphic representation of the signal comprises providing a block diagram overview of connectivity of the signal components and the graphical representation comprises a graphical three dimensional model, and providing a log database that includes review information provided by multiple reviewers and is accessible by the reviewers. A notation medium is provided for the reviewers for communication between the reviewers.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Saravanan Sethuraman, John Francis Mullen
  • Publication number: 20140074449
    Abstract: A high-frequency supply voltage waveform is sampled from a functioning integrated circuit. This waveform is measured at (or coupled closely to) a power supply node on the integrated circuit. A low-frequency supply current waveform is sampled concurrently with the sampling the high-frequency supply voltage waveform. This waveform is measured at a power supply node external to the integrated circuit. A power supply network providing power to the integrated circuit is modeled with a circuit model. The power supply network is modeled using the high-frequency supply voltage waveform as an input to the circuit model. A simulation output is taken at a simulated power supply node corresponding to the power supply node external to said integrated circuit. Based on a comparison of the simulated low-frequency supply current waveform and the low-frequency supply current waveform, a value of at least one component of the circuit model is adjusted.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 13, 2014
    Applicant: LSI CORPORATION
    Inventors: Mark F. Turner, Jonathan W. Byrn, Robert F. Kalinowski, Paul R. Crellin
  • Patent number: 8670970
    Abstract: In one embodiment of the present invention, the performance of an electronic circuit having a clock path between a clock source cell and a clock leaf cell is characterized over a simulation duration, where the clock path has one or more intermediate cells. Variations in the effective power supply voltage level of at least one intermediate cell over the simulation duration are determined using a system-level power-grid simulation tool. Static timing analysis (STA) software is used to determine cell delays for at least one of the intermediate cells for different clock-signal transitions at different times during the simulation duration. The cell delays are then used to generate one or more metrics characterizing the performance of the electronic circuit, such as maximum and minimum pulse widths, maximum cycle-to-cycle jitter, and maximum periodic jitter.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: March 11, 2014
    Assignee: Agere Systems LLC
    Inventor: Hyuk-Jong Yi
  • Patent number: 8670969
    Abstract: A method for eliminating the Fourier analysis noise floor generated by a circuit simulator is disclosed. This is accomplished by making the simulator behavior during each Fourier analysis sample interval (704) algorithmically identical to that employed during every other sample interval. Thus between each Fourier analysis sample point (703), the step size, number of iterations, integration method, etc., are allowed to vary as needed with the proviso that each sample interval uses exactly the same sequence of time steps, and that each member of that sequence is algorithmically identical to the corresponding members in the sequences used on every other Fourier sample interval. In other words, the first time step in the first interval must be algorithmically identical to the first time step in every other interval. The same is true for the second step, the third step, and so on until the last step.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: March 11, 2014
    Inventor: Kenneth Scott Kundert
  • Patent number: 8671372
    Abstract: A verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition is greater than the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in the test scenario group.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: March 11, 2014
    Assignee: Fujitsu Limited
    Inventors: Ryosuke Oishi, David Thach, Yutaka Tamiya