Abstract: An electronic circuit, comprising at least an analog part, subjected to predefined input signals in the time domain, is broken down into at least one modeled elementary block. The input signal is transformed into a simulation signal which comprises at least one useful signal component representative of the spectral power density of the input signal. Application to an input of the simulation signal circuit is simulated. The useful component of the simulated signal is computed on output of each successive block. The useful component of the simulated signal output from the circuit is compared with at least one predefined signal to test at least one characteristic of the circuit. A noise component can be introduced in a simulation signal or in the output signal of a block passed through.

Abstract: A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality of arcs. Each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate. The method selects a plurality of substantially distinct vectors from the plurality of vectors for each of the plurality of arcs, and performs circuit pruning for each of the plurality of substantially distinct vectors, taking each one substantially distinct vector at a time. The circuit pruning includes identifying an active circuit for each vector. The active circuit is identified by determining which circuit features are activated when applying a particular one of the substantially distinct vectors. Then, the circuit simulations limited to a plurality of transistors in the active circuit are performed.

Abstract: A CMOS model generating apparatus 1 according to the present invention generates a CMOS model by converting an In-Ip space into an xn-xp space such that a typical condition TT and corner conditions FF, SS in the In-Ip space become (0, 0), (?, ?) and (??, ??) in the xn-xp space, determining an ellipse fitting to the respective mappings of the corner conditions FF, SS, FS and SF with the mapping (0, 0) of the typical condition TT as a center, expressing two independent principal components in the form of a Gaussian distribution using the major and minor axes of this ellipse as axes of the principal components, and obtaining a probability distribution determining deviations of the Gaussian distribution such that the cumulative probability within this ellipse becomes equal to the one presumed by the corner conditions FF, SS, FS and SF.

Abstract: A system, method, and software program for facilitating the assignment of cell specifications to a plurality of cells of a system design. The methods include generating a plurality of candidate cell specifications that meet the specification for the system design. In one embodiment, the method entails using information related to intra-range preference for cell specifications to generate a set of alternative system pareto-optimal solutions which define a boundary of a region of candidate cell specifications. In another embodiment, the method entails generating a substantially uniform set of candidate cell specifications using a prediction-based performance model, such as support vector regression model or cluster-weighted model, an optimizing algorithm such as conjugate-gradient or Markov Chain Monte Carlo Method, and a sample density model.

Abstract: One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a first area in a first layout, wherein the first area is associated with a first feature. Next, the system determines a first sample using the first check-figure, wherein the first sample represents the first layout's geometry within a first ambit of the first check-figure, wherein the first sample's geometry is expected to affect the shape of the first feature. The system then performs a model-based simulation using the first sample to obtain a first simulation-result which indicates whether the first feature is expected to have manufacturing problems. Next, the system stores the first simulation-result in a database which is used to quickly determine whether a second feature is expected to have manufacturing problems.

Abstract: An automated model componentization feature systematically converts duplicate or otherwise amenable patterns in a model into references. Multiple references are simplified to one unit that contains the otherwise duplicated functionality. Duplicated or selected functionality is identified based on a number of arguments that may be user supplied. These arguments include the level of polymorphism (i.e., which of the sample times, dimensions, and data types can be propagated in) but also the maximum size of the patterns to look for to address the general trade-off of generating few partitions with many blocks or many partitions with few blocks and which modeling constructs are used (e.g., whether Go To/From connections such as in Simulink® are present). Model conversions can result in potentially disjoint partitions.

Abstract: Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.

Abstract: A method of simulating operation of a bitcell includes determining sensitivities of a bitcell model to different component characteristics and device parameters, such as device temperature, operating voltage, and process characteristics. The determined sensitivities are normalized, so that each normalized value represents the relative sensitivity of the bitcell, under the simulated device parameters, to the component characteristic associated with the value. The normalized sensitivity values can be scaled based on a tolerance factor, and the adjusted sensitivities used to model the behavior of each component of the bitcell in subsequent simulations.

Abstract: Methods for generating simulation vectors incorporating periodic jitter, or phase-shifted periodic jitter are disclosed. Periodic jitter, such as sinusoidal jitter, is preferably represented by a mathematical equation which defines the amount of jitter experienced at each cycle of a clock or data signal. The calculated periodic jitter for each cycle is used to form a new multi-cycle vector incorporating the jitter. If a particular signal to be simulated additionally needs to travel a particular distance such that it would experience a time delay, that time delay may also be incorporated into the jitter equation as a phase shift. So incorporating the time delay into the jitter equation allows for the easy simulation of circuits receiving the vectors without the need to actually design or “lay out” the circuits that imposing the time delay.

Abstract: A method, system and article of manufacture are disclosed for constructing corner models for multiple performance targets for circuit simulations. The method includes identifying N (N?2) device and/or circuit performance targets F1, F2, . . . , FN, and obtaining their correlation matrix R using Monte Carlo simulations, analyzing measured hardware data, or using the linear sensitivities of the N targets on M statistical model parameters; b) calculating a normalized joint probability density (JPD); and c) when ?1, . . . , ?N values are already set (each ?i, takes only one value), proceeding to build a common and optimal corner for the N targets when p(N)?pth(N).

Abstract: An integrated circuit configured for hardware co-simulation can include a command processor, a replay buffer storing a command template, wherein the command template specifies an incomplete command, and a command first-in-first out (FIFO) memory storing complementary data for completion of the command template. The integrated circuit further can include a multiplexer coupled to the command processor, the replay buffer, and the command FIFO. The multiplexer, under control of the command processor, can selectively provide data from the replay buffer or the command FIFO to the command processor. The command processor, responsive to a replay command read during a hardware co-simulation session, can enter a replay mode, obtain the command template from the replay buffer, obtain the complementary data from the FIFO memory according to a symbol read from the command template, and form a complete command by joining the command template with the complementary data.

Abstract: A computer-implemented method for marking-up an executable model includes: displaying the executable model; associating an electronic overlay with the executable model, the electronic overlay operating with the executable model without changing the contents of the executable model; and indicating an electronic markup to the executable model using the electronic overlay wherein the electronic markup affects functionality of the executable model when the executable model is executed with the electronic overlay.

Abstract: Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions specify the effects of accesses to a memory by a set of memory ports given a set of parameters chosen by the user.

Abstract: A circuit verifying method is provided for a logic circuit of a first sequential circuit which outputs a first data based on an input data in synchronization with a first clock signal, and a second sequential circuit which outputs a second data based on the first data in synchronization with a second clock signal with a period longer than that of a first clock signal. The circuit verifying method includes detecting a change of the input data in synchronization with the first clock signal; outputting a data indicating a meta stable state during a period longer than one period of the first clock signal based on the change of the input data as the first data; storing the changed input data in a storage unit based on the change of the input data; and outputting the changed input data which has been stored in the storage unit as the first data after stop the output of the data indicating the meta stable state.

Abstract: A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality of arcs. Each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate. The method selects a plurality of substantially distinct vectors from the plurality of vectors for each of the plurality of arcs, and performs circuit pruning for each of the plurality of substantially distinct vectors, taking each one substantially distinct vector at a time. The circuit pruning includes identifying an active circuit for each vector. The active circuit is identified by determining which circuit features are activated when applying a particular one of the substantially distinct vectors. Then, the circuit simulations limited to a plurality of transistors in the active circuit are performed.

Abstract: A mechanism for providing equation-level diagnostic error messages for system models undergoing circuit simulations is discussed. The components in a model of a system being simulated are converted into multiple numerical equations where each equation corresponds to a component in the system being simulated or a topology equation for the system model. Each numerical equation is numerically analyzed in order to identify illegal configurations in the system. Upon detection of an error, an error message listing the components associated with the illegal configuration is generated for the user.

Abstract: A computer is programmed to prepare a computer program for simulating operation of an integrated circuit (IC) chip, in order to test scan circuitry therein. The computer is programmed to trace a path through combinational logic in a design of the IC chip, starting from an output port of a first scan cell and ending in an input port of a second scan cell. If the first and second scan cells receive a common scan enable signal, then the computer generates at least a portion of the computer program, i.e. software to perform simulation of propagating a signal through the path conditionally, for example when the common scan enable signal is inactive and alternatively to skip performing simulation when the common scan enable signal is active. The computer stores the portion of the computer program in memory, for use with other such portions of the computer program.

Abstract: A design method of printed circuit boards includes the following steps. First, simulate a printed circuit board including power layers, and vias connected to all the power layers. Then, change connections of the vias that tend to draw too much current to be connected to fewer power layers, than the vias that tend to draw less current. Repeat adjusting connections of the vias until all vias draw a similar amount of current such that no via draws more current than an upper limit the vias are designed for. Finally, according to the results, design/fabricate a PCB with vias respectively insulated, as needed, from the power layers that do not need to be connected to the vias.

Abstract: A design is simulated utilizing a hardware description language (HDL) simulation model by stimulating the HDL simulation model with a testcase. The HDL simulation model includes instrumentation not forming a portion of the design that includes a count event counter for a count event in the design, and the simulation includes counting occurrences of the count event in the count event counter to obtain a count event value. A threshold is also established for an aggregate count event value for the count event counter. After completion of the testcase, a determination is made whether addition of the count event value to the aggregate count event value for the count event counter would cause the aggregate count event value to exceed the threshold. If not, the count event value is recorded in a testcase data storage area, and the count event value is accumulated in the aggregate count event value. If so, the count event value is discarded without recording the count event value in the testcase data storage area.

Abstract: A coupled analysis simulation apparatus includes a coupled analysis processing unit configured to perform coupled analysis by performing electromagnetic field analysis and circuit analysis in coordination with each other, the electromagnetic field analysis being performed on a space including conductive layers to which an electronic circuit module is connected, the circuit analysis being performed on the electronic circuit module; a first generating unit configured to generate a virtual conductive part in a section or a region including connection parts connecting the electronic circuit module with the conductive layers; and a second generating unit configured to generate virtual connection parts that virtually connect the virtual conductive part with the conductive layers at positions where the connection parts are connected to the conductive layers.

Abstract: A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.

Abstract: Methods and apparatus are provided for analyzing transmission lines with decoupling of connectors and other circuit elements. According to one aspect of the invention, circuits with one or more parasitic elements are analyzed by partitioning at least one of the parasitic elements in a transverse manner; identifying a plurality of subcircuits each comprised of partitioned circuit elements from the plurality of transmission lines and one or more parasitic elements in a given path; wherein each of the subcircuits is associated with a path in the circuit; performing a waveform relaxation analysis between each of the subcircuits; and repeating the step of performing the waveform relaxation analysis using waveforms determined in a previous iteration until convergence to a resultant waveform has occurred. The circuit can optionally further comprise one or more transmission lines which would also be partitioned in a transverse manner.

Abstract: A method of determining the intrinsic electrical characteristics of a device under test (DUT) includes determining a set of test measurements for a test structure including the device and determining test measurements for a number of de-embedding test structures. Based on the test measurements, DUT measurements are determined using both open-short and three-step de-embedding processes. The DUT measurements are combined to determine an imperfection error, which is used to adjust the calculations of a four-port de-embedding method. The adjusted calculations provide for a more accurate measurement of the parasitic elements in the test structure, thereby improving the determination of the intrinsic electrical characteristics of the device.

Abstract: A method for laying out decoupling cells in a semiconductor integrated circuit including a plurality of paths. The method includes extracting from a timing analysis result a timing slack amount as a timing margin for power supply noise in one of the paths serving as a target path, converting the extracted timing margin to a noise tolerance amount, comparing the noise tolerance amount and a power supply noise amount of the target path, and determining whether or not a decoupling cell must be additionally laid out in the target path based on the comparison result.

Abstract: A circuit simulation apparatus according to an embodiment of the present invention calculates a set value of a SPICE parameter of a MOSFET to carry out a variation analysis on a semiconductor circuit including the MOSFET.

Abstract: Mechanisms for generating a worst case current waveform for testing of integrated circuit devices are provided. Architectural analysis of an integrated circuit device is first performed to determine an initial worst case power workload to be applied to the integrated circuit device. Thereafter, the derived worst case power workload is applied to a model and is simulated to generate a worst case current waveform that is input to an electrical model of the integrated circuit device to generate a worst case noise budget value. The worst case noise budget value is then compared to measured noise from application of the worst case power workload to a hardware implemented integrated circuit device. The worst case current waveform may be selected for future testing of integrated circuit devices or modifications to the simulation models may be performed and the process repeated based on the results of the comparison.

Abstract: Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component.

Abstract: A system and method for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.

Abstract: A technique for determining thermal design point (TDP) power efficiency for an integrated circuit is disclosed. A simulation executes a set of input vectors on a model of an integrated circuit to generate a first estimated power consumption data during a first number of clock cycles. A simulation executes the set of input vectors on a model of an integrated circuit to generate a second estimated power consumption data during a second number of clock cycles. TDP power efficiency for the integrated circuit is calculated based on the first estimated power consumption data and the second estimated power consumption data.

Abstract: Simulation method and system for analyzing the stability of a modeled electronic circuit. Simulation of the transient response to a desired input stimulus is performed in a piece-wise fashion, in a sequence of transient time points. At one or more user-specified time points (“tpunch” points) within the transient interval, the state of the circuit in the transient response at that time point is applied to the model as if it were a DC operating point, and the small-signal stability of the circuit under those conditions is analyzed. Transient instability of the circuit is thus discovered by way of simulation, allowing the designer to determine the cause and cure of that instability.

Abstract: Systems and methods are provided for verifying respective configuration data values for programming configuration memory cells of an integrated circuit device such as a programmable logic device (PLD). Each configuration memory cell controls an input of a corresponding initialization value from a file in response to a selectable assertion of an initialization signal of a test bench during a logic simulation of the PLD. The file structurally associates the configuration memory cell with the corresponding initialization value. A current value of one or more of the configuration memory cells is written with the respective configuration data value via a configuration port of the PLD during the logic simulation. Each configuration memory cell compares its initialization and current values in response to a selectable assertion of a check signal of the test bench. A mismatch error is output in response to a difference between the initialization and current values of one or more of the configuration memory cells.

Abstract: Within a high level modeling system (HLMS), a method of visualizing a circuit design can include identifying the circuit design and reading hardware cost information for the circuit design. The method also can include presenting a graphical representation of the circuit design having at least one visual characteristic which can be varied according to the hardware cost information.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

Abstract: According to a method of simulation processing, one or more HDL source files describing a digital design including a plurality of hierarchically arranged design entities are received. The one or more HDL source files include one or more statements instantiating a plurality of print events within the plurality of hierarchically arranged design entities, where each print event has an associated message and at least one associated signal in the digital design. The one or more HDL source files are processed to obtain a simulation executable model including a data structure describing the plurality of print events defined for the simulation executable model and associating each of the plurality of print events with its respective associated signal.

Abstract: A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.

Abstract: A method and an apparatus for verifying a logic circuit, capable of quicker operation, being applied to a logic gate-level or transistor-level circuit design, and verifying timing and analog signal characteristics of a signal. The logic circuit verification method includes a wave file generation stage and a logic circuit verification stage. The wave file generation stage generates a wave file that includes the waveforms of all nodes of the logic circuit using a design source file of the logic circuit. The stage of verification of the logic circuit verifies the logic circuit using a design reference file, which includes ideal operations of all the nodes of the logic circuit, and the wave file.

Abstract: A test quality evaluating and improving system has a fault-layout information link section which creates a weighted fault dictionary by correlating a layout element related to an undetected fault, out of faults corresponding to a specified fault model and occurring in a circuit to be tested, with the undetected fault as a weight of the undetected fault which cannot be detected by a test pattern for testing the faults; a test quality measure calculating section which multiplies the weight of the undetected fault, the failure mode-fault model correlation factor for correlating the failure mode of the layout element and the fault model, and the failure occurrence rate of each layout element, and outputs an obtained product as a failure remaining rate of the test pattern; a determining section; and a test point inserting section.

Abstract: A cycle basis is efficiently determined for a directed graph. A first depth-first search of the directed graph classifies each of the edges of the directed graph to have a type that is one of a within-tree type for an edge within a tree of the first depth first search, a forward type for an edge skipping forward along the tree, a back type for an edge directed back along the tree, or a cross type for an edge between two subtrees of the tree. A second depth-first search of the directed graph determines a respective cycle for each of the edges of the back type. A third depth-first search of the directed graph determines a respective cycle for each of the edges of the cross type that is included a cycle. The basis is output the basis that specifies each of the respective cycles.

Abstract: A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a well resistor comprising a terminal region and a main body; and a plurality of contacts formed above the terminal region, the simulation method comprising: modeling a parasitic resistance Rt0 of the terminal region between the plurality of contacts and the main body by the following formula, where ?0, L?0, W?0 are fitting parameters; L? is a length of the terminal region in the longitudinal direction of the well resistor; and W? is a width of the terminal region in the width direction of the well resistor.

Abstract: A simulator is partitioned into a functional component and a behavior prediction component and the components are executed in parallel. The execution path of the functional component is used to drive the behavior prediction component and the behavior prediction component changes the execution path of the functional component.

Abstract: A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a semiconductor resistor; a plurality of contacts arranged at regular intervals in a longitudinal direction and in a width direction of the semiconductor resistor on a terminal region of the semiconductor resistor; and a wiring line formed on the plurality of contacts, the simulation method including: defining a ratio of a parasitic-resistance by the semiconductor resistor between two of the contacts neighboring in the longitudinal direction to a resistance of one of the plurality of contacts as a constant k; and modeling a parasitic-resistance net by using the constant k, the parasitic-resistance net including the terminal region of the semiconductor resistor and the plurality of contacts.

Abstract: An apparatus for analyzing circuit specification description design has a circuit specification description inputting section that analyzes and obtains information of a related signal, information of the maximum number of cycles in the related signal, and a definite value in a site defined in the circuit specification description for the related signal contained in a circuit specification description, a data base generating section that generates signal variation data indicating time-series signal variation, wherein a definitive value is set in the site defined in the circuit specification description and a predetermined flag is set in a site where the value is not defined in the signal variation data, and a waveform diagram data outputting section that outputs waveform diagram data for displaying the time-series signal variation in a form of a waveform diagram on the basis of the definite value and the predetermined flag set in the data.

Abstract: The present invention is a method and apparatus for creating a reduced-order IC interconnect model, which incorporates variations in interconnect process parameters, and models both on-chip and off-chip interconnects. The method is based on mathematically representing an IC interconnect system, including mathematical interconnect process parameter terms, which are manipulated to facilitate simplification of an IC interconnect model. The IC interconnect model is then simplified by using a mathematical technique called state-space projection. Specifically, an IC interconnect system is represented with at least one modified nodal analysis equation (MNA) that is based on frequency, interconnect process parameters are added and substituted back into the MNA(s), terms with interconnect process parameters are explicitly matched. A state-space projection is created, which implicitly matches frequency terms. The state-space projection is used to create the reduced-order IC interconnect model.

Abstract: A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.

Abstract: Various techniques related to clocking signals used for automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving first and second asynchronous clock signals having a first phase relationship at a first time, and sampling the second clock signal at transitions of the first clock. The method further includes storing the samples; and analyzing the samples to ascertain the first phase relationship of the second clock signal with respect to the first clock signal and provide a representation of the first phase relationship. Other embodiments are described.

Abstract: A computer is programmed to automatically generate in memory, goals for functional verification of a design of a circuit by use of constraints that are specified in the normal manner. Specifically, a predetermined set of rules are automatically applied to the constraints, on random values for signals to be input to the circuit during simulation of the design. Application of the rules identifies one or more templates of goal(s) to be met. The computer is programmed to automatically use constraint(s) and template(s) to instantiate goal(s) in memory. Each goal identifies a signal to be input to the circuit, and defines a counter for a value of the signal. The goals are used in the normal manner, i.e. used to measure coverage of functional verification during simulation of the design of the circuit.

Abstract: A method of generating a scenario includes generating a specification model by describing a specification in a predetermined descriptive language, extracting a plurality of operations from the specification model, generating a plurality of operation descriptions, each of which corresponds to one of the operations and includes an operation name and a constraint condition, generating at least one cause-effect graph that combines the operations based on the operation descriptions, and extracting as a scenario a series of operations from the cause-effect graph.

Abstract: A method for converting a C-type programming language program to a hardware design, where the said program is an algorithmic representation of one or more processes. The C-type programming language program is compiled into a hardware description language (HDL) synthesizable design. The compiler categorizes variables as using either implicit memory or custom memory. Different accessor functions are used depending on which type of memory is used. The programming language may use ANSI C and the HDL may be Verilog Register Transfer Level (RTL). The hardware device generated from the HDL synthesizable design may be an Application-Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA).

Abstract: A computer implemented method, apparatus and computer program product for extending test coverage in a simulated multiple core integrated circuit. The simulator applies at a first time a first test vector on the simulated multiple core integrated circuit, the first test vector having a duration. The simulator may also apply a second test vector at a second time before the duration but substantially after the first time. The simulator can collect a response from the multiple core integrated circuit based on the first test vector and the second test vector.

Abstract: A modular representation of a physical system is generated using modules and variables, each module representing a portion of the physical system, each variable representing a parameter of the physical system. Code is generated according to the modular representation such that the code is suitable to be compiled into a machine code that can be executed on hardware to simulate the physical system. The code contains instructions to cause the hardware to solve a system of differential algebraic equations that represent relationships among the variables.