Abstract: A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are routed in between fully connected power and ground shield mesh which may be generated by a router during the signal routing phase or during power mesh routing phase. Leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device. Another embodiment presents a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment presents a multi-layer grid routing technique where signals are routed on even grid and the power and ground lines are routed on odd grid.

Abstract: A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X1 and at least one other matrix, with first equation including X1Y, X1A, and X1P, and the second equation including X1A and X1P.

Abstract: A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a cell library for use in static timing analysis (STA). During STA, the setup and hold skews calculated for each synchronous circuit are compared with a selected setup/hold time pair stored in the cell library (e.g., a pair having a relatively low hold value). If at least one of the setup and hold skews violates the selected setup/hold time pair, then the remaining identified setup/hold time pairs (or the PWL approximation) are utilized to determine if the synchronous circuit is violates established constraints, and if not, to identify the setup and hold times required to remove the violation.

Abstract: Methods for generating realistic waveforms with controllable voltage noise and timing jitter in a computer-based simulation environment and the simulation of a subset of those waveforms with system elements along the signal path is disclosed. By deriving a generic, re-useable, parameterized Fourier series, time-domain clock and pseudo-random data signals are generated from a subset of their true harmonic components. Time-domain signal parameters including high, low, and common-mode voltage levels, transition slew-rates, transition timing, period and/or frequency, may be designated by the user, and the computer calculates the harmonic components that will combine through the inverse Fourier transform to provide the required time-domain characteristics. By computing the frequency content of the signal directly it is possible to simulate the interaction of the signal with various system blocks while remaining in the frequency domain, thereby reducing simulation time and memory requirements.

Abstract: Signal selecting apparatus 100 according to the present invention for determining an operation parameter of circuit 101 includes circuit analyzing means 110 for enumerating signals in the circuit that are to be measured for the operation parameter when information of the circuit is input thereto, observation signal number determination means 111 for statistically determining the number of observation signals required to determine the operation parameter from the width and reliability of an estimated error and from the number of enumerated signals, and observation signal selecting means 112 for selecting, from the enumerated signals, the same number of signals as the number of observation signals.

Abstract: In various implementations of the invention, methods and apparatuses are provided that enable timing accurate, bit level hardware models for simulation at a rapid rate. With various implementations of the invention, a functional module is combined with a timing module. The combination may be employed to assist in performing performance modeling. With various implementations of the invention, a functional module, a timing module, and a module wrapper are provided, the module wrapper having at least a slave and master port. The slave port and the master port allowing for the exchange of data between modules, between the module and a host computing environment, and between the module and a performance modeling platform.

Abstract: A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.

Abstract: Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.

Abstract: A method and system for designing a structural level description of an electronic circuit with functional behavior described by a plurality of rules, the circuit being specified by data path and control path elements wherein at least one control path element is provided in a form of unresolved variable. The design comprises extracting a plurality of unresolved variables among the control path elements and automatic processing of data path and control path elements for accomplishing a state machine formulation, wherein the states of the state machine include states representing at least combinations of unresolved variables and corresponding transitions satisfying said plurality of rules and predefined design criteria.

Abstract: Some embodiments provide techniques for determining a set of Abbe's kernels which model an optical system of a photolithography process. During operation, the system can receive optical parameters (e.g., numerical aperture, wavelength, etc.) for the photolithography process's optical system. Next, the system can use the optical parameters to determine a point spread function for an Abbe's source. Note that the point spread function for the Abbe's source can be determined either by discretizing the optical system's light source using a set of concentric circles, or by discretizing the optical system's light source in an orthogonal fashion. The system can then determine a correlation matrix from the point spread function. Next, the system can determine the set of Abbe's kernels by performing an eigen decomposition of the correlation matrix using principal component analysis. The system can then use the set of Abbe's kernels to compute image intensity.

Abstract: In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains a latch having a respective plurality of different possible latch values. With one or more statements in one or more files, a configuration entity is associated with the latch. The configuration entity has a plurality of different settings and each setting reflects which of the plurality of different possible values is loaded in the associated latch. A controlling value set for at least one instance of the configuration entity is also defined in one or more files. The controlling value set indicates at least one controlling value for which presentation of a current setting of the configuration entity instance is restricted.

Abstract: A method, and computer program product and system for performing the method, is provided for designing a mask used in the manufacture of semiconductor integrated circuits, in which a model of the lithographic process is used during the mask design process. More particularly, the on-wafer process model is a function of optical image parameters that are calibrated using measurements from a test pattern. An uncertainty metric for the predicted response simulated by the on-wafer process model is computed for a given evaluation point of interest as a function of a distance metric between the collective optical image parameters simulated at the given evaluation point and the collective optical image parameters at the calibration data points. The uncertainty metric preferably is also a function of the sensitivity of the on-wafer process model response to changes in the optical image parameters.

Abstract: Methods and apparatus for designing and measuring a cell-electrode impedance sensor to detect chemical and biological samples, including biological cells. The method of designing a cell-electrode impedance sensor comprises: determining a cell free cell-electrode impedance and a cell-covered cell-electrode impedance; obtaining a sensor sensitivity of the cell-electrode impedance measurement system; and choosing one or more design parameters of the cell-electrode impedance sensor to maximize the sensor sensitivity. When the frequency of AC signal between electrodes ranges from 10 kHz to 40 kHz, the sensitivity of the sensor is maximized.

Abstract: A computer-implemented method is provided for optimizing configuration of absorption enhancement structures for use in a photovoltaic enhancement film that is applied onto a PV device to improve absorption. The method includes receiving optimization run input defining a PV enhancement film including defining absorption enhancement structures with differing configurations. The method includes modeling a PV device including PV material such as a silicon thin film. A first ray tracing is performed over a range of incidence angles for the PV device. The method includes determining a set of base path angles for the PV material layer based on this first ray tracing. A second ray tracing is performed for the PV device with the enhancement film, which has absorption enhancement structures. Enhanced path lengths are determined based on the second ray tracking, and path length ratios are determined by comparing the enhanced path lengths to the base path lengths.

Abstract: A circuit verification device includes a simulation section and a determination section. The simulation section performs a first simulation using a first net list and a second simulation using a second net list. The first net list includes a size parameter of the pair of transistors and, in the first net list, an instance parameter of a first transistor is specified as +P and an instance parameter of a second transistor is specified as ?P, and the second net list includes the same size parameter as in the first net list and, in the second net list, the instance parameter of the first transistor is specified as ?P and the instance parameter of the second transistor is specified as +P. The value of P is set at ?, which is ½ the control upper limit of mismatch of the threshold voltage between the pair transistors.

Abstract: A system and method for simulating a circuit design using both an unknown Boolean state and a negative unknown Boolean state is provided. When the circuit is simulated, one or more initial simulated logic elements are initialized to the unknown Boolean state. The initialized unknown Boolean states are then fed to one or more simulated logic elements and the simulator simulates the handling of the unknown Boolean state by the simulated logic elements. Examples of simulated logic elements include gates and latches, such as flip-flops, inverters, and basic logic gates. The processing results in at least one negative unknown Boolean state. An example of when a negative unknown Boolean state would result would be when the unknown Boolean state is inverted by an inverter. The resulting negative unknown Boolean state is then fed to other simulated logic elements that generate further simulation results based on processing the negative unknown Boolean state.

Abstract: A method for performing an analysis of at least one logic stage in a netlist, which include one or more drivers, is provided. The method includes operations of generating at least one look-up table for an output transient current to be based on values of input and output voltages using data available from a cell library; synthesizing analytically at least one current source model, which includes a DC component and a plurality of parasitic capacitances, using the look-up table; simulating the logic stage using the current source model to model the drivers; and obtaining characteristics of the simulated logic stage. A system and a machine-readable medium for performing the method are also provided.

Abstract: A partitioning method for an integrated circuit (IC) design includes providing a textual file representing the design as library-specific cells and interconnections, including timing data for the cells and timing data derived from the design after placement and routing. The design is flattened to cell level. Edge-triggered flip-flops (ETFF's) are selected and divided into two groups by communications attributes. First group is subdivided into the number of subsets in the partition. The ETFF's in each subset are analyzed by their communications attributes, and divided into those that connect to circuit elements outside the particular subset, and those that do not, reducing intersubset communications and placing them under external clock control. The partition is electrically equivalent to the design. The design is simulated by placing each subset on its own computer with simulator software. The computers are interconnected. User interventions may be allowed.

Abstract: An apparatus, computer system, and storage medium that, in an embodiment, receive elements and a goal for each of the elements. In various embodiments, the elements may represent commands or parameter values for a device to be tested. Testcases are generated based on the elements. If the numbers of testcases for the elements are equally distant from their goals, then a new testcase is generated based on an element chosen at random. But, if the numbers of testcases are not equally distant from their goals, then the new testcase is generated based on the element whose number of testcases if furthest from its respective goal. The number of testcases associated with the chosen element is then incremented, and the process is repeated. In this way, the generated testcases are based on the numbers of previously generated testcases, which, in an embodiment, results in more complete coverage of testcases for the device under test.

Abstract: A design method of a semiconductor device is provided with a mask region setting step of setting a mask region to a layout of the semiconductor device, a parasitic parameter changing step of setting parasitic parameters of a wiring part within the mask region to zero, and a parasitic parameter extraction step of extracting parasitic parameters of either the total layout or a specific part of the layout. The parasitic parameter changing step includes a virtual wiring layer generation step of generating a virtual wiring layer corresponding to the actual wiring layer of the semiconductor device, a parasitic parameter definition step of defining the parasitic parameters of the virtual wiring layer as zero, and a wiring layer conversion step of converting the wiring part within the mask region of the wiring of the actual wiring layer, to the wiring part of the virtual wiring layer.

Abstract: A computer-implemented method may include defining an input bus signal in a graphical block diagram model by associating the input bus signal with a first group of signals, at least two of the first group of signals having a different data type; defining an output bus signal in the graphical block diagram model by associating the second bus signal with a second group of signals, each of the second group of signals corresponding to one of the first group of signals; defining an input to a non-virtual operation block in the graphical block diagram model as the input bus signal; defining an output to the non-virtual operation block in the graphical block diagram as the output bus signal; and simulating an operation performed on the input bus signal by the non-virtual operation block, the operation being performed on each of the first group of signals and output to each of the second group of signals.

Abstract: A computational methodology that improves the accuracy of model parameters in a compact model uses methods and algorithms to self-consistently match independently developed base and stress models by re-fitting the stress model to the data set that generates the base model. The re-fitting algorithm removes any discrepancy between the base model and the stress model as the stress model is applied to the data set obtained from a dimension-scaling macro. Stress offsets for dimension-scaling macro devices are calculated to fit the measured values of the model parameters for the same devices. The process of fitting the model parameters to the data set from the dimension-scaling macro calculates constant, linear, and quadratic coefficients for the model parameters, which are employed to increase the accuracy of the model parameters and of the compact model used in circuit simulations and optimization.

Abstract: A temperature-based clock frequency controller is implemented in an integrated circuit such as a microprocessor. The temperature-based clock frequency controller includes a register to store a threshold temperature value, a thermal sensor, and clock adjustment logic to decrease a clock frequency in response to the thermal sensor indicating that the threshold temperature value has been exceeded. In a microprocessor implementation, the microprocessor contains a plurality of thermal sensors each placed in one of a plurality of different locations across the integrated circuit and an averaging mechanism to calculate an average temperature from the plurality of thermal sensors. Threshold adjustment logic increases the threshold temperature value to a new threshold temperature value in response to the thermal sensor indicating that the threshold temperature value has been exceeded. Threshold adjustment logic further lowers the new threshold temperature to detect decreases in temperature.

Abstract: In one embodiment of the invention, a method of simulating a circuit is disclosed including simulating an analog component of the circuit over a first simulation time period with a first envelope simulation; adaptively switching from simulating the analog component with the first envelope simulation to simulating the analog component with a transient simulation over a second simulation time period; and adaptively switching from simulating the analog component with the transient simulation to simulating the analog component with a second envelope simulation over a third simulation time period. The adaptive switching from the first envelope simulation to the transient simulation may be in response to the envelope simulation accuracy falling below a predetermined level of accuracy in comparison with a transient simulation or in response to the second simulation time period including expected digital transitions where one or more digital events may occur to change the analog input signals to the analog component.

Abstract: Various port reduction methods are employed to reduce the number of port definitions in a simulation file. A ground port reduction method is first employed to reduce certain power supply reference connections to an absolute ground reference for the circuit model. Next, all commonly defined port definitions are combined into a single port definition. Finally, a current analysis is used to further reduce the number of port definitions in the simulation file by removing the current return ports from the simulation file.

Abstract: Device, method and system for displaying data of a machine control system. Status data for at least one element of the system, which represent at least one physical state variable, are received. The status data, which are received for the element, are represented in a circuit diagram which displays, at least for the element, the electrical/physical connection of the element in the system.

Abstract: A method (100) is disclosed for determining the behaviour of an integrated circuit comprising a plurality of resources and being configured to execute a plurality of operations that each require temporary allocation and deallocation of at least a subset of the plurality of resources during said execution. The method comprises the steps of monitoring (130) the execution of at least some of the plurality of operations during an execution run of the IC, capturing (140) events indicating the (de)allocation of resources during said execution, capturing events (150) indicating an operational relationship between allocated resources during said execution, assigning (140, 150) a time stamp to each event; and making (160) the captured events available for visualization. This facilitates the visualization of events that are interrelated in terms of the operation to which they are assigned at a given time instant.

Abstract: A cache replacement system for extending the debugging capabilities of accelerated simulation by enabling enhanced cache data and state checking is provided. The system includes a Cell Broadband Engine Architecture (CBEA) compliant system implementing Replacement Management Tables in an accelerated simulation environment. The RMTs control cache replacement and allow the software to direct entries with specific address ranges at a particular subset of the cache. The RMTs further allow for locking data in the cache and are utilized to prevent overwriting data in the cache by directing data that is known to be used only once at a particular set. Using the locking mechanism in an accelerated simulation environment, a user is able to run code sets, which, when the microprocessor system being tested is correctly designed, generates identical and verifiable data and cache states in each of the different sets of the cache.

Abstract: Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. The electrical behavior of the ferroelectric capacitor is evaluated by evaluating the polarization of each of the domains, as weighted by the weighting function. A time-dependent factor can be included in the polarization expression evaluated for each domain, to include the effect of relaxation. The effects of longer-term mechanisms, such as imprint, can be modeled by deriving a probability distribution function for the domains after an accelerated stress.

Abstract: A simulator comprising: a simulation executing unit to execute a simulation of circuit description data in which a circuit is described in a description language; a bit width monitor to monitor whether a bit width of a simulation result of an operation described in the circuit description data overflows from a bit width of an operation result assignment target variable described in the circuit description, while the simulation executing unit is executing the simulation; and an overflow avoiding unit to dynamically extend a bit width of the operation result assignment target variable that stores the simulation result, when the bit width monitor detects an occurrence of an overflow.

Abstract: A platform for simulating a chip includes a component module, a configuration module and a top module. The component module is utilized for storing a plurality of component models and information related to the plurality of component models. The configuration module is utilized for generating a configuration result according to the component model needed by the chip. The top module is coupled to the component module and the configuration module, for reading information related to the component model from the component module according to the configuration result, so as to simulate the chip.

Abstract: Some demonstrative embodiments of the invention may include, for example, devices, systems and methods of performing functional verification of a hardware design. In some demonstrative embodiments, a test generator may include a transaction generator to automatically generate a plurality of manipulated transactions by manipulating one or more test case transactions resulting from a constraint-satisfaction-problem.

Abstract: A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.

Abstract: A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions.

Abstract: Disclosed are improved methods, systems, and computer program products for lithographic simulation of an electronic circuit design.

Abstract: A peak current modeling method and system for modeling peak current demand of an integrated circuit (IC) block such as, e.g., a compilable memory instance. A current demand curve associated with the IC for a particular IC block event is obtained via simulation, for example. A defined time region associated with the particular IC block event is divided into multiple time segments, whereupon at least a first current value and a second current value for each time segment is obtained based on the current demand curve. Thereafter, the current demand curve is approximated, on a segment-by-segment basis, using a select approximate waveform depending on a relationship between the first and second current values.

Abstract: Systems and methods of performing co-simulation of a partitioned circuit design using multiple programmable logic devices (PLDs) coupled together to form a boundary scan chain. A host computer is coupled to the scan chain via a programming cable. Resident on the host computer are run-time co-simulation blocks corresponding to blocks from the circuit design, where each block is designated to run on one of the PLDs in the scan chain; a programming cable device driver interfacing with the programming cable; and a proxy component. The proxy component is coupled to all of the run-time co-simulation blocks and the programming cable device driver. Each co-simulation block includes a unique pattern identifier, which is also present in the associated PLD. Using this pattern identifier, data and commands targeted to a specific PLD can be extracted from the scan chain, while ignoring data and commands targeted to other PLDs in the scan chain.

Abstract: There are provided a modeling circuit of a high-frequency device capable of providing a more accurate modeling circuit having a higher-order resonance by dividedly modeling an overlap zone and a non-overlap zone of the high-frequency device, and a modeling method thereof.

Abstract: A method for designing a semiconductor device circuit comprising a electrostatic discharge (ESD) protection circuit can include device simulations using at least one, for example two or more ESD models, and designing device features such that they are resilient to damage from the two or more ESD testing models.

Abstract: Method for simulation of an electrical circuit by synthesis of a physical model, using digital wave structures including the following steps: within the framework of digital wave structure, consider a serial and parallel adapter block with at least three ports of which one adapted; represent said electrical circuit connecting the elements together by means of a plurality of said adapter blocks; connect each adapter block to the adapted port of the previous adapter block; consider the plurality of said adapter blocks as nodes of a binary tree and said elements of said electrical circuit as leaves of said binary tree; apply an element of the aforesaid electrical circuit to the adapted port of the root node; consider, for each port, an incident wave and a reflected wave; starting from the lower leaves of the tree and moving towards the root, calculate each reflected wave; assess the reflected wave of the element connected to the adapted port of the root; starting from the root and moving towards the lower leaves

Abstract: Systems and media for reconstructing data from simulation models are disclosed. Embodiments may include a media containing instructions for accessing an alias from an alias file. The media may include instructions for searching for a net name and, if the net name is not found, searching an alias index file for an alias index entry associated with the net name, the alias index entry having a net name and an associated position. The instructions may also include, if the net name entry is found, instructions for accessing from an alias file an alias associated with the net name. A further embodiment may include instructions for receiving a net name and a position of an alias in the alias file, creating an alias index entry for the alias having a net name and the position of the alias, and storing the created alias index entry in the alias index file.

Abstract: A method and system for providing a block for use in a block diagram in a graphical modeling environment which is capable of outputting information regarding the dynamic state of the block.

Abstract: A method of obtaining a resolution-based proof of unsatisfiability using a SAT procedure for a hybrid Boolean constraint problem comprising representing constraints as a combination of clauses and interconnected gates. The proof is obtained as a combination of clauses, circuit gates and gate connectivity constraints sufficient for unsatisfiability.

Abstract: The simulation information creating part 111 generates random numbers corresponding to the correlation coefficient data between the simulation model parameters, and also creates the simulation model library having correlated model parameters with variations, and the simulation net list for the objective characteristic, by Monte Carlo method using the typical simulation model library, the standard deviations for the plural simulation model parameters and the simulation net list for the typical objective characteristic. The simulation part 112 obtains samples having the objective characteristics with variations. The yield estimation part 120, estimates the yields by determining whether the samples satisfy the predetermined specification or not (Pass or Fail), wherein by repeating the determination by making the simulations again only for the samples on which the filter having the function of learning the boundary for decision of Pass or Fail did not determine as Pass.

Abstract: A method of resetting a programmable logic device (PLD) for use with hardware co-simulation can include loading a full bitstream into the PLD. The full bitstream can program the PLD with a circuit design to be used with a first simulation. The method further can include loading a partial bitstream into the PLD thereby resetting at least one component of the circuit design that does not have a reset function such that the circuit design is initialized for use in a subsequent simulation.

Abstract: A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

Abstract: A method, apparatus and computer-readable medium for conjunctive binary decision diagram building and variable quantification using case-splitting are presented. A BDD building program builds a BDD for at least one node in a netlist graph representation of a circuit design. One or more variables are selected for case-splitting. The variable is set to a constant logical value and then the other. A BDD is built for each case. The program determines whether the variable is scheduled to be quantified out. If so, the program combines the BDDs for each case according to whether the quantification is existential or universal. If the variable is not scheduled to be quantified, the program combines the BDDs for each case so that the variable is introduced back into the resulting BDD, which has a reduced number of peak live nodes.

Abstract: Testing a model of a logic circuit model. The testing includes generating valid random input stimulus sequences for a logic circuit model. Enumerating critical resource requirements, enumerating critical resource availabilities does this, and selecting of stimulus sequences and determining legal times for execution of said stimulus sequences based on resource availability. This includes generating a plurality of possible combinations of input stimulus sequences and generating an array representation of critical resource requirements. These are used to generate an array representation of critical resources availabilities.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: An equivalent circuit of an inductor is provided with a five wire structure. A first wire has a first resistor, an inductor, and a third resistor connected in series. A second wire is connected in parallel with the first wire and has a second resistor. A third wire is connected in parallel with the first and second wires and has a third capacitor. A fourth wire is serially connected to a first common node of the first, second, and third wires, and has a first capacitor connected between the first common node and a first sub capacitor and a first sub resistor connected in parallel. A fifth wire is serially connected to a second common node of the first, second, and third wires, and has a second capacitor connected between the second common node and a second sub capacitor and a second sub resistor connected in parallel.