Circuit Simulation Patents (Class 703/14)
  • Publication number: 20100332202
    Abstract: A new method for simulation of general electrical circuits on parallel computing platforms is disclosed. Parallel simulation of general time-domain circuits that are represented by nonlinear/linear differential algebraic equations is accomplished by partitioning them into smaller subcircuits via a novel combination of the companion form representation of the given circuit and an efficient form of node splitting, during Newton Raphson iterations, at any time point. The new invention formulates the interface vectors between partitions, through purely binary vectors, leading to a high degree of parallelism, scalability and reduced computational and communication costs for synchronizing the solutions between various partitions. Parallel platforms considered can be diverse such as (including but not restricted to) multicore CPUs, distributed systems of computers.
    Type: Application
    Filed: June 30, 2010
    Publication date: December 30, 2010
    Applicant: OMNIZ DESIGN AUTOMATION CORPORATION
    Inventors: Michel Nakhla, Ramachandra Achar, Douglas Paul, Natalie Nakhla
  • Publication number: 20100332206
    Abstract: A method is provided for simulating leakage distribution of integrated circuit design. The method analyzes a layout of the integrated circuit design to understand the groups of dimensions of the transistors and capacitors of the layout, and then simulates a leakage distribution of the layout resulted from possible fabrication process variations. Therefore, designer can know the leakage distribution of the integrated circuit design before the integrated circuit design is actually fabricated, and modify the layout if a leakage failure happens to the layout.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 30, 2010
    Inventor: Iyun Leu
  • Publication number: 20100332208
    Abstract: Predictive Split Lot Emulator, and methods simulating integrated circuit performance variations, before IC fabrication. The emulator receives a split lot parameter, maps the split lot parameter onto an IC element model, and transforms the IC element into a predictive IC element model. The emulator uses the predictive model to determine simulated performance characteristic of the IC element model. Also, a predictive split lot analyzer, a CAD simulation system, and a PDK including the emulator. IC simulating methods include choosing a Split Condition from a Split Table; a Predictive Split Lot Emulator receiving the Condition, determining a Split Parameter Condition Perturbation, mapping the Perturbation into a Model Parameter Perturbation for an IC element, and storing the Model Perturbation for an IC element into a Model Parameter Perturbation Library. The Perturbation Library emulates IC element performance characteristic in a Split Condition.
    Type: Application
    Filed: June 28, 2010
    Publication date: December 30, 2010
    Inventors: James Victory, Juan D. Cordovez
  • Publication number: 20100332193
    Abstract: A method for modeling bond wires in an IC package for predicting noise effects generated by electromagnetic coupling in complex bond wire configurations. A look-up table of equivalent LC circuit models for the bond wires is generated that accurately predicts the effects of the bond wire circuitry of a signal transmission system. Switch and mirror techniques are applied to reduce the bond wire configurations necessary to simulate.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 30, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Haitian Hu, Timothy W. Budell, Charles S. Chiu, Eric Tremble
  • Patent number: 7860700
    Abstract: The exemplary embodiments provide a computer implemented method, apparatus, and computer usable program code for calculating the expected behavior of a group of hardware verification test cases. Batch simulation parameters are configured. A test case is submitted for evaluation. Historical performance data for test cases associated with the submitted test case is gathered. A set of performance statistics for the submitted test case is generated based on the historical performance data and the configured batch simulation parameters. A set of values for the submitted test is generated based on the generated performance statistics for the submitted test case and the historical performance data. The generated set of values and the generated set of performance statistics for the submitted test case are displayed to a user.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: December 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Michael L. Behm, Steven R. Farago, Bryan R. Hunt, Stephen McCants
  • Patent number: 7861200
    Abstract: A method of characterizing a device under test (DUT) includes determining a goal function associated with a setup and hold time for the DUT. A minimum value for the goal function is determined by iteratively adjusting setup and hold times for input data to the DUT, and determining whether the DUT performs according to specifications. The minimum goal function value will reflect minimum setup and hold time values based on weights associated with the goal function. This allows the minimum setup and hold times for the DUT to be characterized with a small number of binary searches, improving the speed of the characterization process.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: December 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yifeng Yang, Yun Zhang, Yibin Xia, David J. Chapman
  • Patent number: 7860701
    Abstract: A method for predicting functionality of an integrated circuit segment to be lithographically printed on a wafer. Initially there is provided a two-dimensional design of an integrated circuit, including an integrated circuit segment having critical width, and a two-dimensional printed image of the critical width integrated circuit segment is simulated. The method then includes determining a ratio of perimeters or areas of the designed critical width integrated circuit segment to the simulated printed critical width integrated circuit segment, and predicting functionality of the critical width integrated circuit segment after printing based on the ratio of perimeters or areas.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: December 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ioana Graur, Kafai Lai, Rama N. Singh
  • Patent number: 7860703
    Abstract: A timing-control method of a hardware-simulating program can be applied to a software platform for facilitating control program development. The hardware-simulating program can be recorded in any suitable recording medium and defines therein a plurality of simulating elements which are automatically synchronized at intervals by setting specified time points as aligning points. The specified time points are set with adjustable intervals. By adjusting an interval between adjacent specified time points, the simulating speed between the adjacent specified time points can be changed to comply with practical requirements.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: December 28, 2010
    Assignee: Iadea Corporation
    Inventors: John C. Wang, Mu-Yi Chen, Yung-Chieh Lin
  • Publication number: 20100324879
    Abstract: A circuit simulation apparatus acquires wiring connection information indicating connection data in an electric circuit, selects a component constituting the circuit based on the wiring connection information, performs a setting of replacing the selected component with each resistor having different resistance values, generates at least one of netlists using the acquired wiring connection information and at least one of the set resistance values, calculates a value of an equivalent power source and a value of an internal resistance thereof for a part of the circuit using the acquired wiring connection information and at least one of the generated netlists, and calculates a resistance value of the selected component and a power consumption for the resistance value using the value of the equivalent power source and the value of the internal resistance.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 23, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Eiji Yajima, Shunko Kaneko, Atsushi Asayama, Ryo Yamazaki
  • Publication number: 20100324880
    Abstract: Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation.
    Type: Application
    Filed: August 30, 2010
    Publication date: December 23, 2010
    Inventors: Gunnar Braun, Olaf Zorres, Achim Nohl, Andreas Hoffmann
  • Publication number: 20100324878
    Abstract: Disclosed are a method, a system, and a computer program product for implementing hotspot detection, repair, and optimization of an electronic circuit design, which, in some embodiments, defines, identifies criteria for hotspots/metrics or optimization objective function; performs the initial hotspot or metric prediction; identifies correction candidate(s); applies a correction candidate to the electronic circuit design; and determines whether the outcome of applying the correction candidate is acceptable. The method or the system identifies custom correction candidate(s) or custom command(s) and identifies one or more hints for the predicted hotspots or metrics; provides a single architecture to use a first model for hotspot identification/correction and a second model for design check; and provides the capability to apply a correction for a hotspot or metric, evaluate the effectiveness of the correction on the fly, and revert any changes made to the electronic circuit design by the correction.
    Type: Application
    Filed: June 23, 2009
    Publication date: December 23, 2010
    Applicant: Cadence Design Systems, Inc.
    Inventors: Brian LEE, Srinivas DODDI, Ron PYKE, Taber SMITH, Emmanuel DREGE
  • Patent number: 7856346
    Abstract: A test system for data processing circuit design emulates multiple bus masters and provides an arbitration mechanism for coordinating arbitration between those bus masters in the design emulation. The shared bus being tested may be a multi-layer bus and one or more of the bus masters being emulated or bus slaves being emulated may be cut-down emulations modelling the bus interaction itself or full emulations of the intended bus master circuit or bus slave circuit including its operational data processing.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: December 21, 2010
    Assignee: ARM Limited
    Inventors: Andrew Mark Nightingale, Timothy Charles Mace
  • Patent number: 7856344
    Abstract: A method for transforming paths in a logical model to their physical equivalent in a physical model is provided. A logical model is retrieved. All entities in the logical model are mapped. All paths connecting the entities of the logical model are mapped. Tables are created that correspond to the entities in the logical model for traceability. Columns are created that correspond to attributes of the paths in the logical model for traceability. A reduced logical model is created by reducing overlapping paths in the logical model. Virtual logic paths are created where an entity is rolled up, is rolled down, or participates in a many-to-many relationship in the reduced logical model. The reduced logical model is transformed into a physical model.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: December 21, 2010
    Assignee: International Business Machines Corporation
    Inventors: John Matthews, Pat Meehan
  • Publication number: 20100318340
    Abstract: A method of generating a model of a leadframe IC package, a leadframe modeler and an IC design system are disclosed. In one embodiment the method includes: (1) adding connectivity information to a geometric representation of a leadframe, wherein the connectivity information represents electrical connections between the IC die and leads of the leadframe and (2) formatting the leads to represent BGA point of contacts for the IC die.
    Type: Application
    Filed: June 16, 2009
    Publication date: December 16, 2010
    Applicant: LSI Corporation
    Inventors: Donald E. Hawk, JR., Stephen M. King, Jeffrey M. Klemovage, John J. Krantz, Allen S. Lim, Ashley Rebelo, Richard J. Sergi
  • Publication number: 20100318956
    Abstract: A method of physical design for integrated circuit (IC) chip fabrication, physical design system and program product therefor. A design shape is fragmented into segments for Optical Proximity Correction (OPC) and a harmonic mean of the segments is determined. Electrical intent is determined for the shape and a harmonic mean is determined for the segments. Segments may be moved based on a effect on the harmonic mean from moving the segments, measured using a harmonic mean cost function. Finally segmented shapes are passed to OPC.
    Type: Application
    Filed: June 11, 2009
    Publication date: December 16, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Geng Han, Fook-Luen Heng, Jin Fuw Lee, Chao Yi Tien, Rama N. Singh
  • Publication number: 20100318342
    Abstract: A method includes causing a circuit simulator to perform a circuit simulation using circuit data stored in a storage, the circuit data containing a module to be modeled and a circuit for making a change to a clock to be inputted into the module and clock setting data stored in a storage, the clock setting data being intended to, at a predetermined timing, make a change to the clock to be inputted into the module, and storing a result of the circuit simulation in a simulation result data storage; and generating a hidden markov model about input and output signals of the module from values and times of the signals in accordance with a predetermined algorithm, the values and times being contained in the circuit simulation result stored in the simulation result data storage, and storing data about the model in a hidden markov model data storage.
    Type: Application
    Filed: June 9, 2010
    Publication date: December 16, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Yutaka TAMIYA
  • Publication number: 20100318341
    Abstract: A non-transitory computer-readable recording medium stores therein a program that causes a processor to execute inputting a driving capability value, a lumped-constant capacitance value, and an input capacitance value included in the lumped-constant capacitance value, respectively defined in a circuit model, and further inputting a first delay time of the circuit model, based on the driving capability value and the lumped-constant capacitance value; setting in the circuit model, the driving capability value, the lumped-constant capacitance value, and the input capacitance value; acquiring a second delay time of the circuit model, by providing to a simulator, the circuit model having values set therein; calculating a relative evaluation value for the first delay time and the second delay time; and storing to a storage apparatus and as a delay time correcting coefficient, the relative evaluation value correlated with the driving capability value, the lumped-constant capacitance value, and the input capacitance
    Type: Application
    Filed: June 3, 2010
    Publication date: December 16, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Mitsuru ONODERA
  • Patent number: 7853909
    Abstract: An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: December 14, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Susumu Kobayashi, Morihisa Hirata, Mototsugu Okushima, Tomohiro Kitayama, Tetsuya Katou
  • Patent number: 7853442
    Abstract: There are provided a printed circuit board design instruction support method between a circuit design and a printed circuit board design, a printed circuit board design instruction support device between a circuit design and a printed circuit board design, a Web system, a program, an a computer-readable recording medium which improve the work efficiency of the printed circuit board designing and the quality of the printed circuit board design. By selecting a circuit part to which the design rule is applied, a circuit program and a portion-to-be-checked on the printed circuit board are simultaneously displayed by cooperation between the circuit design system and the printed circuit board design system, thereby reducing the time and labor required for check.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: December 14, 2010
    Assignee: Zuken Inc.
    Inventors: Hiromichi Inaishi, Hiroyuki Tanaka, Keisuke Fukuoka, Masahiro Yamawaki, Asako Ajimine
  • Patent number: 7853443
    Abstract: A transient simulation system, methods and program product that implement an adaptive piecewise constant (PWC) model are disclosed. The invention evaluates an error criteria to determine a maximum allowable change in one of a current and a voltage; and simulates the transient conditions by implementing an adaptive step in the PWC model according to the maximum allowable change. The invention allows dynamic or static adaptation of a PWC model according to an error criteria.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: December 14, 2010
    Assignee: International Business Machines Corporation
    Inventor: Jeffrey G. Hemmett
  • Patent number: 7853908
    Abstract: An Algorithmic Reactive Testbench (ART) system is provided for the simulation/verification of an analog integrated circuit design. The ART system is a high level simulation/verification environment with a user program in which one or more analog testbenches are instantiated and operated as prescribed in an algorithmic reactive testbench program, and the properties of the unit testbenches (test objects) can be influenced by prior analysis of themselves or other tests. The test object may also contain various properties including information reflecting the status of the test object. The modification of a property of a test object is an act of communication in the ART system from the algorithmic reactive testbench program to the test object.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: December 14, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Jang Dae Kim, Steve A. Martinez, Satya N. Mishra, Alan P. Bucholz, Hui X. Li, Rajesh R. Berigei
  • Patent number: 7853915
    Abstract: A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with route-based delays and parasitics for the selected nets. At this point, synthesis can be run using actual route-based delays and parasitics for the selected nets, with their routes being updated incrementally as needed. In one embodiment, the nets can be re-ranked after synthesis. Finally, these routes can be preserved across the subsequent global routing of the remaining nets.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: December 14, 2010
    Assignee: Synopsys, Inc.
    Inventors: Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, Jing C. Lin, Mahesh A. Iyer
  • Patent number: 7853903
    Abstract: An improved method and mechanism for verification of an electrical circuit design is provided. The method and system simultaneously provides the coverage advantage of formal verification with the scaling efficiencies of simulation. In one approach, the method and system generates an intelligent set of test vectors off a resolution proof. The intelligent set of test vectors can be used to simulate the circuit design for complete coverage without having to test the entire set of possible variable assignments for the CNF formula corresponding to the circuit design.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: December 14, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Evgueni Goldberg, Felice Balarin
  • Publication number: 20100312539
    Abstract: An electromagnetic field simulation apparatus disclosed herein replaces a predetermined region in printed circuit board CAD data to be subjected to electromagnetic field simulation with measurement data measured by a near-field measurement device and generates new printed circuit board CAD data. Subsequently, regarding a measurement data portion in the new printed circuit board CAD data generated by the data generating unit, the electromagnetic field simulation apparatus generates analysis model data by setting, as a wave source, an electric field or a magnetic field measured by the near-field measurement device. Then, the electromagnetic field simulation apparatus executes electromagnetic field simulation with respect to the analysis model data having a set wave source.
    Type: Application
    Filed: May 26, 2010
    Publication date: December 9, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Takashi Yamagajo, Hitoshi Yokemura
  • Publication number: 20100312374
    Abstract: System and method for implementing a VM APC platform are described. In one embodiment, the VM APC system comprises a process tool for processing a plurality of wafers, a metrology tool for measuring a sample wafer of the plurality of wafers and generating actual metrology data therefor, and a VM model for predicting metrology data for each of the plurality of wafers. The actual metrology data is received from the metrology tool and used to update the VM model. Key variables of the virtual metrology model are updated only in response to a determination that the VM model is inaccurate and parameters of the VM model are updated responsive to receipt of the actual metrology data for the sample wafer of the plurality of wafers.
    Type: Application
    Filed: June 5, 2009
    Publication date: December 9, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Feng Tsai, Andy Tsen, Jin-Ning Sung
  • Patent number: 7849362
    Abstract: A method and system comprises creating a test case that is dependent upon known sequences and executing the test case on an originating processor until it reaches a known point. The method further includes executing the test case on a different processor to perform an action and informing the originating processor that the action was taken. The action is verified as being occurred with the originating processor.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: December 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Devins, David W. Milton, Pascal A. Nsame
  • Patent number: 7844423
    Abstract: Channel access delays and reception uncertainty are modeled as protocol-independent generic processes that are optimized for improved simulation performance. The generic process components are designed such that each different protocol can be modeled using an arrangement of these components that is specific to the protocol. In this way, speed and/or accuracy improvements to the generic process components are reflected in each of such protocol models. If an accurate analytic model is not available for the generic process component, a prediction engine, such as a neural network, is preferably used. The prediction engine is trained using the existing detailed models of network devices. Once trained, the prediction engine is used to model the generic process, and the protocol model that includes the generic component is used in lieu of the detailed models, thereby saving substantial processing time.
    Type: Grant
    Filed: October 20, 2007
    Date of Patent: November 30, 2010
    Assignee: OPNET Technologies, Inc
    Inventors: Karthikeyan Chandrashekar, Paul M. Janes, Alain J. Cohen, Pradeep Singh, David James Boyd, Ibrahim Utku Moral
  • Patent number: 7844437
    Abstract: A system and method for matching the hardware resource requirements of a user module with the available resources of an underlying integrated circuit is shown. Databases are utilized to describe the requirements of a particular user module and the resources of a particular chip. A graphical interface is utilized to relate a selected user module with potentially appropriate resources, and to illustrate alternative placements. This graphical interface utilizes highlights of both the module and the associated resource in patterns, grayscales, or colors to graphically illustrate the relationship between the module and the associated resource.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: November 30, 2010
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kenneth Y. Ogami, Frederick R. Hood, III
  • Patent number: 7844438
    Abstract: A method to analyze and correct dynamic power grid variations in an IC includes performing a dynamic power grid analysis of the circuit, identifying an excessive dynamic power grid voltage fluctuation from the analysis, and modifying the circuit to reduce the excessive dynamic power grid fluctuation.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: November 30, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Nishath Verghese, Kenneth Tseng
  • Patent number: 7844435
    Abstract: An integrated circuit chip has new Frequency dependent RLC extraction and modeling providing on chip integrity and noise verification and the extraction and modeling employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: November 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Bowen, Alina Deutsch, Gerard V. Kopcsay, Byron L. Krauter, Barry J. Rubin, Howard H. Smith, David J. Widiger
  • Patent number: 7844927
    Abstract: According to one exemplary embodiment, a method for producing a quality assured semiconductor device model when at least one critical parameter of a semiconductor device process is upgraded includes verifying the quality assured semiconductor device model for consistency against measured data or projected targets. The method further includes verifying the quality assured semiconductor device model for accuracy and consistency when one of a number of critical parameters is varied. The method further includes verifying consistency of the quality assured semiconductor device model against an old semiconductor device model. The method further includes verifying the quality assured semiconductor device model over a range of each of a number of semiconductor device dependencies. The method further includes verifying the quality assured semiconductor device model for digital circuit operation. The method further includes verifying the quality assured semiconductor device model for analog circuit operation.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: November 30, 2010
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Zhi-Yuan Wu, Ali Icel, Judy X. An, Ciby T. Thuruthiyil
  • Publication number: 20100299115
    Abstract: Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. To create a model of a small ferroelectric capacitor, a Poisson probability distribution is assigned to each of an array of gridcells defining the probability distribution function of positive and negative coercive voltages, and a number of domains assigned to each gridcell is randomly selected according to that Poisson distribution and an expected number of domains in the modeled capacitor for that gridcell, based on the area of the modeled capacitor.
    Type: Application
    Filed: September 29, 2009
    Publication date: November 25, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Borna Obradovic, Keith R. Green, Scott R. Summerfelt
  • Publication number: 20100292977
    Abstract: A computer-readable recording medium stores therein a program causing a computer that accesses a simulator to execute receiving a measured yield distribution that expresses an actually measured yield distribution concerning leak current of a circuit-under-design, and model data for leak current of a cell of the circuit-under-design; providing the simulator with the model data and values for a normal distribution concerning variation components of the leak current of the cell; acquiring the leak current of the circuit-under-design; calculating, based on the acquired leak current, an estimated yield distribution concerning the leak current of the circuit-under-design; calculating values for the normal distribution that minimize error between the measured yield distribution and the estimated yield distribution; setting an initial value to the normal distribution and the calculated values for the normal distribution to the normal distribution; and outputting the estimated yield distribution that is based on the l
    Type: Application
    Filed: April 20, 2010
    Publication date: November 18, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Katsumi HOMMA
  • Patent number: 7835898
    Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: November 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Daniel Geist, Mark Ginzburg, Yoad Lustig, Ishai Rabinovitz, Ohad Shacham, Rachel Tzoref
  • Patent number: 7836416
    Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs. Moreover, various embodiments related to HDL code coverage are described.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: November 16, 2010
    Assignee: Synopsys, Inc.
    Inventors: Nils Endric Schubert, John Mark Beardslee, Gernot Heinrich Koch, Ewald John Detjens
  • Patent number: 7835896
    Abstract: A new system for simulation of electrical circuits and devices over a network is disclosed. The system consists of at least a client computer, a server computer, a network that connects them (including intermediate proxy servers and routers) and software methods. New software methods are disclosed that combine client-submitted data from the internet with template data, simulate the combined data using a simulator such as SPICE and create display and other data for transport to and display on the client computer. Additional methods are disclosed relating to circuit synthesis prior to simulation, access control, limiting resource use and abuse, expiration of temporary files and identifiers and usage logging.
    Type: Grant
    Filed: April 6, 1999
    Date of Patent: November 16, 2010
    Assignee: Rode Consulting, Inc.
    Inventor: Christian Stig Rode
  • Patent number: 7835890
    Abstract: The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: November 16, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Lifeng Wu, Zhihong Liu, Alvin I. Chen, Jeong Y. Choi, Bruce W. McGaughy
  • Patent number: 7835897
    Abstract: A system and method is described for connecting a logic circuit simulation to a hardware peripheral that includes a computer running software for communicating data to and from the hardware peripheral. The software transmits the data received from the hardware peripheral to the device being simulated by the logic circuit simulation. The computer also transmits the data received from the device being simulated by the electronic circuit simulation to the hardware peripheral. This allows the user to test the device being simulated using real hardware for input and output instead of simulated hardware.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: November 16, 2010
    Inventor: Robert Marc Zeidman
  • Patent number: 7836419
    Abstract: Method and system for partitioning integrated circuits are disclosed. The method includes receiving a netlist representation of the circuit comprising circuit components, partitioning the circuit to form one or more circuit partitions according to a predefined partitioning method, where each circuit partition includes one or more circuit components. The method further includes, for each circuit partition, identifying substantial correlations between the circuit partition and one or more other circuit partitions to form a spanning tree, where the spanning tree connects the circuit partition to the one or more other circuit partitions via a graph, and merging the circuit partition and the one or more other circuit partitions in the spanning tree to form a new circuit partition.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: November 16, 2010
    Assignee: Cadence Design Systems, Inc
    Inventors: Bruce W. McGaughy, Jun Kong
  • Publication number: 20100286975
    Abstract: The present invention relates to a method for finding design weakness and potential field failure of a PCB assembly which includes components, comprising the steps of: (a) creating a model of the PCB assembly by which natural frequencies and mode shapes of the PCB assembly can be determined; (b) performing a natural frequencies simulation for determining natural frequencies and mode shapes of the PCB assembly; and (c) analyzing said determined natural frequencies and mode shapes and identifying local dominant oscillations of components, components identified as having a local dominant oscillation in at least one of said determined mode shapes are identified as components having a relatively high potential of field failure.
    Type: Application
    Filed: April 5, 2010
    Publication date: November 11, 2010
    Inventor: Abraham Varon-Weinryb
  • Publication number: 20100286807
    Abstract: In a particular embodiment, a first digital function module is created that represents a first analog circuit and a second digital function module is created that represents a second analog circuit. A first value representing a first analog signal is transmitted from the first digital function module to the second digital function module while concurrently or substantially currently, the second digital function module transmits a second value representing a second analog signal to the first digital function module. In a particular embodiment, the first digital function module is a current signal related to an output of the first analog circuit and the second analog signal from the second digital function module is a voltage signal related to an output of the second analog circuit. The values may be transmitted along a bidirectional analog data bus capable of communicating real floating point numbers.
    Type: Application
    Filed: May 8, 2009
    Publication date: November 11, 2010
    Applicant: QUALCOMM INCORPORATED
    Inventor: Jesse Eugene Chen
  • Publication number: 20100286974
    Abstract: A method for estimating power consumption of a design block of an integrated circuit includes obtaining power consumption data from designs of older-generation microprocessors, selecting a set of power consumption parameters, applying a curve-fitting technique on the obtained power consumption data for the selected set of power consumption parameters, creating a new power consumption model based on the curve-fitting technique and one or more of the power consumption parameters, using the model at a register transfer level of a newer-generation microprocessor to represent estimates of register transfer level power consumption of the newer-generation microprocessor, and outputting the register transfer level power consumption estimates based on the model.
    Type: Application
    Filed: May 5, 2009
    Publication date: November 11, 2010
    Applicant: Sun Microsystems, Inc.
    Inventors: Krishnan Sundaresan, Pravin Chander Chandran
  • Patent number: 7827020
    Abstract: Disclosed is simulation of circuit behavior by running a central electronic core simulation in a high level simulator up to and including initial microload, creation of a post-IML (initial microcode load) state, and transferring the post-initial microcode state from the central electronic core simulation to the post-initial microcode load co-simulator.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: November 2, 2010
    Assignee: International Business Machines Corporation
    Inventor: Edward C. McCain
  • Patent number: 7827017
    Abstract: A system and method for performing circuit simulation is described. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. Mechanisms are provided that allow for viewing, measurement or other manipulation of signals at specific locations in a circuit design for simulation, such as parameters that include observation points which are implemented using probes. One approach to executing a measurement is via a controllable and flexible control statement, which in one embodiment is the “run” statement. Improved interfaces for viewing, controlling, and manipulating simulations and simulation results are also provided.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: November 2, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventor: Kenneth S. Kundert
  • Patent number: 7827517
    Abstract: A system for designing an integrated circuit is provided. The system includes a plurality of class databases having register information extracted from a register entry tool. A system integration tool is used to integrate the register information from each of the class databases into a system database. The system integration tool essentially consolidates the class databases and maintains a base address for the various components. A system application module includes a number of application tools, which may be referred to as generators. The application tools include, among other tools, a document generator tool, a hardware description language (HDL) generator, a hardware abstraction layer (HAL) generator, and a test framework. A method of designing a circuit is also provided.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: November 2, 2010
    Assignee: Altera Corporation
    Inventor: Kent Orthner
  • Patent number: 7827019
    Abstract: A passive macromodel for lossy, dispersive multiconductor transmission lines uses a multiplicative approximation of the matrix exponential known as the Lie product. The circuit implementation of the macromodel is a cascade of elementary cells, each cell being the combination of a pure delay element and a lumped circuit representing the transmission line losses. Compared with passive rational macromodeling, the Lie product macromodel is capable of efficiently simulating long, low-loss multiconductor transmission lines while preserving passivity. This result is combined with transmission line theory to derive a time-domain error criterion for the Lie product macromodel. This criterion is used to determine the minimum number of cells needed in the macromodel to assure that the magnitude of the time-domain error is less than a given engineering tolerance.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: November 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ibrahim M. Elfadel, Hao Ming Huang
  • Patent number: 7827018
    Abstract: A method and computer program for selecting circuit repairs using redundant elements with consideration of aging effects provides a mechanism for raising short-term and long-term performance of memory arrays beyond present levels/yields. Available redundant elements are used as replacements for selected elements in the array. The elements for replacement are selected by BOL (beginning-of-life) testing at a selected operating point that maximizes the end-of-life (EOL) yield distribution as among a set of operating points at which post-repair yield requirements are met at beginning-of-life (BOL). The selected operating point is therefore the “best” operating point to improve yield at EOL for a desired range of operating points or maximize the EOL operating range. For a given BOL repair operating point, the yield at EOL is computed. The operating point having the best yield at EOL is selected and testing is performed at that operating point to select repairs.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: November 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chad A. Adams, Rajiv V. Joshi, Rouwaida N. Kanj, Sani R. Nassif
  • Publication number: 20100274548
    Abstract: Clock approximate signals within an electronic design may be identified. Allowing the identified clock approximate signals to be conditionally ignored during a subsequent simulation of the electronic design may provide for a significant increase in the efficiency of the simulation.
    Type: Application
    Filed: January 31, 2010
    Publication date: October 28, 2010
    Inventors: Du Nguyen, Anissa Mawer
  • Patent number: 7822590
    Abstract: A system and method for performing circuit simulation is described. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. Mechanisms are provided that allow for viewing, measurement or other manipulation of signals at specific locations in a circuit design for simulation, such as parameters that include observation points which are implemented using probes. One approach to executing a measurement is via a controllable and flexible control statement, which in one embodiment is the “run” statement. Improved interfaces for viewing, controlling, and manipulating simulations and simulation results are also provided.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: October 26, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventor: Kenneth S. Kundert
  • Patent number: 7822591
    Abstract: A logic circuit model conversion apparatus includes a first analysis unit which analyzes a model in which a logic circuit of a register transfer level has been coded and outputs simultaneous blocks and an analysis result, a creating unit which creates a common execution frequency group that is a set of codes whose execution frequency becomes common, based on the simultaneous blocks and analysis result, a second analysis unit which analyzes the common execution frequency group and creates a formula of a general term to derive a predetermined value of each register, a third analysis unit which analyzes a mutual relationship between the common execution frequency groups and derives an execution frequency of each common execution frequency group up to a predetermined time, and a deriving unit which derives a value of each of the registers at the predetermined time from the formula of the general term and execution frequency.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: October 26, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoshi Otsuki, Nobuhiro Nonogaki