Abstract: A logic circuit model conversion apparatus includes a first analysis unit which analyzes a model in which a logic circuit of a register transfer level has been coded and outputs simultaneous blocks and an analysis result, a creating unit which creates a common execution frequency group that is a set of codes whose execution frequency becomes common, based on the simultaneous blocks and analysis result, a second analysis unit which analyzes the common execution frequency group and creates a formula of a general term to derive a predetermined value of each register, a third analysis unit which analyzes a mutual relationship between the common execution frequency groups and derives an execution frequency of each common execution frequency group up to a predetermined time, and a deriving unit which derives a value of each of the registers at the predetermined time from the formula of the general term and execution frequency.

Abstract: An integrated circuit chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.

Abstract: A method, computer system and program product introduce adding a variable performance ranking parameter to a diagram of a circuit to drive implementation of modifications that are yield improving, performance boosting, or performance-neutral. The information is paired to accomplish a more complete design for manufacturability modification in the design of circuits implemented on chips. In this matter, both yield and chip performance are improved.

Abstract: A computer-aided design system and method are provided. The computer-aided design method reads PCB design data from a storage system, obtains a plurality of circuit signals from the PCB design data, and groups the differential signals into a plurality of differential signal pairs. The computer-aided design method further sets a signal design standard for each of the differential signal pairs according to the electrical characteristics of the differential signal pair, and compiles each of the signal design standards into an instruction set. In addition, the computer-aided design method generates a PCB design specification by integrating each of the instruction sets and the PCB design data, and stores the PCB design specification into the storage system.

Abstract: In a computer simulation of an analog device in a digital circuit, a piece-wise linear lookup table is used to determine the channel resistance of the transistors in the analog device, allowing the node voltages to take on non-digital values. The piece-wise linear lookup table contains a set of channel resistances corresponding respectively to gate-to-source voltages. The program uses multi-terminal binary decision graphs (MTBDDs) to represent non-digital resistances, capacitances and voltages in the circuit as a function of symbolic inputs. The program can analyze circuits containing more than two voltage sources by modeling voltage sources with voltage dividers between the maximum and minimum voltages in the circuit.

Abstract: A method for analyzing an electrical characteristic of wire segments configured as one or more power meshes in an integrated circuit (IC) core comprising the steps of (A) specifying design information corresponding to the power meshes, (B) specifying at least one type of analysis to be performed, where the analysis comprises (i) generating a file corresponding to the IC core in a format compatible with an electronic circuit simulator and (ii) calculating the electrical characteristic of the wire segments via the circuit simulator, and (C) displaying the calculated electrical characteristic.

Abstract: Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.

Abstract: A method of verifying a performance model of an integrated circuit is provided. The method comprises the following steps: obtaining statistical request numbers and corresponding latency values of memory access requests; developing functions of latency value based on the statistical request numbers and the corresponding latency values; bringing a random value to one of the functions to retrieve a latency value; and verifying the logic of the performance model using the latency value retrieved in the step above.

Abstract: According to a method of simulation data processing, a difference is determined between a simulated value of a characteristic for a simulated integrated circuit device and a corresponding empirical value of the characteristic for a fabricated integrated circuit device. A data structure containing a simulation model of the fabricated integrated circuit device is accessed, where the data structure includes a plurality of entries each accessed via a unique index and an index used to access the data structure is offset in accordance with the difference between the simulated value and the empirical value. Operation of the simulated integrated circuit device is then simulated utilizing a value obtained from one of the plurality of entries of the data structure. Results of the simulation are stored in a data storage medium.

Abstract: In accordance with one embodiment, a plurality of empirical measurements of a fabricated integrated circuit including a fabricated transistor having multiple terminals is received. The plurality of empirical measurements each include an empirical terminal current set and an empirical terminal voltage set for the terminals of the fabricated transistor. A mathematical simulation model of a simulated transistor is also received. Utilizing the mathematical simulation model, an intermediate data set is calculated by determining, for each of a plurality of different terminal voltage sets, a simulated terminal current set and a simulated terminal charge set. A modeling tool processes the intermediate data set to obtain a time domain simulation model of the fabricated transistor that, for each of the plurality of empirical measurements, provides a simulated terminal charge set. The time domain simulation model is stored in a computer-readable data storage medium.

Abstract: A method for simulating an integrated circuit having a plurality of clock control modules includes simulating the integrated circuit, and automatically receiving from each clock control model during simulation an indication of a simulated power state of the clock control model. Accordingly, the simulated power state of the portion of the integrated circuit model to be clocked by a clock control model can be monitored based on the indicator from the clock control model, rather than on a higher level analysis of the simulated input/output behavior of the integrated circuit model.

Abstract: A system and method for analyzing power glitch in circuits includes simulating a circuit to provide waveform responses at positions of interest in the circuit. Each waveform response is processed to determine glitch power by comparing optimal energy to actual energy for the waveform. The circuit is adjusted to reduce loss due to the glitch power.

Abstract: Methods of detecting unwanted logic in a configuration bitstream for a programmable logic device (PLD). The bitstream can be reversed engineered to generate a model of the design. The model is then tested for unwanted logic, e.g., logic inserted for the purpose of monitoring or interfering with the desired functionality of the design, by applying a test suite that exercises all desired functions for the design. If some of the logic nodes in the model are not exercised by the test suite, then the unexercised nodes might constitute unwanted logic and might have been inserted for malicious purposes. To reverse engineer the bitstream, a simulation model of the unprogrammed PLD can be used. Configuration bits from the bitstream can be inserted into the model of the unprogrammed PLD. The modified model can be simplified by propagating constants through the model in response to the values inserted into the model.

Abstract: A semiconductor circuit deterioration simulation method for a circuit including MOSFETs includes inserting a dynamic voltage source associated with a fluctuation in voltage/current characteristics into each gate terminal of a plurality of MOSFETs in series, calculating dynamic deterioration amounts of the plurality of MOSFETs by performing circuit simulation and calculating a dynamic deterioration amount, and repeating the above processing to perform the circuit deterioration simulation over the long term.

Abstract: IC chip design modeling using perimeter density to an electrical characteristic correlation is disclosed. In one embodiment, a method may include determining a perimeter density of conductive structure within each region of a plurality of regions of an integrated circuit (IC) chip design; correlating a measured electrical characteristic within a respective region of an IC chip that is based on the IC chip design to the perimeter density; and modeling the IC chip design based on the correlation.

Abstract: A virtual platform simulates behavior of a modular circuit based on a circuit design including both high-level and low-level models of circuit modules. A compiler that converts the high-level and low-level models into executable models prior to an initial simulation also generates a separate “replay engine” corresponding to each low-level module for use during subsequent replay simulations. During the initial simulation, the virtual platform simulates circuit behavior by concurrently executing the high-level and low-level executable models and recording data representing behavior of output signals of the low-level design modules modeled by the executable models. To speed up subsequent replays of the simulation, the virtual platform executes one or more of the replay engines in lieu of executing their corresponding low-level executable models.

Abstract: A processor with a computer program product embodied thereon for modeling an LDMOS transistor having a drift region is provided. Characteristic behavior of a CMOS transistor with its body coupled to its source is generated, and characteristic behavior of a resistor is generated, where the resistor is coupled to the drain of the CMOS transistor. Then to account for impact ionization, an impact ionization current for electrons in the drift region an impact ionization current for holes in the drift region are calculated.

Abstract: A method for detecting and reporting changes in functional features of a simulation model caused by a software revision is disclosed. In one aspect, the method is independent of simulation model architecture. One performs regression testing with a plurality of feature-specific modules. The feature-specific modules are configured to generate a first set of information with the simulation model and compare the first set of information to a second set of corresponding information from the simulation model. In the above-described testing, the first set of information postdates the software revision and the second set of information predates the software revision.

Abstract: A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly, and thereafter simulating the planarization process with the adjusted density until the hot spot is eliminated.

Abstract: A method of analyzing timing uncertainty involves creating an accurate model of one or more circuit elements of a mesh circuit residing within a window that covers a subset of the mesh circuit. An approximate model of one or more circuit elements of the mesh circuit residing outside of the window is also created. Monte Carlo simulations are performed on the combination of the accurate model and the approximate model to determine a plurality of timing values, wherein each run of the Monte Carlo simulation varies one or more parameters potentially affecting the operation of the mesh circuit. An uncertainty associated with the circuit elements is determined, based at least in part on the plurality of timing values. One embodiment considers clock as the signal whose timing uncertainty can be determined. Other embodiments model and simulate the global drive circuit that drives the mesh circuit separately from the mesh circuit to take into account common path correlations in the drive circuit.

Abstract: A system and method for re-executing a test case and modifying the test case's effective addresses, effective segment identifiers (ESIDs), and virtual segment identifiers (VSIDs) in order to fully test a processor's SLB and TLB cells is presented. A test case generator generates a test case that includes an initial set of test case effective addresses, an initial set of ESIDs, and an initial set of VSIDs. The test case executor uses an effective address arithmetic function and a virtual address arithmetic function to modify the test case effective addresses, the ESIDs, and the VSIDs on each re-execution that, in turn, sets/unsets each bit within each SLB and TLB entry. In one embodiment, the invention described herein sequentially shifts segment lookaside buffer entries, whose ESIDs are in single bit increments, in order to fully test each ESID bit location within each SLB entry.

Abstract: A method of passing data among modules of a heterogeneous software system can include identifying a scripted function to be executed within the heterogeneous software system and building a wrapper script by embedding a call to the scripted function and an XTable object associated with the scripted function within the wrapper script. The method further can include executing the wrapper script thereby causing the scripted function to execute and receiving a result from execution of the scripted function.

Abstract: A method for converting a circuit design into a semiconductor device includes the following steps. A first set of deign information is provided for representing the circuit design. Priority design information, which represents a priority portion of the circuit design, is extracted from the first set of design information. The priority design information is processed for generating a second set of design information. The semiconductor device is fabricated based on the first and second sets of design information. The second set of design information contains enhanced fabrication conditions as opposed to those of the first set of design information for optimizing the conversion of the circuit design into the semiconductor device.

Abstract: A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.

Abstract: A computer readable storage medium storing an electromagnetic field simulation program that causes a computer to execute receiving data defining, in virtual space, a shape of a conductor and an insulator included in a conductive layer and a dielectric layer of a printed circuit board; setting a plurality of cells in the virtual space by arranging nodes of the cells on a boundary between the conductive layer and the dielectric layer in a thickness direction of the printed circuit board and by arranging nodes of the cells at regular intervals in a plane parallel to the printed circuit board; giving, to each of the cells, an electric constant of a medium occupying an area of each of the cells; and determining a change over time in a an electromagnetic field strength in each of the cells.

Abstract: A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.

Abstract: An interference analysis device can be provided, which analyzes interference between wirings of a circuit board with reduced load and for a short time period. The interference analysis device according to the present invention includes: a design data input part for inputting design data of the circuit board; a noise characteristics setting part that sets data representing electrical characteristics of noise for a wiring of the circuit board; a limit value setting part that sets an allowable limit value of noise received by a wiring; a selection part that selects a wiring group to be analyzed based on the noise characteristics data and the allowable limit value; an interference analysis part that calculates, concerning the selected wiring group, an amount of interference from a wiring giving the interference to a wiring receiving the interference; and a received noise level calculation part that calculates a noise level that the wiring receiving the interference will receive.

Abstract: A method and an apparatus for obtaining an equivalent circuit model of a multi-layer circuit are disclosed. The method includes simulating the multi-layer circuit using an electromagnetic field analysis to provide a coupling network; and simplifying the coupling network using a circuit model order reduction method to generate the equivalent circuit model. The method is very simple to implement and the equivalent circuit model obtained has an apparent physical meaning.

Abstract: Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation.

Abstract: Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system logic potentially obscures the detectability of one or more faults in the scan chains (or channels) and vice versa. At least some embodiments employ an iterative approach where at least some scan chain faults are identified, these chain faults are used to identify system logic faults, and then additional chain faults are identified using the system logic faults and vice versa. Failing bits can be partitioned into at least two groups: failing bits determined as being caused by system logic failures, and failing bits determined as being possibly caused by chain defects, system logic defects, or the compound effects of both types of defects.

Abstract: An accurate method to compute the capacitance at a pin whose capacitance is slew dependant. The method uses existing library characterized data and provides an equation based approach which can easily be integrated in static timing analysis without the added resource needs that an iterative approach would require. An RC/RLC network from slew and output load dependent pin capacitance tables is generated. The resulting linear network which models the pin capacitance is then stitched to the original interconnect network and used to calculate the propagation delay across a gate and corresponding interconnect.

Abstract: A method for evaluating an erroneous state associated with a target circuit is provided that includes receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified. One or more partitioned ordered binary decision diagram (POBDD) operations are executed using the information in order to identify an erroneous state associated with a sub-space within the target circuit. A path associated with the erroneous state is identified. The path reflects a correlation between an initial state associated with the erroneous state and a point where the erroneous state was encountered.

Abstract: A network status indicating circuit includes a logic circuit, a switch circuit, and an indicating unit. The logic circuit includes nine input ends, a NOT gate, and two OR gates. The switch circuit includes two input ends and two output ends. The indicating unit includes two LEDs. The logic circuit is connected to the indicating unit to indicate the status of a network IC.

Abstract: A method of physical simulation of an integrated circuit design comprising the steps of (A) reading design information for an integrated circuit from a computer readable storage medium, (B) reading library information and physical design information from the computer readable storage medium, (C) simulating the integrated circuit design based upon the library information and the physical design information using a computer, where the simulation of the integrated circuit design provides signoff accurate results and (D) determining whether the integrated circuit design meets one or more performance goals based upon results of the simulation of the integrated circuit design.

Abstract: In a method for simulating electrical characteristics of a plurality of power planes, each power plane includes a plurality of geometric features. The geometric features of each power plane are projected onto a single planar construct. A polygonal mesh, including a plurality of pairs of interconnected nodes, that corresponds to the single planar construct is generated. The polygonal mesh is projected onto at least one power plane an equivalent circuit between each adjacent node of the plurality of interconnected nodes is projected onto the power plane. An equivalent capacitance is assigned between each node and a common ground planer. A finite element equation that includes a plurality of discrete terms is generated. The equation is solved, thereby determining the electrical characteristic value between each pair of adjacent nodes.

Abstract: A method for evaluating a device during circuit simulation includes receiving a first request including a first input value; and mapping the first input value to a first space in a table. The table is configured to store one or more table entries. A table entry includes an input value and a stored value. The stored value is obtained as a function of the input value from an analytical device model used to characterize the device during circuit simulation.

Abstract: A computer-implemented method for solving parallel equations in a circuit simulation is described. The method includes partitioning a circuit Jacobian matrix into loosely coupled partitions, reordering the voltage vector and the matrix according to the partitions, and splitting the Jacobian matrix into two matrices M and N, where M is a matrix suitable for parallel processing and N is a coupling matrix. M and N are then preconditioned to form M?1Jx=(I+M?1N)x=M?1r and the Jacobian matrix J is solved using an iterative solving method.

Abstract: A method and system are disclosed for preserving measured temperature and geometric behavior of a hardware model while adjusting the model to match specified target values. In one embodiment, the method includes measuring a characteristic of an integrated circuit (IC) chip at a plurality of temperatures; modeling to form a hardware model for the characteristic versus temperature based on the measuring; obtaining a known first target value of the characteristic for at least one temperature in the hardware model; determining a plurality of second target values for the characteristic for a corresponding plurality of temperatures in the hardware model; and modeling to form a target model for the characteristic based on the first known target value and the plurality of second target values.

Abstract: A digital system design method uses a higher programming language. In order to realize a digital system, an algorithm is verified based on a program written by the higher programming language and a program is programmed considering the higher programming language-hardware characteristics before the program is written in the lower programming language, and thus conversion into the lower programming language may be easily performed.

Abstract: A card for simulating peripheral component interconnect (PCI) loads includes an interface configured for electrically connecting to a motherboard and a load circuit configured for simulating the different loads. The load circuit comprises at least one power module receiving a voltage from the interface. The power module is capable of changing resistance of the power module thereby to thermally consume various powers to simulate the different loads. Because the card consumes various power according to testing requirement, the stability of the motherboard can be tested in various load power without connecting actual PCI loads to the motherboard.

Abstract: Capturing interconnectivity data for one or more multi-pin devices in the design of emulator circuit boards is automated using a translator that extracts relevant information, from a text-based input/output (I/O) definition file. The I/O definition file contains textual descriptions of I/O connectivity information for the various devices created by partitioning the design for application on the emulator circuit board, undefined connector interface entries, and design-specific information. The translator parses through the I/O definition file extracting the I/O connectivity and design-specific information, and retrieves connector interface definitions for the undefined connector interface entries using vendor data.

Abstract: In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and simulation and testing for mapping portions of a circuit, such as a power domain or portion of a power domain, to a test mode. Thereby only those portions of the circuit which need to be powered up in a particular test mode are powered up both in the design (simulation) phase and in the actual testing. This conserves power usage during actual testing as against powering up all portions of the circuit, which is not desirable during the testing of the circuit after manufacture. This ensures that the power conditions required to excite and observe any circuit faults during testing exist for the power conditions that are applied during, for instance, manufacturing testing.

Abstract: Embodiments of the present invention provide a method for generating write and read commands used to test hardware device models. The method is able to generate multiple write commands to a location without having to generate intervening read commands to validate the data. In addition, the method enables read commands to be generated in a different sequence from the sequence of generated write commands, having different sizes than the sizes of the write commands, and that maximize the amount of data read (verified) and minimize the amount of unnecessary reads (re-verification).

Abstract: A computer system simulation method starts with algorithmically implementing a specification model independently of hardware architecture. High level functional blocks representing hardware components are connected together using a bus architecture-independent generic channel. The bus architecture-independent generic channel is annotated with timing and protocol details to define an interface between the bus architecture-independent generic channel and functional blocks representing hardware components. The interface is refined to obtain a CCATB for communication space. The read( ) and write( ) interface calls are decomposed into several method calls which correspond to bus pins to obtain observable cycle accuracy for system debugging and validation and to obtain a cycle accurate model.

Abstract: A method and apparatus for developing microcomputer-based systems. A controller model having at least one parameter is simulated and, similarly, a plant model having at least one parameter and controlled by the controller model is simulated. A user interface then has access to the parameters of the controller model and plant model and optionally suspends the execution of the controller model and plant model in response to a trigger event. The user interface determines the status of the controller model parameters and/or plant model parameters at the time of the trigger without altering the controller model parameters or plant model parameters or the program code of the controller model.

Abstract: A method and a device for simulating an automation system are disclosed. The aim of the invention is to allow an automation system to be simulated in such a way that simulation components operating at very different computing speeds can be combined into an overall simulation. Said aim is achieved by a method comprising a control component that can be clocked using an external timing source and at least one simulation component which can be clocked using an external timing source. A coordinated clock system is provided for the control component and the at least one simulation component by means of a control component-independent timing coordinator.

Abstract: A design structure embodied in a machine readable medium used in a design process includes an apparatus for testing logic devices configured across asynchronous clock domains, including a deactivation mechanism for deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto; wherein the deactivation mechanism is configured to permit data capture within the first plurality of latches, and wherein the deactivation mechanism is further configured to permit at-speed data launch from the first plurality of latches to downstream latches with respect thereto during at-speed testing.

Abstract: There is provided a data processing apparatus (1) including a logic circuit (10) that is reconfigurable in each cycle and a library (2) that stores hardware control information (20). The hardware control information (20) includes a plurality of pieces of cycle-based mapping information (21) for individually mapping a plurality of cycle-based circuits, which each realize a function in each cycle for executing an application, onto the logic circuit (10) and configuration selection information (22) for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application. The data processing apparatus (1) includes a control unit (11) that reconfigures at least part of the logic region (10) using at least one of the plurality of pieces of cycle-based mapping information (21) according to a request in each cycle based on the configuration selection information (22).

Abstract: A multi level cell (MLC) NAND flash memory storage system is provided. A controller of the MLC NAND flash memory storage system declares it a signal level cell (SLC) NAND flash memory chip to a host system connected thereto and provides a plurality of SLC logical blocks to the host system. When the controller receives a write command and a user data from the host system, the controller writes the user data into a page of a MLC physical block and records the page of the SLC logical block corresponding to the page of the MLC physical block. When the controller receives an erase command from the host system, the controller writes a predetermined data into the page of the MLC physical block mapped to the SLC logical block to be erased, wherein the predetermined data has the same pattern as a pattern of the erased page.

Abstract: Various tools and techniques are provided for reducing an original circuit network into a simpler, realizable RCLM circuit network. Branches of the original network are merged to reduce its total number of nodes. More particularly, the branches of the original circuit are merged so that the resulting reduced circuit approximately replicates the timing characteristics of the original circuit over the desired operating frequency range. The determination whether to merge two branches is made based upon one or more circuit characteristics associated with the node connecting the branches.