Abstract: A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

Abstract: A test system or simulator includes an enhanced IC test application sampling software program that executes test application software on a semiconductor die IC design model. The enhanced test application sampling software may include trace, simulation point, CPI error, clustering, instruction budgeting, and other programs. The enhanced test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software workloads. The enhanced test application sampling software utilizes the microarchitecture dependent information to generate the FBVs to select representative instruction intervals from the test application software. The enhanced test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing a global instruction budgeting analysis method.

Abstract: A design specifications-driven platform (100) for analog, mixed-signal and radio frequency verification with one embodiment comprising a client (160) and server (150) is presented. The server comprises an analog verification database (110), a code and document generator (1020), a design to specifications consistency checker (103), a symbol generator (104), a coverage analyzer (105), a server interface (106), a web server (111), and an analog verification server application (101). The client comprises a web browser (130), generated datasheets and reports (120), generated models, regression tests, netlists, connect modules, and symbols (121), generated simulation scripts (122), a client interface (124), design data (131), simulators (132), and a design data extractor (123).

Abstract: Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device.

Abstract: A method is provided to produce a model of an integrated circuit substrate, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; and connecting the mapped tile instances to each other to produce a tile grid that models overall electrical behavior of the substrate.

Abstract: A computer-implementable method comprises a matrix-based approach to generating in parallel a plurality of realistic simulatable signal vectors, which vectors include the addition of amplitude noise and/or timing jitter and encoding. Each channel in a parallel bus can be populated in a matrix, with each row comprising ideal voltage values for the channel, and the columns comprising bits of the sequence of voltage values for that channel. Encoding can be employed to modify the data in the matrix. Amplitude noise and/or timing jitter can then be applied to each channel (row) in the matrix. This modifies the time basis from a bit basis as used in the matrix to a time-step basis. With such modification accomplished, each row in the matrix can be transformed into simulatable vector, which vectors can then be simulated in parallel to test, the robustness of the parallel bus of which the channels are part.

Abstract: A method for generating a compressed representation of a simulated waveform is disclosed. The method may have the steps of: (a) processing circuit model information, (b) identifying a segment of stable repetition; and (c) generating the compressed representation. Step (a) may generate waveform information representing a simulated waveform occurring in the circuit model. Step (b) may identify the segment in the waveform information. In step (c), the compressed waveform information may define the segment by (i) cycle information representing the waveform cycle and (ii) repetition information representing the stable repetitions of the waveform cycle to form the segment.

Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.

Abstract: Disclosed are exemplary finite difference methods for electromagnetically simulating planar multilayer structures. The exemplary finite difference methods simulate multilayer planes by combining the admittance matrices of single plane pairs and equivalent circuit models for such single plane pairs based on multilayer finite difference approximation. Based on the methods, coupling between different layers through electrically large apertures can be modeled very accurately and efficiently.

Abstract: A computer-implemented method of scheduling a multi-rate, synchronous circuit design for simulation within a high-level modeling system. The method can include determining a component clocking rate for each of a plurality of synchronous components of the circuit design and classifying each of the plurality of synchronous components into a plurality of schedules according to component clocking rate. For each clock cycle during simulation, the method can include selecting one of the plurality of schedules and executing each synchronous component of the selected schedule. A value determined through execution of a synchronous component of the circuit design can be output.

Abstract: A method of communicating data among a plurality of software modules of a heterogeneous software system can include constructing an XTable object in a first software module of the plurality of software modules and providing the XTable object to a second software module of the plurality of software modules. The method further can include extracting data from the XTable object within the second software module.

Abstract: A computer-based simulation process executes a checkpoint operation while simulating behavior of an electronic circuit by forking an active checkpoint process having the same state as the original simulation process. While simulation time for the simulation process continues to increase after executing the checkpoint operation, simulation time for the checkpoint process remains unchanged so that the checkpoint process remains in the state of the simulation at the simulation time it executed the checkpoint operation (the “checkpoint time”). When the checkpoint process subsequently receives a request to resume simulating the circuit, it forks a new simulation process that mimics the original simulation process as of checkpoint time, and the new simulation process then begins to advance its simulation time, thereby enabling it to re-simulate behavior of the electronic circuit previously simulated by the original simulation process starting from the checkpoint time.

Abstract: A method for reducing variation in a desired property between transistors in an integrated circuit that is fabricated with a given process. The process is characterized to form a mathematical model that associates changes in polysilicon density and active density in the integrate circuit with changes in gate length and gate width in the transistors, and associates changes in the gate length and the gate width to the desired property. The integrated circuit is laid out with space sufficient to adjust the gate length and the gate width of the transistors without violating design rules of the transistors. The integrated circuit is divided into portions, and for at least a given one of the portions of the integrated circuit, the polysilicon density and the active density of the given portion is measured.

Abstract: A design structure which enables e-fuse memory repair. The design structure uses a compressed bit string to generate another bit string based on a select value. The select value provides instructions to an encoding logic element, which generates a second bit string. For example, the select value may instruct the encoding logic to create a duplicate copy of each bit in the compressed bit string to generate a 2n-bit string. Once the fuses are programmed using the second bit string, the fuse values are read out as a third string, which is decoded by a decoding logic element according to the select value, thereby improving memory repair.

Abstract: Embodiments of the present invention provide a method for performing lumped-process model calibration. The method includes creating a plurality of sub-process models for a set of sub-processes; creating a lumped-process-model incorporating said set of sub-processes; calculating a first set of output patterns from a set of test patterns by using said plurality of sub-process models; calculating a second set of output patterns from said set of test patterns by using said lumped-process-model; and adjusting process parameters used in said lumped-process-model to calculate said second set of output patterns to match said first set of output patterns. A computer system for performing the lumped-process model calibration is also provided.

Abstract: A method of optimizing MOSFET device production which includes defining key independent parameters, formulating those key independent parameters into a canonical variational form, calculating theoretical extracted parameters using at least one of key independent parameters in canonical variational form, physics-based analytical models, or corner models. The method also includes calculating simulated characteristics of a device using the key independent parameters and extracting target data parameters based on at least one of measured data and predicted data, comparing the simulated characteristics to the target data parameters, and modifying the theoretical extracted parameters or key independent parameters in canonical form as a result of the comparison. Then, calculating and outputting the simulated characteristics based on the modified theoretical extracted parameters and the modified key independent parameters in canonical form.

Abstract: A skeleton generation method includes: creating a netlist which is a circuit connection information input file format for analog circuit simulation, as subcircuit descriptions corresponding to function blocks of a system, on the basis of input and output information on the function blocks; constructing a function block skeleton of a system level design language using the respective subcircuit descriptions as units of the function blocks, on the basis of the circuit connection information described in the netlist; and constructing a system skeleton on the basis of a result of analysis of connection information on nodes of the subcircuit descriptions.

Abstract: The electrical circuit timing method provides accurate nominal delay together with the delay sensitivities with respect to different circuit elements {e.g., cells, interconnects, etc.) and variational parameters (e.g., process variations; environmental variations). All the sensitivity computations are based on closed-form formulas; as a consequence, the method provides rapidly and at low cost high accuracy and high numerical stability.

Abstract: A method and apparatus are described in which an optimal configuration of memory instances is determined. The optimal configuration of memory instances to be fabricated with built-in repair capacity and memory instances that are non-repairable may provide a maximum number of good chip dies per wafer. An amount of memory instances to be fabricated with built-in repair capacity as well as a remaining amount of memory instances to be fabricated without any built-in repair components in the integrated circuit design is determined relative to achieving the maximum number of good chip dies per wafer for a given defect density and wafer area. The amount of good dies produced per fabricated wafer for a populated amount of memories with built-in repair components is determined to be between an amount established by a minimum limit for the die area up to the amount established by a maximum limit for the die area.

Abstract: Methods and apparatuses for modeling and simulating a high-level circuit design are provided. With some implementations of the invention, a layered model corresponding to an algorithmic description for a circuit design is generated. The layered model includes a set of threads that describe the behavior of the circuit design, a schedule that describes timing constraints of the circuit design, and interfaces that facilitate the transfer of data between various layered models. With some implementations, a layered model may also include a shared variable that facilitates the transfer of data between ones of the set of threads within a layered model.

Abstract: This invention relates to a system level power evaluation method in which detailed power macro-models (PMM) are created for operations of modules. These PMMs are stored in memory. A system level circuit description (SLCD) is evaluated using the PMMs stored in memory that are relevant to that SLCD and using other PMMs that are generated for operations of modules that do not have PMMs stored in memory. In this way, a highly accurate and computationally efficient power evaluation of the SLCD is possible. Furthermore, the user implementing the method may define a case, which relates to an operation of a module and has a PMM associated therewith, in a highly flexible manner that allows for more abstract analysis of the SLCD to be carried out. A case may relate to a single operation of a module, a plurality of operations of a module or operation(s) of a plurality of modules.

Abstract: An apparatus and computer program product for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The apparatus and computer program product may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the apparatus and computer program product, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the apparatus and computer program product may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.

Abstract: Methods and systems for providing a synchronous model in a modeling environment are disclosed. The predetermined operations of the model, such as a transition to a state in a state-based modeling environment, are implicitly synchronized with a signal selected by users, such as a clock signal. The predetermined operations of the model may be synchronized on a rising and/or falling edge of the clock signal. The synchronization of the operations is guarded in which the predetermined operation of the model occurs only on the synchronization signal selected by the users while other operations may occur at any time when the model is activated.

Abstract: A method is provided for simulating a complex system including a scheduler hierarchy. The complex system includes at least one processor that executes a set of functions under the control of a hierarchical group of schedulers. The method includes a step of constructing an architectural model of the complex system comprising a hierarchical group of components, each of said components comprising an instance of an object class belonging to the group containing: a first class, known as the Processor class, which represents an abstract model of any processor included in the complex system, a second class, known as the Function class, which represents an abstract model of any function executed by the complex system; and a third class, known as the Scheduler class, which represents an abstract model of any scheduler. Each instance is initialized with at least one attribute that characterizes the behavior desired therefrom.

Abstract: One embodiment of the present invention is a method for producing a system for describing an electrical network. An output signal of the electrical network is sampled at a frequency that corresponds to the Nyquist criterion for the input signal to the electrical network. A model with a memory is developed for the output signal, which is sampled at a low sampling rate, with this model approximating the output signal. The model is then transformed by suitable interpolation to an interpolated model with a memory. The interpolation results in the model created in this way providing a good approximation to an output signal which is sampled at a high frequency. The resultant system can be used for predistortion.

Abstract: Methods for identifying failing timing requirements in a digital design. The method includes identifying at least one timing test in the digital design that has a passing slack in a base process corner and a failing slack in a different process corner. The method further includes computing a sensitivity of the failing slack to each of a plurality of variables and comparing each sensitivity to a respective sensitivity threshold. If the sensitivity of at least one of the variables is greater than the respective sensitivity threshold, then the at least one timing test is considered to fail.

Abstract: Systems and methods for hierarchical noise analysis of digital circuits, wherein analysis of a cell is based on the configuration of the cell itself and also the upstream circuit components that are connected to the inputs of the cell. One embodiment comprises a method for noise analysis in an electronic circuit such as a digital CMOS circuit. The method includes identifying a cell and identifying the inputs of the cell. For each of the inputs of the cell, a corresponding first upstream circuit component is identified. The identified component is the first component upstream from the cell's input and is directly connected to the input. A noise analysis for the cell is performed based upon the configuration of the cell in combination with the identified upstream circuit components. The result of the analysis for the combination of the cell and the upstream circuit components can then be stored.

Abstract: A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology.

Abstract: A method of simulating an integrated circuit design is provided. In this method, a node order ranking of nodes in a netlist can be determined. Circuits of the netlist can then be partitioned based on the node order ranking with both static current driving and dynamic current driving schemes. A hierarchical data structure can be built based on the node order partitioning. In one embodiment, intermediate node orders can be dynamically merged for simulation optimization. Then, the circuits can be re-partitioned based on one or more merged intermediate node orders. Solving and integration can be performed using the hierarchical data structure to generate an order-ranked hierarchy engine. Analysis on the order-ranked hierarchy engine can be performed. At this point, simulation data of the IC design can be exported based on the analysis. By using this method, linear network reduction with its attendant accuracy loss is unnecessary.

Abstract: A simulator system is connected to simulate the connection of a mechanically loaded motor to a motor controller/driver. The simulator system includes a current transformer circuit for monitoring AC output currents provided by the motor controller/driver. A simulation controller calculates, based on the monitored AC output currents, dynamic load voltages that simulate the response that would be generated by a mechanically loaded motor based on the AC output currents provided by the motor controller/driver. A number of power supplies amplify the dynamic loading calculated by the simulation controller to generate a dynamic loading that opposes the AC output currents provided by the motor controller/driver.

Abstract: Mechanisms for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is provided that does not have this asynchronous behavior logic but instead correlates to the simplest synchronous model that is usually used for non-asynchronous functional verification tasks. Sequential equivalence checking is performed to verify that the two models are input/output equivalent. In order to address non-uniform arrival times of bus strands, logic is provided for identifying bus strands that have transitioning bits, determining a representative delay for these strands, comparing the representative delays for all of the bus strands to determine the maximum delay for the entire bus, and applying this maximum delay to one of the models.

Abstract: An embodiment relates to a multi-objective optimization design supporting technique to reduces the computational complexity of QE/CAD. When the input logical expression generated by a logical-expression-with-qualifier generation unit is satisfied in regard to the sample point included in a certain piece of cell information for each value of the same design parameter, a first cell processing unit does not evaluate the input logical expression on the cell information including other sample points having a value equal to or smaller than the value of a predetermined design variable (for example, a design variable indicating a yield) corresponding to the sample point above, but selects it as the cell information for an output of a logical expression without a qualifier.

Abstract: An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.

Abstract: A disclosed device includes a simulation apparatus which simulates a shift in signal characteristics occurring in a wiring pattern formed in a printed wiring board including a first database that stores wiring pattern attribute information and wiring pattern positional information, a second database storing solid lack portion size information and solid lack portion positional information, a third database that stores shift amount information relative to positional relationships between the wiring patterns and the solid lack portions, a shift amount processing unit configured to obtain the shift amount of the signal characteristics in the wiring pattern corresponding to the wiring pattern attribute information which is input based on the wiring pattern positional information corresponding to the wiring pattern attribute information which is input, the solid lack portion positional information, the solid lack portion size information, and the shift amount information.

Abstract: A discrete event system (DES) modeling environment models the occurrence of events independent of continuous model time. In a DES modeling environment, state transitions depend not on time, but rather asynchronous discrete incidents known as events. A user may customize selected parameters of a block or other component able to support at least one entity passing therethrough holding a value of arbitrary data type in a DES modeling environment. For example, a user can enable and disable ports a discrete event execution block in a discrete event execution model using a graphical user interface, such as a dialog box. Based on user-selected dialog inputs, a discrete event execution program can automatically update a specification for a block, for example, by adding ports to the graphical representation of the block.

Abstract: Techniques are provided for modeling memory operations when generating test cases to verify multi-processor designs. Each memory operation has associated therewith a set of transfer attributes that can be referenced by a test generator. Using the transfer attributes, it is possible to generate a variety of interesting scenarios that handle read-write collisions and generally avoid reloading or resources. The model provides accurate result prediction, and allows write access restrictions to be removed from sensitive memory areas, such as control areas.

Abstract: Mechanisms for accurately modeling an asynchronous interface using expanded logic elements are provided. With these mechanisms, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration whether or not the primitive logic elements themselves may be experiencing a switching or glitch hazard and whether or not the inputs to the primitive logic elements may be based on a switching or glitch hazard from another primitive logic element in the asynchronous interface logic. These expanded logic elements are used in an integrated circuit design to replace the original primitive logic elements in the design. The asynchronous interface may then be simulated with the expanded logic elements providing outputs indicative of whether the actual data output of the expanded logic elements is deterministic or not.

Abstract: A power supply system includes a power supply, a daughterboard, and a motherboard. Output currents of power connectors of the motherboard and impedances of copper foils between every two adjacent power connectors of the motherboard are obtained via simulation. A voltage of one power connector of the motherboard is predetermined. Therefore, desired impedances of copper foils between VRM connectors and corresponding power connectors on the daughter board are determined via calculations, to make currents passing through the power connectors of the motherboard equal to each other.

Abstract: A high-speed multicore model simulator is realized. A multicore model simulator having a plurality of threads, and a plurality of core models executing the aforesaid plurality of threads is provided. The plurality of core models are a plurality of processor core models, each of which executes one thread, and they are synchronized with each other every predetermined number of execution instructions of each thread.

Abstract: Power gating logic cones is described. In one embodiment a method includes synthesizing logic for an integrated circuit (IC) design; identifying low switching nodes within the logic that switch less than a threshold; determining a potential power gating cone (PGC) based on the identified low switching nodes; determining a power gating logic expression for the potential PGC that includes a minimum set of inputs to the potential PGC that are least switching; determining whether energy savings using the power gating logic expression meets a criteria; and accepting the potential PGC in response to meeting the criteria.

Abstract: A method and system for automating unit performance testing in integrated circuit design is disclosed. One embodiment of the present invention sets forth a method, which includes the steps of generating a first performance data for the unit to operate on a workload, embedding the first performance data in the workload for a register transfer level (RTL) implementation of the unit to operate on, and determining whether the expected performance of the unit is achieved based on the comparison between the first performance data and a second performance data, wherein the second performance data is generated after the RTL implementation of the unit operates on the workload.

Abstract: This invention provides techniques and tools for reducing circuit simulation time when an electronic circuit with multiple input vectors is simulated. Instead of running the simulation for each input vector one at a time, the circuit-simulation application runs the simulation of the circuit for all input vectors simultaneously. Efficiencies in the simulation are obtained during each iteration of a transient analysis by grouping circuit instances with different input vectors based on a predetermined criteria, and producing a combined solution for circuit instances within each group.

Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

Abstract: Methods and apparatuses for generating a random sequence of commands for a semiconductor device. The method generates random state transitions within a finite state machine model of the semiconductor device. A sequence of commands is determined which are associated to the generated random state transitions based on the finite state machine model of the semiconductor device.

Abstract: A method for allowing simultaneous parameter-driven and deterministic simulation during verification of a hardware design, comprising: enabling a plurality of random parameter-driven commands from a random command generator to execute in a simulation environment during verification of the hardware design through a command managing device; and enabling a plurality of deterministic commands from a manually-driven testcase port to execute in the simulation environment simultaneously with the plurality of random parameter-driven commands during verification of the hardware design through the command managing device, the plurality of deterministic commands and the plurality of random parameter-driven commands each verify the functionality of the hardware design.

Abstract: A methodology is provided to perform noise analysis in the implementation stage of the design of an integrated circuit, and based upon analysis results, a floorplan may be adjusted or guard rings may be inserted to reduce the impact of digital switching noise upon noise sensitive circuits.

Abstract: A method for creating a global simulation model of an architecture for models of integrated circuits under development, including reading an architecture description file of the global model and storing information related to all of the possible configurations instantiating the components and storing the corresponding information, topologically connecting the interface signals, physically connecting the interface signals, at the level of each instance of the components using a component and connection rule table, and storing the corresponding information, and automatically generating the HDL-type and HLL-type source files of the global simulation model.

Abstract: A method of using a static performance analyzer that accepts as input a cell-level netlist, to perform static performance analysis on a circuit represented by a transistor level netlist. The method begins with converting said transistor-level netlist to a cell-level netlist by modeling individual transistors with a cell model. Then, a static performance analyzer is used to perform a static performance analysis of said cell-level netlist. Among performance characteristics that may be analyzed are timing (static timing analysis) and leakage power. The method described may also be used for statistical static timing and power analysis.

Abstract: A method, apparatus and a filter compiler system for building a filter is disclosed. The filter compiler system includes a filter resource estimator. The filter resource estimator is configured to estimate an implementation cost of the filter. The filter compiler system determines whether the implementation cost is acceptable and updates a design of the filter upon determining that the implementation cost is unacceptable.

Abstract: A via impedance matching method is provided. Firstly, a circuit model of a via in the PCB is created, which comprises a low pass filter circuit composed of two capacitors connected in parallel and an inductor connected between the two capacitors. Then, S parameters of the via by analyzing the circuit model is obtained and converted to an ABCD matrix, and parameters of an ideal low pass filter model is obtained by equaling an ABCD matrix of the ideal low pass filter model to the ABCD matrix with the S parameters. Then, impedance matching parameters are calculated according to the parameters of the ideal low pass filter model. Finally, proper capacitors and inductors are selected and disposed on the PCB to match the via.