Abstract: A method for generating and evaluating a table model for circuit simulation in N dimensions employing mathematical expressions for modeling a device. The table model uses an unstructured N-dimensional grid for approximating the expressions.

Abstract: Methods are provided for processing design information of an electronic circuit design. A single path or multiple paths that are produced by a first design tool are an input for the method. Each path includes an ordered set of element names of the electronic circuit design. Each element name of each path is pattern matched with the names of design blocks of the electronic circuit design produced by a second design tool. Data indicative of a path produced by the second design tool that includes the design blocks that are pattern matched to the ordered set of element names is the output of the method.

Abstract: A delay calculation method that is capable of calculating delay time with a small margin of error is provided for delay calculation in a logic circuit. The operating characteristics of transistor are expressed with a fixed resistance and a power supply voltage that changes with time. The power supply voltage is represented as a waveform which is a combination of two straight lines: the one indicating that the voltage, after a fixed delay of t0, increases to V1 during ?t1; and the one indicating that the voltage increases from V1 to E during ?t2 and thereafter remains at the fixed value of E. A difference in the shapes of input waveforms is adopted as a correction parameter to determine the values of ?t1, V1, and ?t2.

Abstract: Stimulation signals (22) are applied to a first circuit model (20) and the power behaviour of the circuit being modelled is determined from the behaviour of the first circuit model (20). In parallel, the same stimulation signals (22) are applied to a second circuit model (26) and the state variable changes within that second circuit model are calculated. The calculated power behaviour and the calculated state variable changes are then applied as training data inputs to a self learning power model, such as a neural network (28), which learns the relationship between state variable changes between the second model (26) and power behaviour of the circuit being simulated. In this way, a detailed first circuit model (20) may be used to calculate power behaviour and to train a separate power model (28, 30) which once trained can be publicly released without having to release sensitive information within the first circuit model (20).

Abstract: The method and the computer-related products provide for error information relating to inconsistencies in a system of differential equations that describes a technical system or a technical process.

Abstract: A method and a system for defining groups of tests that may be concurrently performed or overlapped are provided. Channel-independent test groups are determined such that each group includes tests that the input/output channels may be utilized simultaneously without conflicts. The channel-independent test groups are divided into block-under-test (BUT) conflict test groups and total-independence test groups. The total-independence test groups may be performed concurrently. Performance of the BUT-conflict test groups may be overlapped such that the input/output channels are used concurrently, but the execution of the tests by the blocks of the device-under-test (DUT) is performed sequentially.

Abstract: In accordance with an embodiment of the present invention, a method of serving IBIS data may include determining a circuit specified for signal integrity simulation. IBIS data may be obtained for the circuit specified, from which polynomials may be determined to be representative of at least a portion of the IBIS data. The polynomial information determined may be stored in a file with indexing for enabling its subsequent selective retrieval by way of a request for the IBIS data for the specified circuit.

Abstract: A method, system and program product are disclosed that enable a netlist of an integrated circuit (IC) design for modeling of technology dependent back-end-of-line (BEOL) process variation. In one embodiment, the method includes obtaining a netlist of electrical elements (i.e., BEOL parasitic resistance and/or capacitance), the netlist including estimated electrical values for the electrical elements and geometric data for at least one of the electrical elements; determining variations of the electrical value for a selected electrical element based on the geometric data using a scaling methodology; and placing a model call in the netlist, the model call implementing the variations of electrical value for the selected electrical element. The revised netlist can be used to model the IC design and includes a scaling of electrical values without having to generate more than one netlist.

Abstract: Methods and systems for partitioning objects in modeling environments are disclosed. The modeling environments enable users to partition an object (parent object) to include other objects (child objects). The parent object may reference the child objects (referenced objects). The child objects may be subsystems in the hierarchy of the parent object or modules (or units) in the partitioning of the parent object. The child objects may be encapsulated so that changes in the parent object do not affect the child objects. The partition of the parent object may allow users to load and compile the parent object incrementally. The partition of the parent object may also allow users to generate code for the parent object incrementally.

Abstract: In a graphical modeling environment, bus signals, which group a plurality of signals together for simplifying a model, include a partial or complete physical definition. Models are simplified by passing bus signals through graphical objects representing functional entities, without degrouping the bus signal. During simulation of the model, code can be generated for the bus signal having a complete definition independent of other components of the graphical model.

Abstract: A method and apparatus are provided for storing the boot configuration PROM of a microprocessor in an FPGA. The boot interface of the microprocessor, such as an I2C interface, leads to the FPGA instead of to a PROM. The boot configuration is stored as an image in the FPGA, and the microprocessor accesses the boot configuration using its normal boot interface. In this way, a dedicated boot PROM is not needed, saving real estate on the card on which the microprocessor is located. The boot configuration is also more easily modified, such as for version upgrades or diagnostics, than if the boot configuration were stored on a dedicated PROM. Different boot configurations may be stored as software images on a separate housekeeper processor, for loading into the FPGA.

Abstract: A reduced order model of a distributed time invariant system is produced by projecting system matrices onto smaller matrices, interpolating the matrices and placing into a state-space system. The system matrices are an internal representation of the distributed time invariant system which comprises a description of the system to be modeled, mainly, for example, its inputs and outputs. The method is applied to distributed systems and guarantees accuracy in complicated systems and produces well-behaved models appropriate for use in simulators and simulations.

Abstract: A method of providing simulation results includes detecting any power net and rail in a circuit netlist. The circuit can be divided into net-partitioned blocks. Using these net-partitioned blocks, a topological analysis can be performed to identify cuttable/un-cuttable devices and synchronization requirements. Then, the circuit can be re-divided into rail-partitioned blocks. Using these rail-partitioned blocks, a sparse solver can identify potential partitions, but eliminate fill-ins as determined by the topological analysis. A cost function can be applied to the potential partitions as well as the identified cuttable/un-cuttable devices to determine final cut points in the circuit and dynamic inputs to the final blocks. Simulation can be performed on the final blocks and simulation results can be generated.

Abstract: A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

Abstract: An automated design process using a computer system includes identifying a set of timing endpoints in a circuit defined by a machine-readable file. Values of slack in the estimated arrival times for the timing endpoints are assigned. Probability distribution functions, such as Gaussian distributions, are assigned for the respective values of slack, and are combined. The combination of probability distribution functions represents a measure of circuit performance. The measure is computed for alternative implementations of the circuit, and used to identify an alternative more likely to meet timing constraints.

Abstract: Determining piece-wise polynomials which together would represent large data sets having multi-dimensional input vectors and corresponding output element. In an embodiment, a function/procedure/routine is recursively called/invoked to determine piece-wise polynomial is a data set cannot be entirely modeled by one polynomial. Another aspect of the present invention reduces the number of combinations (of orders for sub-polynomials forming the polynomials) to be tried in determining polynomials, meeting various accuracy requirements. Such a reduction is obtained based on a recognition that when the order in one dimension alone is increased and the result does not lead to acceptable accuracy of the polynomial, the combinations with a lesser number for the order (of the dimension) can be ruled out.

Abstract: Systems and methods for designing and generating integrated circuits using a high-level language are described. The high-level language is used to generate performance models, functional models, synthesizable register transfer level code defining the integrated circuit, and verification environments. The high-level language may be used to generate templates for custom computation logical units for specific user-determined functionality. The high-level language and compiler permit optimizations for power savings and custom circuit layout, resulting in integrated circuits with improved performance per watt of power consumption.

Abstract: An apparatus for automatic testing of a PS/2 interface includes a micro controller unit, a PS/2 port, and a plurality of LEDs. The micro controller unit is coupled with both a data pin and a clock pin of the PS/2 interface. The LEDs coupled to the micro controller unit simulate functions of a keyboard. A related method for testing the PS/2 interface is also provided.

Abstract: A self-checking test generator program creates a self-checking test program that can test a device under test (DUT). The self-checking test generator selects instructions for a test. Selected instructions are executed on a software DUT model to generate results that can be self-checked by other instructions such as compare and branch instructions. The software DUT model has fuzzy models and unknown models for blocks in the DUT. Fuzzy models generate expected outputs for a block of the DUT. Fuzzy models may propagate unknown data from their inputs to their outputs. Unknown models do not predict expected outputs. Instead, unknown models always output unknown (X). Over time, as more of the DUT logic is modeled, unknown models may be replaced with fuzzy models.

Abstract: A layout comprises a plurality of elemental areas which define the shape and arrangement of patterns of an integrated circuit. A method for searching for potential faults in the layout begins with dividing the layout into sections. One of a number of predetermined classes is allocated to a section by means of allocation criteria. An evaluation criterion allocated to the class which was allocated to the section is then applied to the section in order to obtain an evaluation result. Each section is then identified as potentially faulted in dependence on the evaluation result.

Abstract: Mechanisms for modeling metastability decay through latches in an integrated circuit model are provided. Asynchronous clock boundaries are identified in the integrated circuit model and latches in a receive clock domain are enumerated. Latches within a range of the asynchronous clock boundary are selected for transformation. These latches are transformed into metastability decay latches using new latch primitive logic that models the decay of an indeterminate value. The metastability decay latches maintains an indeterminate value during a metastability time period and achieve a randomly selected logic value at the end of the metastability time period. The transformed integrated circuit model may then be simulated and the results analyzed to generate reports of the integrated circuit model's operation. The transformed integrate circuit model more accurately represents the actual operation of the hardware implementation of the integrated circuit model.

Abstract: A method of determining the behavior of an electronic system comprising electronic components under variability is disclosed. In one aspect, the method comprises for at least one parameter of at least one of the electronic components, showing variability defining a range and a population of possible values within the range, each possible value having a probability of occurrence, thereby defining an input domain. The method further comprises selecting inputs randomly from the input domain, wherein the probability to sample (PTS) is obtained from the probability of occurrence (PTOIR). The method further comprises performing simulation to obtain the performance parameters of the electronic system, thereby defining an output domain sample.

Abstract: The accuracy of effective channel width extraction in drain current method is improved. There are prepared a transistor with a wide channel width serving as a reference, and a transistor with a narrow channel width that becomes a candidate for extraction (step ST1.1). From the characteristic curve of a plane formed by mask channel width and source-drain conductance, there is extracted a virtual point at which the change of source-drain conductance is estimated to be approximately zero even if the gate overdrive is finely changed. Then, the value of function F is calculated which is defined by the difference between the change of the conductance at the coordinate of the virtual point and the product obtained by multiplying the conductance per unit width by the change of the mask channel width (step ST1.6). From a shift amount (?) which minimizes the standard deviation of the function F to be obtained (step ST1.

Abstract: Disclosed herein is a method of managing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, a restriction list associated with the HDL model is received. The HDL model has a maximum number of possible keyword/value pairs sets for which result data can be obtained, and the restriction list specifies a fewer number of keyword/value pair sets for which the result data can be queried based upon at least one keyword. In response to receipt of result data obtained by simulation of the HDL model, the result data are stored within a data storage subsystem by reference to the restriction list, such that particular result data attributable to each of the plurality of keyword/value sets is separately accessible.

Abstract: System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse circuit descriptions, such as gate level netlists. The tool is capable of generating rudimentary substrate models based on estimated die size, allowing the designer to have an early indication of potential substrate noise issues. During the middle phases, the tool can accept more accurate circuit descriptions, such as a SPICE netlist. A more detailed substrate model can be generated, which considers layout information, thereby allowing the designer to make layout and circuit modifications before the circuit is completed. Lastly, during final verification, the tool can accept an even more accurate netlist, such as a SPICE netlist that includes parasitic capacitance. The tool can also accept a more detailed substrate model and provides the substrate noise analysis necessary to finalize the design.

Abstract: A digital circuit simulation method. The method starts with a digital circuit design which includes: a first source latch, a destination latch, a logic cone, a first WAM circuit electrically coupling an output of the first source latch to a first input of the logic cone, and a WAGG circuit electrically coupling an output of the logic cone and an input of the first source latch. Then, a zero-delay simulation is performed in which if a first situation of (a) the first WAM circuit entering an uncertainty state in which the first WAM circuit generates a random value of 1 or 0 at the first input of the logic cone, (b) the logic cone being vulnerable to a positive glitch, and (c) the output of the logic cone being at logic 0, the WAGG circuit generates a random value of 0 or 1 at the input of the destination latch.

Abstract: In the VCD-On-Demand system, the EDA tool has the following attributes: (1) RCC-based parallel simulation history compression and recording, (2) RCC-based parallel simulation history decompression and VCD file generation, and (3) On-demand software regeneration for a selected simulation target range without simulation rerun. When the user selects a simulation session range, the RCC System records a highly compressed version of the primary inputs from the test bench process. The user then selects a narrower region, the simulation target range, within the simulation session range for a more focused analysis. The RCC System dumps the hardware state information of the hardware model into a VCD file. The RCC System then allows the user to proceed directly to view the VCD file from the beginning of the simulation target range without having to rerun the entire simulation from the beginning of the simulation session range.

Abstract: A method, apparatus and system for building a filter is disclosed. In a particular embodiment, the filter is a finite impulse response (FIR) filter and a compiler suitable for implementing the FIR filter is described. The compiler includes a filter coefficient generator suitably arranged to provide a first set of filter coefficients corresponding to the desired FIR filter spectral response and a filter spectral response analyzer coupled to the filter coefficient generator for providing an expected FIR filter spectral response based in part upon the first set of filter coefficients. The compiler also includes a filter resource estimator coupled to the filter spectral response simulator for estimating an implementation cost of the FIR filter based upon the second set of filter coefficients as well as a filter compiler unit coupled to the resource estimator arranged to compile a FIR filter implementation output file.

Abstract: A system is provided for modeling an integrated circuit including at least one insulated-gate field-effect transistor. The system includes generator means for defining a parameter representing mechanical stresses applied to the active area of the transistor, and processing means for determining at least one of the electrical parameters of the transistor based at least partially on the stress parameter. Also provided is a method of modeling an integrated circuit including at least one insulated-gate field-effect transistor, and a method of producing an integrated circuit including at least one insulated-gate field-effect transistor.

Abstract: Techniques are disclosed for determination of parameter variability for one or more given interconnects of a plurality of interconnects in a simulated semiconductor circuit. The simulated semiconductor circuit is defined at least in part by a plurality of input parameters. From a distribution of first values of a given input parameter, a plurality of the first values are determined to use when calculating a corresponding plurality of second values for each of one or more output parameters. By using at least the determined plurality of first values for the given input parameter and selected values for other input parameters in the plurality of input parameters, the corresponding plurality of second values are calculated for each of the one or more output parameters. The one or more output parameters correspond to the one or more given interconnects. Each of the second values corresponds to one of the determined plurality of first values.

Abstract: A tool for emulation systems that obtains the state values for only discrete partitions of a circuit design. When a partition is being emulated, the emulation system obtains the input values for the specified partition at each clock cycle and the state values for the specified partition at intervals. Using the state and input values with a software model of the specified circuit design partition, the tool calculates the state values for the partition at every clock cycle. The software model may correspond to the partitioning information used to implement the circuit design across multiple configurable logic element devices, such as FPGAs. Thus, each software model may correspond to the portion of a circuit design emulated on a discrete FPGA integrated circuit.

Abstract: A synthesizer or emulator processes a gate level IC design derived from an RTL design to produce a gate level dump file indicating how signals of the gate level design behave. The gate level dump file is converted into an RTL dump file indicating how signals of the RTL design behave. A debugger processes the RTL dump file to produce displays depicting the RTL design and behavior of signals indicated by the RTL dump file. Thus while the IC is simulated or emulated at the gate level of the design to produce waveform data for a debugger, the gate level-to-RTL dump file conversion process enables a designer debug the more familiar RTL design based on the gate level simulation or emulation results. file conversion process enables a designer debug the more familiar RTL design based on the gate level simulation or emulation results.

Abstract: A method for designing a system LSI includes the steps of dividing an algorithmic description (D1) of the system LSI into software and hardware groups, synthesizing the hardware group by behavior synthesis to create an RTL description ((D5) and a simulation description (D6), examining the circuit scale of the system LSI based on the RTL description (D5), and simulating the system LSI based on the simulation description (D6) and a software description.

Abstract: A cable simulator that comprises an input device configured to receive a communication signal. The cable simulator further comprises a circuit configured to simulate attenuation in both the differential mode and common mode components of a communication signal.

Abstract: A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first-controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Abstract: System and method for automatically synchronizing multiple I/O devices with homogeneous and/or heterogeneous timing and I/O channel types. A graphical program specifying configuration and operation of a plurality of timed circuits, e.g., input circuits and/or output circuits, comprised on one or more I/O devices, may be created in response to user input, and executed to perform an I/O operation using the devices, where executing the program includes invoking software to: analyze the timed circuits to determine timing and triggering information for operation of the circuits, configure the circuits in accordance with the timing and triggering information, and operate the configured circuits to perform the operation. The analyzing may include determining the timed circuits, and one or more of: number, types, sharing, sources, exporting, and routing, of timing signals for each circuit, and starting/stopping orders for the circuits.

Abstract: The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.

Abstract: A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of scheduling a selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. The memory is utilized to store the plurality of adaptive computing descriptive objects and a plurality of adaptive computing circuit versions generated during the scheduling process. The selected adaptive computing circuit version is converted into a hardware description language, for fabrication into the adaptive computing integrated circuit.

Abstract: Apparatus and methods for integrated circuit (IC) design, including management of the configuration, design parameters, and functionality of a design in which custom instructions or other design elements may be controlled by the designer. In one exemplary embodiment, a computer program rendered in an object-oriented language implementing the aforementioned methods for designing user-customized digital processors is disclosed. Design iteration, component encapsulation, use of human-readable file formats, extensible dynamic GUIs and tool sets, and other features are employed to enhance the functionality and accessibility of the program. Components within the design environment comprise encapsulated objects which contain information relating to interfaces with other components in the design, hierarchy, and other facets of the design process.

Abstract: A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the one or more nodes by setting the first fattest variable to a primary value, and a first cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using an inverse of the primary value to generate a first cofactored binary decision diagram set. A second cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using the primary value to generate a second cofactored binary decision diagram set, and verification of the design is performed by evaluating a property of the second cofactored binary decision diagram set.

Abstract: A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.

Abstract: A method to simulate an electronic circuit includes determining process parameters and a process variation for each process parameter, and determining a value for each of a plurality of components of the circuit as a function of the process variations.

Abstract: Techniques are disclosed for automatically determining whether a potential constraint set to be applied to a portion of a circuit are overconstrained. An environment circuit supplies inputs to the circuit portion. Embodiments of the invention recognize that if the environment circuit produces a set of outputs that contain a pattern that is not present in the potential constraint set, then the potential constraint set is overconstrained. A verification tool establishes the properties for the environmental circuit based on the potential constraint set. If the verification tool determines that the outputs produced by the environment circuit conflict with the properties of the environment circuit, then the verification tool concludes that the potential constraint set is overconstrained, because the environment circuit produces a pattern that is not present in the potential constraint set.

Abstract: A design structure for a hybrid phase locked loop (PLL) circuit that obtains stabilized dynamic response and independent adjustment of damping factor and loop bandwidth is provided. The hybrid PLL circuit of the illustrative embodiments includes the resistance/capacitance (RC) filter elements of a conventional RC PLL and the feed-forward path from the output of the phase frequency detector to the voltage controlled oscillator (VCO). The hybrid PLL essentially enhances the performance of the conventional feed-forward PLL by providing the RC filter whose components can be weighted to provide a dynamic response that is significantly less sensitive to parameter variation and which allows loop bandwidth optimization without sacrificing damping.

Abstract: A method is provided to produce a model of an integrated circuit substrate, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; and connecting the mapped tile instances to each other to produce a tile grid that models overall electrical behavior of the substrate.

Abstract: A method of minimizing phase noise is provided. In operation, a first phase noise in a first circuit located on an integrated circuit is determined. Additionally, a second phase noise in a second circuit coupled to the first circuit but which is not located in the integrated circuit is determined, the second circuit being programmable. Further, the first phase noise is compared with the second phase noise. If the phase noises are about the same, it is determined that the noise source is from an algorithm of a random number generator, the second circuit is modified to optimize the performances of the integrated circuit, and the modified second circuit is copied to the first circuit. If the phase noises are different, it is determined that a source of the phase noise is at least one of a power supply coupling and a substrate coupling in the integrated circuit.

Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.

Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.

Abstract: In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access.

Abstract: A method and system for generating transistor models. In one embodiment, the method includes generating a transistor model that characterizes a topology of a circuit, and characterizes at least one coupling or at least one interaction between at least two transistors of the circuit.