Circuit Simulation Patents (Class 703/14)
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Publication number: 20090164194Abstract: Techniques are presented for determining effects of process variations on the leakage of an integrated circuit having multiple devices. The operation of the circuit is simulated using a first set of values for the process parameters for the devices and is also simulated with some of the process parameter values varied. For the simulation with the varied values, the circuit is split up into distinct components (such as channeled coupled components, CCCs), where each component has one or more devices, and a process parameters value in a device in each of two or more of these components is varied.Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Inventors: Sachin Shrivastava, Harindranath Parameswaran
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Patent number: 7552040Abstract: A method and system for modeling logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit block inputs that are connected to the logical circuit block output is taken into account by a transition time function and a delay time function that are each separately dependent on static capacitance and transistor gate capacitance and can be used to determine logical circuit block timing and output performance. A separate N-channel and P-channel gate capacitance may also be used as inputs to the transition time and delay time functions to provide further improvement, or a ratio of N-channel to P-channel capacitances may alternatively be used as input to the transition time and delay time functions.Type: GrantFiled: February 13, 2003Date of Patent: June 23, 2009Assignee: International Business Machines CorporationInventors: Barry Lee Dorfman, Thomas Edward Rosser, Jeffrey Paul Soreff
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Patent number: 7552042Abstract: Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to the integrated circuit for storage in the memory. The memory is accessed with the plurality of threads to concurrently process a plurality of the messages.Type: GrantFiled: January 30, 2004Date of Patent: June 23, 2009Assignee: Xilinx, Inc.Inventors: Gordon J. Brebner, Philip B. James-Roxby, Eric R. Keller, Chidamber R. Kulkarni
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Patent number: 7552406Abstract: A method and model for modeling a characteristic C that is distributed within a domain. A provided base equation expresses C as a function f of a variable V through use of N+1 parameters C0, C1, . . . , CN in the form C=f(C0, C1, . . . , CN, V), wherein N?1, and wherein C0, C1, . . . , CN are subject to uncertainty. A probability density function (PDF) is provided for describing the probability of occurrence of C0 in accordance with the uncertainty. Subsidiary equations expressing C1, . . . , CN in terms of C0 are provided. A value of C may be sampled by: providing a value V? of V; picking a random value C0R of C0 from the PDF; computing values C1R, . . . , CNR of C1, . . . , CN, respectively, by substituting C0R into the subsidiary equations; and calculating C by substituting C0R, C1R, . . . , CNR and V? into the base equation.Type: GrantFiled: February 22, 2007Date of Patent: June 23, 2009Assignee: International Business Machines CorporationInventors: Jeffrey B. Johnson, Bartholomew Martin, Jr.
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Patent number: 7552043Abstract: According to a method of simulation processing, a simulation model is received that includes a plurality of design entity instances modeling a digital system and one or more instrumentation entity instances, separate from the plurality of design entity instances, that generate instances of instrumentation events for testing purposes during simulation. In response to receiving an exclusion list identifying at least one instance of one or more instrumentation events to be removed from the simulation model, at least one instance of the one or more instrumentation events and associated logic elements are removed from the one or more instrumentation entity instances of the simulation model prior to simulation, such that a more compact simulation model is obtained.Type: GrantFiled: September 15, 2005Date of Patent: June 23, 2009Assignee: International Business Machines CorporationInventors: Gabor Bobok, Wolfgang Roesner, Matyas A. Sustik, Derek E. Williams
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Publication number: 20090157375Abstract: A power index computing apparatus that computes a power index for a circuit having one or more modules includes an obtaining unit that obtains estimated power consumption for a module in the circuit and a first computing unit that computes entropy based on a transition probability of an output signal of the module during a simulation period. The entropy is indicative of an expected value of a data volume output from the module, and the output signal is output to a destination that is external to the module. The power index computing apparatus further includes a second computing unit that computes a power index based on the estimated power consumption and the entropy, where the power index concerns power consumption for output of the output signal with respect to the estimated power consumption. An output unit of the power index apparatus outputs a result of the second computing unit.Type: ApplicationFiled: November 30, 2008Publication date: June 18, 2009Applicant: FUJITSU LIMITEDInventors: Tatsuya YAMAMOTO, Yutaka Tamiya
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Publication number: 20090152259Abstract: A layered heater structure including an electrode layer and a localized tuning method for tuning the electrode layer of a layered heater structure with high precision is provided. The localized tuning method tunes the electrode layer to its proper local resistance to minimize temperature offsets on the heater surface and thus provide a desired thermal profile that is in marked contrast to conventional, non-localized resistance tuning approaches based on thickness trimming practices, such as grinding or blasting, or resistivity adjustment, such as local heat treatment.Type: ApplicationFiled: December 17, 2007Publication date: June 18, 2009Inventors: Wei Fan, Benjamin J. Olechnowicz, Marc Schaepkens, David M. Rusinko, JR., Xiang Liu, John T. Mariner
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Patent number: 7549142Abstract: Devices and methods are provided that include advantages such as the ability to identify sizes, shapes and locations of frequently unwanted additional features that occur as a result of photolithographic interference. The additional feature information is obtained through use of simulation methods with reduced processing time or solving a system of equations. This allows a user to quickly find information about additional feature printing before the features are printed, and before the reticle is made.Type: GrantFiled: June 8, 2006Date of Patent: June 16, 2009Assignee: Micron Technology, Inc.Inventors: Husayn Alvarez-Gomariz, John R. C. Futrell
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Patent number: 7549069Abstract: Techniques are provided for characterizing processor designs and estimating power consumption of software programs executing on processors. A power model of a processor may be obtained by performing simulation using one or more training programs to obtain average power consumption during one or more windows of operation, then using the results to select parameters and coefficients for a processor characterization equation that can estimate power consumption while minimizing error.Type: GrantFiled: March 15, 2006Date of Patent: June 16, 2009Assignee: Fujitsu LimitedInventors: Toru Ishihara, Farzan Fallah
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Patent number: 7548843Abstract: Simulating network connections. A method includes generating a transaction by simulating a method model of a service model. The transaction includes representations of network interactions. A sequence of actions is created. The actions define network hardware activities including network actions performed by one or more source computer models, one or more network models, and one or more destination computer models. The sequence of actions is applied to network hardware device models to simulate network connectivity.Type: GrantFiled: April 10, 2006Date of Patent: June 16, 2009Assignee: Microsoft CorporationInventors: Efstathios Papaefstathiou, John M. Oslake, Pavel A. Dournov
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Patent number: 7548841Abstract: To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is early to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.Type: GrantFiled: November 12, 2002Date of Patent: June 16, 2009Assignee: Canon Kabushiki KaishaInventors: Yoshihiro Terashima, Hiroshi Nonoshita, Nobuyuki Yuasa
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Patent number: 7548842Abstract: A scalable system for verifying electronic circuit designs in anticipation of fabrication by compiling a hardware description to instructions for canvassing processors and instructions for circuit evaluation processors which are scalably interconnected to provide simulation and emulation, having deterministically scheduled transfer of circuit signal values among the large number of circuit evaluation processors.Type: GrantFiled: January 26, 2006Date of Patent: June 16, 2009Assignee: Eve S.A.Inventors: Subbu Ganesan, Leonid Alexander Broukhis, Ramesh Narayanaswamy, Ian Michael Nixon, Thomas Hanni Spencer
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Patent number: 7548792Abstract: An equivalent material constant calculation system that calculates an equivalent material constant of a structure constituted by a plurality of materials includes a shape data input portion that inputs shape data, a material data input portion that inputs material constant data, a dividing portion that divides the structure into a plurality of small regions, and a small region interior calculation portion that calculates equivalent material constants in the small regions, in which the small region interior calculation portion, based on the shape data and material constant data, with a function that includes a value in a variable that expresses a position in at least one direction in the small region, expresses an equivalent material constant for a region that is a portion of a small region, and using the function, calculates an equivalent material constant for the small region with respect to the at least one direction.Type: GrantFiled: March 21, 2008Date of Patent: June 16, 2009Assignee: Panasonic CorporationInventors: Yutaka Kumano, Tetsuyoshi Ogura, Toru Yamada
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Patent number: 7549135Abstract: A design methodology is disclosed for optimizing guard ring design by optimizing the guard ring to power supply path resistance value between physical and/or virtual injection sources in a CMOS circuit and the corresponding power supply. By comparing the calculated guard ring to power supply path resistance value to resistance criteria derived from specifications, elements that need further redesign are identified. Repeated redesign with several redesign options eventually lead to an optimized guard ring structure that provides area-efficient and sufficient latchup protection for the CMOS circuit.Type: GrantFiled: December 5, 2006Date of Patent: June 16, 2009Assignee: International Business Machines CorporationInventors: Phillip F. Chapman, David S. Collins, Steven H. Voldman
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Publication number: 20090150138Abstract: In an aspect of the present invention, a circuit analyzing method includes: generating an analysis object circuit model by connecting a package model as a lumped parameter circuit model of a package, a noise source model as a lumped parameter circuit model of a noise source circuit, a noise-receiving circuit model as a lumped parameter circuit model of a noise-receiving circuit, and a substrate model as a lumped parameter circuit model of a substrate between the noise source circuit and a noise-receiving circuit; and performing a circuit simulation to the analysis object circuit model to calculate a power supply voltage waveform in the noise-receiving circuit.Type: ApplicationFiled: December 5, 2008Publication date: June 11, 2009Applicant: NEC Electronics CorporationInventor: Susumu Kobayashi
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Publication number: 20090150324Abstract: One embodiment of the present invention provides a system that monitors a physical variable associated with an electronic component within a computer system. During operation, the system receives telemetry signals of the physical variable which are collected by one or more physical sensors associated with the electronic component. The system also collects electromagnetic interference (EMI) signals generated by the electronic component. Next, the system builds an inferential model for the physical variable by correlating the EMI signals with the telemetry signals. The system then uses the inferential model to infer values for the physical variable from the EMI signals.Type: ApplicationFiled: December 10, 2007Publication date: June 11, 2009Applicant: Sun Microsystems, Inc.Inventors: Ramakrishna C. Dhanekula, Kenny C. Gross, Aleksey M. Urmanov
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Publication number: 20090150137Abstract: A method for generating performance evaluation model may be provided which executes, by using first models of function modules which are described in a transaction level, a first simulation of system operation at the transaction level between the function modules, records transactions which are generated in the first simulation per function module, executes, by using second models of the function modules which are described in a hardware level, a second simulation of circuit operation of each of the function modules to determine a delay time of each function module of the recorded transactions, and assigns information of the delay time to the first model and generating a third model per function module.Type: ApplicationFiled: November 3, 2008Publication date: June 11, 2009Applicant: Fujitsu Microelectronics LimitedInventor: Yoichiro Kumazaki
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Patent number: 7546232Abstract: A method and apparatus for identifying sections of an existing schematic that are consistent with best design practices, the method comprising the steps of providing a template set, each template specifying a sub-set of components and relationships that are consistent with best design practices and examining the existing schematic to identify sections of the existing schematic that are inconsistent with the best design practices specified in the template set.Type: GrantFiled: August 18, 2005Date of Patent: June 9, 2009Assignee: Rockwell Automation Technologies, Inc.Inventors: Ruven E. Brooks, David W. Grooms
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Patent number: 7546559Abstract: A method for optimization of clock gating in integrated circuit (IC) design. Clock gating techniques are very useful in reducing the electrical power consumed by an IC. A general method for identifying registers that are candidates for clock gating is presented. Furthermore, a determination is made regarding which of the candidate registers to clock gate in order to achieve optimal power and IC area savings. The determination is based on switching activity of the candidate registers.Type: GrantFiled: May 22, 2006Date of Patent: June 9, 2009Assignee: Atrenta, Inc.Inventors: Bhanu Kapoor, Debabrata Bagchi, Nitin Sharma
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Patent number: 7546561Abstract: A system and method for determining scan chain correspondence including defining a reference scan chain having reference latches and a reference constraint, each of the reference latches having a reference latch logic cone, the reference constraint having a reference constraint logic cone and being associated with one of the reference latches; defining an implementation scan chain having implementation latches and an implementation constraint, each of the implementation latches having an implementation latch logic cone, the implementation constraint having an implementation constraint logic cone and being associated with one of the implementation latches; matching known corresponding scan points between the reference scan chain and the implementation scan chain; and determining scan chain functional correspondence between the reference latches and the implementation latches from the reference latch logic cones with any associated reference constraint logic cone and the implementation latch logic cones with anType: GrantFiled: May 25, 2006Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Travis W. Pouarz, Viresh Paruthi
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Patent number: 7546227Abstract: A method for generating a linear piecewise representation of a driver output current signal includes segmenting the driver output current signal such that an integral of each segment matches an actual voltage change in corresponding portion of an associated output voltage signal (within a desired tolerance). The beginning and ending current/time values for each segment can then be compiled into the piecewise linear representation of the driver output current signal. A method for generating a model driver output current signal includes conformally mapping first and second sets of precharacterization output current data based on a weighted average of the indexing parameter (e.g., input slew or output capacitance) values for the model driver output signal and the first and second sets of precharacterization data.Type: GrantFiled: July 31, 2008Date of Patent: June 9, 2009Assignee: Synopsys, Inc.Inventor: Harold J. Levy
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Patent number: 7546230Abstract: A model for modeling electromagnetic response in a conductor and in dielectric, a method of modeling the electromagnetic response in the conductor and dielectric and a program product therefor. Coupled supplies (delayed capacitive-current-controlled current sources or delayed inductance-voltage-controlled voltage sources) are low pass filtered in an electromagnetic model for the particular medium, e.g., a Partial Element Equivalent Circuit (PEEC) model for a conductor or dielectric. Thus, high frequency model instabilities are substantially reduced or eliminated.Type: GrantFiled: April 18, 2005Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Albert E. Ruehli, Chuanyi Yang
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Patent number: 7546566Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.Type: GrantFiled: April 5, 2007Date of Patent: June 9, 2009Assignee: Synopsys, Inc.Inventors: Harsh Chilwal, Srikanth Jadcherla, Sriram Kotni, Prapanna Tiwari
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Patent number: 7546231Abstract: A method and computer program for simulating a semiconductor integrated circuit is disclosed, in which a voltage coefficient of resistance according to a variation of width or length of a resistor device of the integrated circuit may be accurately applied to a model in a manner of including the length and width in variables for measuring the resistance of the resistor device and by which efficiency of a circuit design is considerably enhanced. The method generally includes the steps of measuring a plurality of resistances of a plurality resistors having different length (L) and width (W) from each other while varying a voltage applied to the resistors respectively, calculating a voltage coefficient resist (VCR) of the resistors using the measured resistances, the VCR expressed as a linear function of voltage, and calculating resistance of a certain resistor device having a specific length and width using the VCR.Type: GrantFiled: December 29, 2005Date of Patent: June 9, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Jin Soo Kim
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Publication number: 20090144042Abstract: A 3-D multi-physics design environment (“3-D design environment”) for designing and simulating multi-physics devices such as MEMS devices is discussed. The 3-D design environment is programmatically integrated with a system modeling environment that is suitable for system-level design and simulation of analog-signal ICs, mixed-signal ICs and multi-physics systems. A parameterized MEMS device model is created in a 3-D graphical view in the 3-D design environment using parameterized model components that are each associated with an underlying behavioral model. After the MEMS device model is completed, it may be exported to a system modeling environment without subjecting the model to preliminary finite element meshing.Type: ApplicationFiled: November 25, 2008Publication date: June 4, 2009Applicant: COVENTOR, INC.Inventors: Gunar LORENZ, Mattan KAMON
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Publication number: 20090144043Abstract: Disclosed is simulation of circuit behavior by running a central electronic core simulation in a high level simulator up to and including initial microload, creation of a post-IML (initial microcode load) state, and transferring the post-initial microcode state from the central electronic core simulation to the post-initial microcode load co-simulator.Type: ApplicationFiled: February 10, 2009Publication date: June 4, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Edward C. McCain
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Publication number: 20090144041Abstract: A method runs a simulation. The method comprises receiving a selection of a device. The device is one of a prober used in wafer testing and a handler used in package testing. The method comprises receiving at least one parameter for a set of parameters for the simulation. The method comprises running the simulation by executing commands to be performed as if the device were present. A controller supplies the set of commands. Results from the simulation indicate a performance of the controller.Type: ApplicationFiled: November 30, 2007Publication date: June 4, 2009Inventor: Larry Ira Goldsmith
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Patent number: 7543250Abstract: In some embodiments, multiple functional blocks (agents) in a complex integrated circuit are connected to a physically-distant shared resource (e.g. a memory controller) through packet buses which do not depend on establishing clock-cycle sequenced handshakes. On-chip repeaters including one or more register stages are used to segment the agent-shared resource interconnects into multiple segments, each shorter than a single-clock-cycle pathlength. The interconnects of multiple closely-spaced agents can be routed to the shared resource through an on-chip router having a single routed connection to the shared resource, for reducing the floorplan space taken by interconnects. The packet-based communications protocols do not require redesigning the agents or memory controller to make protocol changes accounting for the clock cycles inserted by repeaters and/or routers.Type: GrantFiled: November 18, 2005Date of Patent: June 2, 2009Assignee: NetXen, Inc.Inventors: Govind Kizhepat, Omar M. Kinaan
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Patent number: 7542891Abstract: Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor performance measure and one or more instance parameters that are available as inputs to a second, stress-insensitive, transistor model. The second transistor model may for example be the same as the first model, with its stress sensitivity disabled. Thereafter, a substitute stress analyzer can be used to determine a stress-adjusted value for the first performance measure, and the mathematical relationship can be used to convert that value into specific values for the one or more instance parameters. These values are then provided to the second transistor model for use in simulating the characteristics of the particular transistor during circuit simulation.Type: GrantFiled: September 7, 2006Date of Patent: June 2, 2009Assignee: Synopsys, Inc.Inventors: Xi-Wei Lin, Victor Moroz, Dipankar Pramanik
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Publication number: 20090138253Abstract: First, the position and the length of a harness are set. Next, a shape setting function having an unknown variable that minimizes potential energy as a binding position is generated, and a position of the minimum potential energy at a bending position is calculated in the Lagrange Multiplier Method. The position of the minimum potential energy obtained by the Lagrange Multiplier Method is the optimum binding position.Type: ApplicationFiled: August 11, 2008Publication date: May 28, 2009Applicant: FUJITSU LIMITEDInventors: Shinichi SAZAWA, Masayoshi Hashima
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Patent number: 7539960Abstract: An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. The elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.Type: GrantFiled: June 1, 2006Date of Patent: May 26, 2009Assignee: LSI CorporationInventors: Weiqing Guo, Sandeep Bhutani
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Publication number: 20090132062Abstract: Disclosed are apparatus and methods for embodiments for efficiently and flexibly controlling hardware devices in a semiconductor processing system are provided for use in a distributed control arrangement. In general, the distributed arrangement includes at least one upper-level controller that is configurable with a computer program sequence of instructions for controlling one or more hardware devices of a processing tool. The hardware devices are controlled through one or more lower-level controllers. Prior to execution of the program sequence of the upper-level controller, at least one instruction of this program is pre-compiled so as to translate the instruction for execution by a selected lower-level controller and to add an at least one interlock check to such pre-compiled instruction and make the translated instruction accessible to at least one lower-level controller. The interlock check specifies one or more condition(s) for the selected lower-level controller to execute the pre-compiled instruction.Type: ApplicationFiled: December 18, 2008Publication date: May 21, 2009Applicant: NOVELLUS SYSTEMS, INC.Inventors: Jaideep Jain, Qiang Zhou, Steve Kleinke
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Patent number: 7536288Abstract: According to a method of specifying a trace array for simulation of a digital design, one or more entities within a simulation model are specified with one or more statements in one or more hardware description language (HDL) files. In addition, a trace array for storing data generated through simulation of the simulation model is specified in one or more statements in the one or more HDL files. The HDL files may subsequently be processed to create a simulation model containing at least one design entity and a trace array within the design entity for storing trace data regarding specified signals of interest.Type: GrantFiled: December 31, 2003Date of Patent: May 19, 2009Assignee: International Business Machines CorporationInventors: Bradley Nelson, Wolfgang Roesner, Derek Edward Williams
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Patent number: 7536663Abstract: In one embodiment, a plurality of signals are sequentially driven onto a signal path. Each of the signals has a pulsewidth defined by a trigger edge and a sensor edge, and at least some of the signals having different pulsewidths. After driving each signal, the signal is sampled at or about a timing of the signal's sensor edge to thereby characterize the signal's sensor edge. The sensor edge characterizations corresponding to the different signals are then analyzed to quantify a timing error induced by an impedance variation of the signal path.Type: GrantFiled: February 25, 2005Date of Patent: May 19, 2009Assignee: Verigy (Singapore) Pte. Ltd.Inventor: Hiroshi Matsumiya
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Patent number: 7536289Abstract: A method of configuring an information processing system according to the present invention, in an information processing system for realizing one or a plurality of applications, comprises, a step of modeling all of the applications for each certain process level and inputting the models, a step of inputting parameters representing invariability for the inputted models, a step of using the models of the applications and the parameters representing invariability as inputted information and comparing the parameters representing invariability to a boundary condition, and a step of allocating one of the application models to programmable logic and another of the application models to an exclusive-use hardware based on a result of the comparison.Type: GrantFiled: March 4, 2005Date of Patent: May 19, 2009Assignee: Panasonic CorporationInventors: Kazuhiro Okabayashi, Minoru Okamoto
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Patent number: 7536377Abstract: Method and apparatus for component naming is described. Parameters (305) for a target component are obtained (201). The parameters (305) are hashed (202) to provide a hash value (203). The hash value (203) is used to construct a name (205) of the target component.Type: GrantFiled: December 18, 2003Date of Patent: May 19, 2009Assignee: Xilinx, Inc.Inventors: Roger B. Milne, Jeffrey D. Stroomer
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Publication number: 20090125292Abstract: A method for testing functionality of a chip checker is disclosed. The checker is arranged for generating a predetermined verification signal when the chip, upon receiving a predetermined input signal, generates a corresponding response signal. The method comprises the steps of developing a model of the chip, the model at least partially emulating at least one response of the chip by generating, upon receiving the predetermined input signal, the corresponding response signal. The method further supplies the developed chip model with the predetermined input signal. The checker is then used to test whether the generated response signal corresponds to the respective predetermined input signal. A failure of the checker to generate the predetermined verification signal indicates checker malfunction.Type: ApplicationFiled: November 12, 2007Publication date: May 14, 2009Inventors: Shridhar Narasimha Ambilkar, Girish Gopala Kurup
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Publication number: 20090119084Abstract: A simulation system includes a Response database for storing Response Data in which an output result of a device-under-test (DUT) model for a predetermined test item is set, and a framework for causing the test plan program to operate. The framework determines an output result of a DUT or a DUT model for a predetermined test item, which is executed based on the test plan program, based on the Response Data stored in the Response database. That enables a test flow to be verified in an offline simulation environment of the test equipment without loading a pattern program.Type: ApplicationFiled: November 5, 2007Publication date: May 7, 2009Applicant: ADVANTEST CORPORATIONInventors: Teruhiko Nagashima, Hajime Sugimura
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Publication number: 20090119085Abstract: Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.Type: ApplicationFiled: November 6, 2007Publication date: May 7, 2009Inventors: Yutao Ma, Min-Chie Jeng, Bruce W. McGaughy, Lifeng Wu, Zhihong Liu
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Patent number: 7529652Abstract: A method and apparatus are provided to model, analyze, and build linear time invariant systems with delays. The method and apparatus model a linear time invariant system as a linear fractional transformation of matrices of a delay free linear time invariant model with a bank of pure delays. The method and apparatus of the present invention can further accommodate input delays and output delays associated with the linear time invariant system with delays.Type: GrantFiled: July 19, 2007Date of Patent: May 5, 2009Assignee: The MathWorks, Inc.Inventors: Pascal Gahinet, Lawrence F. Shampine
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Publication number: 20090112549Abstract: Methods for generating realistic waveform vectors with controllable amplitude noise and timing jitter, simulatable in a computer-based simulation environment are disclosed. In one implementation, a transition vector is created from a sequence of bits having a rise time and a fall time, in which the transition vector comprises voltage values at timings corresponding to midpoints of transitions in the bit sequence. A jittered transition vector is created from the transition vector, in which the timing of the transitions in the jittered transition vector include timing jitter. An upscaled jittered transition vector is then formed having additional points, in which at least some of the additional points comprise corners of the sequence of bits. The voltages of the additional points are set by the sequence of bits, and the timing of the corners are set in accordance with the rise time and the fall time.Type: ApplicationFiled: October 29, 2007Publication date: April 30, 2009Applicant: MICRON TECHNOLOGY, INC.Inventor: TIMOTHY M. HOLLIS
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Publication number: 20090112556Abstract: Systems, method, and media for reconstructing data from simulation models are disclosed. Embodiments may include a method for accessing an alias from an alias file. The method may generally include searching for a net name and, if the net name is not found, searching an alias index file for an alias index entry associated with the net name, the alias index entry having a net name and an associated position. The method may also generally include, if the net name entry is found, accessing from an alias file an alias associated with the net name. A further embodiment may generally include receiving a net name and a position of an alias in the alias file, creating an alias index entry for the alias having a net name and the position of the alias, and storing the created alias index entry in the alias index file.Type: ApplicationFiled: January 2, 2009Publication date: April 30, 2009Applicant: International Business Machines CorporationInventors: Charles Lenier Alley, Anthony Joseph Bybell
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Publication number: 20090112552Abstract: At a simulation client, a design is simulated utilizing a hardware description language (HDL) simulation model by stimulating the HDL simulation model with a testcase. The HDL simulation model includes instrumentation not forming a portion of the design that includes a plurality of count event counters that count occurrences of count events in the design during stimulation by the testcase. At multiple intervals during stimulation of the HDL simulation model by the testcase, the simulation client records count values of the plurality of count event counters. The simulation client determines, for each of the multiple intervals, a temporal statistic regarding the count values of the plurality of count event counters and outputs a report containing temporal statistics for the multiple intervals.Type: ApplicationFiled: October 31, 2007Publication date: April 30, 2009Inventors: Michael L. Behm, Carol I. Gabele, Derek E. Williams
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Publication number: 20090112551Abstract: One or more embodiments of the disclosed computer-implementable method comprise a matrix-based approach to generating in parallel a plurality of realistic simulatable signal vectors, which vectors include the addition of amplitude noise and/or timing jitter and encoding. For example, each channel in a parallel bus can be populated in a matrix, with each row comprising ideal voltage values for the channel, and the columns comprising bits of the sequence of voltage values for that channel. Thereafter, encoding can be employed to modify the data in the matrix. Amplitude noise and/or timing jitter can then be applied to each channel (row) in the matrix. This modifies the time basis from a bit basis as used in the matrix to a time-step basis. With such modification accomplished, each row in the matrix can be transformed into simulatable vector, which vectors can then be simulated in parallel to test, for example, the robustness of the parallel bus of which the channels are part.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Applicant: MICRON TECHNOLOGY, INC.Inventor: TIMOTHY M. HOLLIS
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Publication number: 20090112550Abstract: A system and method for generating a worst case current waveform for testing of integrated circuit devices are provided. Architectural analysis of an integrated circuit device is first performed to determine an initial worst case power workload to be applied to the integrated circuit device. Thereafter, the derived worst case power workload is applied to a model and is simulated to generate a worst case current waveform that is input to an electrical model of the integrated circuit device to generate a worst case noise budget value. The worst case noise budget value is then compared to measured noise from application of the worst case power workload to a hardware implemented integrated circuit device. The worst case current waveform may be selected for future testing of integrated circuit devices or modifications to the simulation models may be performed and the process repeated based on the results of the comparison.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Inventors: Makoto Aikawa, Jonathan J. DeMent, Sang H. Dhong, Brian K. Flachs, Gilles Gervais, Iwao Takiguchi, Tetsuji Tamura
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Publication number: 20090112555Abstract: A design structure for an on-chip duty cycle measurement system may be embodied in a machine readable medium for designing, manufacturing or testing an integrated circuit. The design structure may embody an apparatus that measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. The design structure may specify that the DCM circuit includes a capacitor driven by a charge pump and that a reference clock signal drives the charge pump. The design structure may specify that the clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The design structure may specify that the DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store.Type: ApplicationFiled: December 31, 2008Publication date: April 30, 2009Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM CorporationInventors: David William Boerstler, Eskinder Hailu, Jieming Qi
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Publication number: 20090112553Abstract: An LCD display design system and method are disclosed. The method includes performing operations by a variety of operation modules after initial parameters are input and an operation type is selected, so as to generate operation results and transfer the operation results to an integration module; integrating the operation results by an integration module to generate a correspondence relation such as an operation window, a compare-table or an equation, and further transferring the operation results and the correspondence relation to an output module such that the output module can display performance variations of a variety of designs corresponding to the different initial parameters. Therefore, the present invention provides a user with a convenient way to obtain optimal design parameters for designing a display pixel circuit.Type: ApplicationFiled: July 18, 2008Publication date: April 30, 2009Inventors: I-Yin Li, Jean-Fu Kiang
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Test Bench, Method, and Computer Program Product for Performing a Test Case on an Integrated Circuit
Publication number: 20090112554Abstract: The disclosure relates to a test bench, method, and computer program product for performing a test case on an integrated circuit. The test bench may comprise a simulation environment representing an environment for implementing the integrated circuit and a reference model of the integrated circuit, wherein the reference model may be prepared for running within the simulation environment. The test bench may further comprise a device for running a simulation on the reference model within the simulation environment. The reference model may be based on an original reference model provided for a formal verification.Type: ApplicationFiled: October 8, 2008Publication date: April 30, 2009Applicant: International Business Machines CorporationInventors: Joerg Walter, Lothar Felten, Christopher Smith, Ulrike Schmidt -
Patent number: 7526739Abstract: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.Type: GrantFiled: July 13, 2006Date of Patent: April 28, 2009Assignee: R3 Logic, Inc.Inventor: Lisa G. McIlrath
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Patent number: 7526419Abstract: Methods for reconstructing data from simulation models are disclosed. Embodiments may include a method for accessing an alias from an alias file. The method may generally include searching for a net name and, if the net name is not found, searching an alias index file for an alias index entry associated with the net name, the alias index entry having a net name and an associated position. The method may also generally include, if the net name entry is found, accessing from an alias file an alias associated with the net name. A further embodiment of the method may generally include receiving a net name and a position of an alias in the alias file, creating an alias index entry for the alias having a net name and the position of the alias, and storing the created alias index entry in the alias index file.Type: GrantFiled: May 24, 2005Date of Patent: April 28, 2009Assignee: International Business Machines CorporationInventors: Charles Lenier Alley, Anthony Joseph Bybell