Abstract: A method and an apparatus to perform logic synthesis preserving high-level specification and to check that a common specification (CS) of two circuits is correct have been disclosed. In one embodiment, the method includes building a circuit N2 that preserves a predefined specification of a circuit N1. In some embodiments, the method includes verifying that N2 and N1 indeed implement the same specification and so they are functionally equivalent.

Abstract: A method, apparatus, and system in which a modeling tool made up of a testbench executable program validates behavior of one or more sub-components of an electronic system design modeled as one or more executable behavioral models and a transactor translates a behavior of the sub-components between one or more different levels of abstraction derived from a same design.

Abstract: A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for relating currents and voltages can be incrementally adapted from other designs or design elements in applications including mixed-signal, analog and RF (radio frequency) circuits.

Abstract: A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for relating currents and voltages can be incrementally adapted from other designs or design elements in applications including mixed-signal, analog and RF (radio frequency) circuits.

Abstract: A method, apparatus, and system in which a modeling tool made up of a testbench executable program validates behavior of one or more sub-components of an electronic system design modeled as one or more executable behavioral models and a transactor translates a behavior of the sub-components between one or more different levels of abstraction derived from a same design.

Abstract: Various embodiments are disclosed for transferring data between blocks in a design during simulation. Operation of at least one high-level block in the design is simulated in a high-level modeling system (HLMS). A hardware-implemented block in the design is co-simulated on a hardware simulation platform. A first vector of data received by a co-simulation block is transferred to the simulated hardware-implemented block via a transfer function.

Abstract: Disclosed is a SCSI target device simulator consisting of a personal computer, a SCSI host adapter board, and simulator software. The SCSI target device simulator is employed to test SCSI host adapter systems by simulating multiple SCSI target devices for test purposes. The simulated SCSI target devices may be configured to imitate a wide variety of different SCSI target device types, with an equally wide variety of configuration settings within a single SCSI target device type. A user may quickly create and change simulated SCSI target devices for a test system. The SCSI target device simulator may also be configured so that the simulated SCSI target devices respond in a specified manner to SCSI commands and SCSI task management commands. Controlling the simulated SCSI target device responses to SCSI commands and SCSI task management commands allows a user to easily configure and test a SCSI host adapter device for specific operational scenarios.

Abstract: A pin-based memory power modeling method using arc-based characterization includes steps as follows. All power arcs of a memory model are identified and characterized. A power arc is selected from the identified and characterized power arcs. Output bus switching power is computed by removing overlapping power using the selected power arc, and a temporary value for various input ramp times and output loads is derived. Output pin power for the selected power arc is calculated using the temporary value and a ratio of a number of output bits switching over an entire bus width. Switching power for the selected power arc is calculated by a power estimation tool based on port activity and an input intrinsic power value.

Abstract: A method for modeling the performance of memory address translation mechanism (MATM), comprises: a) receiving an execution profile that contains a memory address reference stream of an application, a set of page size mappings, and events about the application's data allocations and de-allocations; b) translating each memory reference in the input memory reference stream into a reference to the corresponding data object, by consulting the memory allocation and de-allocation events, to provide a data object reference stream; c) translating each data object reference into a corresponding page reference by consulting the page size mapping and by modeling the data allocation and de-allocation events in accordance with the mapping to provide a page reference stream and a number of pages of each page size that are needed by the respective mapping; d) using the page reference stream to provide a stream of reuse distance values; e) determining, for each reference in the reuse distance value stream, whether the referen

Abstract: Method and system for determining electrical isomorphism between two electrical networks are disclosed. In one embodiment, the method includes representing the circuit as a hierarchically-arranged set of branches. The hierarchically-arranged set of branches including a first branch that includes a first electrical network and a second branch that includes a second electrical network, where the first and second branches are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches. Next, the method determines whether the first and second electrical networks are electrically isomorphic networks. If the first and second electrical networks are determined to be electrically isomorphic networks, the first and second electrical networks are represented with a single electrically isomorphic network. The method further includes simulating the first and second electrical networks using the single electrically isomorphic network.

Abstract: Translating to a hardware description language (HDL) from an architecture description language (ADL) is disclosed. An architecture description that is written in the ADL and has a hierarchical organization is received. Decoders are generated, described in the HDL, from the architecture description written in the ADL. Control signals are generated, described in the HDL, from the architecture description written in the ADL. The decoders are configured to output the control signals and the control signals are input to functional units in order to preserve the hierarchical organization of the architecture description written in the ADL.

Abstract: Disclosed herein is a method of managing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, a restriction list associated with the HDL model is received. The HDL model has a maximum number of possible keyword/value pairs sets for which result data can be obtained, and the restriction list specifies a fewer number of keyword/value pair sets for which the result data can be queried based upon at least one keyword. In response to receipt of result data obtained by simulation of the HDL model, the result data are stored within a data storage subsystem by reference to the restriction list, such that particular result data attributable to each of the plurality of keyword/value sets is separately accessible.

Abstract: Methods and apparatus to minimize saturation in a ground fault detection device are disclosed. An example method includes connecting a capacitor simulator to a node of the ground fault detector device to prevent saturation, and monitoring power-line conductors for ground fault conditions with the ground fault detector device. An example apparatus to simulate a saturation capacitance in a ground fault device includes a sense coil induced by power-line conductors, and at least one of an amplifier or a current detector including an input connected to the sense coil and an output connected to a ground fault detector. The example apparatus also includes a saturation capacitor simulator connected to a node of at least one of the amplifier or the current detector to prevent saturation.

Abstract: A system and method models regional timeout functionality in a discrete event execution environment. A timeout function is initiated associated with an entity upon occurrence of a start condition and terminated or reset upon reaching an end condition. The timeout function is configured to expire after a selected amount of time. Upon expiration of the timeout function, the entity is redirected to a predetermined location for timeout processing.

Abstract: Systems and methods for simulating signal coupling in electronic devices are disclosed. In an exemplary implementation a computer program product executes a computer process to simulate a victim signal having a toggling bit pattern relative to a quiet culprit signal. The process also simulates a culprit signal having a toggling bit pattern relative to a quiet victim signal. The computer process generates test results for each simulation and combines the test results to determine effects of signal coupling in an electronic device.

Abstract: Methods and apparatus are provided for implementing a programmable device including a processor core and a hardware accelerator. A portion of a program written in a high-level language is automatically selected for hardware acceleration. Dedicated ports are generated to allow the hardware accelerator to handle pointer referencing and dereferencing. Profiling information is used to optimize selection of code for hardware acceleration.

Abstract: A computer-executable method for analyzing a condition of a computer system comprises executing an operating system on a processor according to an operating system image resident in a memory, and executing an analysis engine independently of the operating system on the processor in co-existence with the operating system. The analysis engine is enabled complete access to information relating to the processor and the operating system. The operating system is prevented access to the analysis engine.

Abstract: A method for generating and evaluating a table model for circuit simulation in N dimensions employing mathematical expressions for modeling a device. The table model uses an unstructured N-dimensional grid for approximating the expressions.

Abstract: The invention has an object to provide a method for simulating power voltage distribution of a semiconductor integrated circuit, by which it is possible to attempt to shorten the time required for preparing a power unit model and it is possible to carry out a highly accurate simulation with uneven distribution of a floor plan taken into account. In Step S1, design information (Core size CS, core ring width CW, block shape BS, macro shape MS, block current BI, macro current MI, etc.) is inputted into a simulator. In Step S2, information regarding a floor plan (Block position BP, macro position MP, power I/O position IOP) is inputted into the simulator by a designer. In Step S3, the power unit management table is initialized, and resistance modeling and current source modeling are also carried out. In Step S5 (FIG. 1), the static IR drop is calculated based on the power unit management table CT obtained in Step S4.

Abstract: The present invention provides an electronic circuit analyzing apparatus for evaluating the reliability value of an analysis result, an electronic circuit analyzing method, and an electronic circuit analyzing program. The electronic circuit analyzing apparatus comprises an input information storage unit 1 that stores input information, an analytic model creation unit 12 that creates an analytic model of an electronic circuit on the basis of the input information, an analysis unit 3 that calculates an analysis result of the electronic circuit using the analytic model, a partial model reliability value database 21 that defines the accuracy of each part of the analytic model and stores the accuracy value as a partial model reliability value, a partial model influence database 22 that defines the magnitude of influence of each part of the analytic model and stores the influence value as a partial model influence, a reliability value evaluation unit 23 that calculates an analysis result reliability value, i.e.

Abstract: The LSI design and development in manufacture is actualized by algorithm design, architecture design, actual hardware and software design, and verification. Herein, the architecture design contains a simulation program structuring process and a bus performance evaluation process, which are interconnected by a feedback loop. In the algorithm design, sources are described by the general-purpose high-level language such as the C language and C++ language. In the simulation program structuring process, the sources are subjected to isolation of the hardware and software, while an evaluation function is created to count bus traffic of the bus interconnecting the hardware and software. Every time data is written to a pre-defined variable loaded onto the bus, the evaluation function is performed to modify the sources. Then, evaluation is performed on the performance of the bus, so that the bus traffic for its processing rate is finally produced.

Abstract: Method and apparatus for interfacing between a high-level modeling system and a hardware description language (HDL) co-simulation engine. A plurality of HDL co-simulation engine libraries are queried as to the capabilities of the engines. A co-simulation engine is selected based on the capabilities, and an instance of the engine is created. The selected co-simulation engine is configured, input logic vectors are provided to the selected HDL co-simulation engine, and the co-simulation engine is executed accordingly.

Abstract: An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

Abstract: An automatic digital-circuit design apparatus receives a control target model written in a design description language, generates a control target model represented by a finite state machine model, stores the generated control target model, receives a control specification model written in a design description language, generates a control specification model represented by a finite state machine model, stores the generated control specification model, generates a control apparatus synthesis model by composing the generated control target model and the generated control specification model, computes controllable simulation relation, stores the computed controllable simulation relation, determines whether the control apparatus synthesis model is a model capable of providing the control, generates a permissible operation model, stores the generated permissible operation model, determines a control rule, generates a control apparatus model represented by a finite state machine, and converts the control apparatus

Abstract: A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the one or more nodes by setting the first fattest variable to a primary value, and a first cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using an inverse of the primary value to generate a first cofactored binary decision diagram set. A second cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using the primary value to generate a second cofactored binary decision diagram set, and verification of the design is performed by evaluating a property of the second cofactored binary decision diagram set.

Abstract: A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.

Abstract: A method for simulating a complex system including a plurality of constituents is provided. The method includes constructing at least one complex system model, each system model including a hierarchised set of modelled constituents. The construction step includes, for each model, obtaining a multiple instance hierarchical model including at least one instance vector corresponding to a plurality of instances of one and the same modelled constituent, each instance vector being able to be located at any level of a hierarchical decomposition tree of the multiple instance hierarchical model. The construction step additionally includes, for each model, expanding the multiple instance hierarchical model into an expanded model by expansion of at least one instance vector included in the multiple instance hierarchical model.

Abstract: An indicating circuit for indicating network status includes a signal generating unit configured for being set in a kernel board, and an indicator circuit configured for being set in a device board. The signal-generating unit includes a logic circuit with two input terminals and an output terminal, a network IC with two output pins connected to the two input terminals of the logic circuit respectively for sending status signals to the logic circuit, and a micro control unit (MCU) for transmitting a network transmitting speed signal from the network IC. The indicator circuit has two input terminals, one is connected to the MCU of the signal-generating unit to receive the network transmitting speed signal and the other is connected to the output terminal of the logic circuit to receive a status signal for indicating the network status.

Abstract: An optimized interface for simulation and visualization data transfer between an emulation system and simulator is disclosed. In one embodiment, a method of transferring data between a simulator to an emulator across an interface, comprises updating a simulator buffer of the simulator to contain a desired input state for an emulation cycle. A target write to the interface is performed to indicate that the emulation cycle can proceed. The emulation cycle is completed using an instruction sequencer within the interface independent of the simulator.

Abstract: The present invention is directed to a diagnostic compiler for use with a pipeline analog-to-digital converter (ADC) having code sequences corresponding to stages thereof. In one embodiment, the diagnostic compiler includes a transition locator configured to determine transition locations for the code sequences. The diagnostic compiler also includes a characteristics indicator coupled to the transition locator and configured to provide at least one characteristic of the ADC based on the transition locations.

Abstract: A method is described in which design data are prescribed which stipulate a geometrical design for a component. The design is used to produce an altered geometrical design, for example through relocations in a region. For the two designs, assessment criteria are ascertained and compared. Depending on the comparison result, the unaltered design data are retained or are replaced with altered design data. This method is carried out for a plurality of cycles in succession in order to optimize the design.

Abstract: A system for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.

Abstract: Transmission line macromodels can be classified into main categories of delay-extraction and rational approximation. The exponential solution of the Telegrapher's Equation is used to create a system and method that enable a time-domain circuit simulator to automatically select the most appropriate macromodel for a given transmission line structure.

Abstract: The present invention generally relates to hardware development and design, and in particular it relates to a method for simulating hardware. A meta model (22) is compiled for integrating a plurality of n different instantiations (12A, . . . 12N) of the same hardware model, and facilities and signals of different instantiations are resolved by instantiation-specific name space specifications in a code switch (24,26). Thus, computing time is saved because by simulating the meta model, the processor resources, for instance, storage spaces, are utilized more efficiently.

Abstract: A method of modeling statistical variation of field effect transistors having fingers physically measures characteristics of existing transistors and extracts a scaled simulation based on the characteristics of the existing transistors using a first model. The method creates synthetic single finger data using the scaled simulation. The method physically measures characteristics of existing pairs of matched transistors and extracts random dopant fluctuations from the characteristics of the existing pairs of matched transistors using a second model that is different than the first model. The method extracts a single finger from the synthetic single finger data and the random dopant fluctuations using the first model. The method can also create an ensemble model by determining the skew between a typical single device model and a typical ensemble model. The method adjusts parameters of the first model to cause the single finger to match targets for the single finger.

Abstract: A system, method, and apparatus select state variables for, build state equations of, and simulate time-domain operation of an electronic circuit. The circuit is modeled with three branch types (inductor, resistor, voltage source in series; capacitor, resistor, current source in parallel; and switch), including four pre-defined switch types (unidirectional unlatched, bidirectional unlatched, unidirectional latched, and bidirectional latched). Automated analyses determine efficient state variables based on the currently active circuit topology, and state equations are built and applied. Switching logic determines when switch states change, and state equations for the new topology are either drawn from a cache (if the topology has already been processed) or derived anew. The switch control signals may be combined into a single switching variable, defined as a function of the state output.

Abstract: An attribute of a hardware feature to be customized in a soft core is parameterized so that a value received from a user can be used to generate a description of a circuit containing the customized hardware feature. The generated description also describes, in accordance with the invention, a register that is indicative of the customization. For example, the generated (customized) description may describe the register as containing the value. After the circuit is created, the register may be read (at any time) to identify the customization. Hence, access to such a register eliminates the need for a user to maintain documentation on values specified during customization. Such a register may additionally be used to identify a device driver that is appropriate for use with the customized hardware feature. Additional registers may be included in the generated description, e.g. to identify the function of the circuit, and the version number.

Abstract: Embodiments of the present invention include a system for accessing a memory device comprising a master device coupled to a first serial bus. The system further comprises a slave device coupled to a second serial bus wherein the slave device comprises a first memory. The system further includes a slave device simulator coupled to the first serial bus and coupled to a long distance system specific interconnection, wherein the slave device simulator comprises a first shadow memory of the first memory and wherein a master device simulator is coupled to the second serial bus and coupled to the system specific interconnection. The master device comprises a second shadow memory of the slave device. Data read operations of the master may be satisfied directly from the slave device simulator shadow memory. Data writes from the master are propagated to the slave device and data coherency routines update the shadow memories accordingly.

Abstract: A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.

Abstract: A modeling system for modeling integrated circuits includes a process variation generator for generating a first statistic distribution of a process parameter; a performance parameter distribution generator for generating a second distribution of a performance parameter; a stress generator for generating a third statistic distribution of the performance parameter under a stress condition; and a circuit simulator for receiving data randomly generated based on the first, the second and the third distributions and for generating a statistic distribution of a target performance parameter.

Abstract: A method, data processing system, and computer program product are provided for performing time-based symbolic simulation. A delay-aware representation of a circuit is created that includes a plurality of circuit nodes. The data-aware representation is simulated. In particular, the simulator simulates transitions from a first set of circuit nodes to a second set of circuit nodes selected from the plurality of circuit nodes, the simulating based on executing a first set of simulation events. A second set of simulation events is then generated in response to executing the first set of simulation events. During the simulation, a time is computed for each of the transitions. An an event scheduling diagram is constructed during simulation. The event scheduling diagram depicts the transitions and the times of the transitions.

Abstract: This invention provides directional connectivity described by the interconnections of the blocks in the schematic or netlist that are used to propagate impedance data from one block to another. The propagation of impedance data for discrete time based simulation programs allow for the simulation under less than ideal termination conditions between the blocks. This invention also supports functionality where the input impedance and output impedance of each block are not perfectly terminated. This assumption can lead to very significant modeling errors in the simulated results. In general, termination impedances are complex frequency dependent functions that result in frequency dependent mismatch losses between the blocks. This invention allows for the propagation and calculation of impedance mismatches between the various blocks.

Abstract: Various approaches for controlling simulation of an electronic system are disclosed. In one approach, at least one breakpoint block is instantiated in a high-level design. The breakpoint block has an associated breakpoint condition driven by at least one signal of the design, and the design further includes at least one simulation block and at least one co-simulation block. The simulation block is simulated on a software-based simulation platform, and the co-simulation block and the breakpoint block are co-simulated on a hardware-based co-simulation platform. Advancement of a clock signal to the co-simulation block on the hardware-based co-simulation platform is inhibited in response to satisfaction of the breakpoint condition. After inhibiting the clock signal, advancement of steps of the clock signal is controlled on the co-simulation platform in one of a plurality of user-selectable clock advancement modes.

Abstract: In one embodiment of the invention, parameter functions for a plurality of circuits in a subsystem are created. The subsystem has design constraints. Each one of the parameter functions corresponds to each one of the circuits. The parameter functions represent a relationship among design parameters of the subsystem. The design parameters include constraint and optimizing sets. Initial design points are selected on the parameter functions having a first sum of the constraint set and a second sum of the optimizing set such that the first sum satisfies the design constraints. New design points are selected on the parameter functions such that the second sum is improved within the design constraints.

Abstract: Co-simulation of a circuit design includes simulating a first subset of blocks of the circuit design on a software-based co-simulation platform, simulating a second subset of the blocks of the circuit design on a hardware-based co-simulation platform, and maintaining coherency for a memory block of the circuit design between a first representation of data in the memory block on the software-based co-simulation platform and a second representation of the data in the memory block on the hardware-based co-simulation platform. Coherency is maintained by managing mutually exclusive access to the memory block from the first subset of blocks and the second subset of blocks.

Abstract: A remote monitoring system is described which enables monitoring of flow meters or other scientific instruments from a remote location using the GSM cellular phone network. The system includes a wireless modem utilizing the GSM cellular phone network, a central processing unit, connection of a scientific instrument to the central processing unit, power supply (e.g. one or more batteries), and an enclosure for housing the components.

Abstract: A method for selecting and/or producing automation hardware which is appropriate or necessary for controlling and/or monitoring a technical process to be automated (10) according to an automation solution is provided. The method includes developing the description of the automation solution, analyzing this description with an analysis tool (20) and selecting and, where applicable, producing respective automation hardware on the basis of the analysis of the description.

Abstract: A first block, a second block, a shared memory, and a third block are generated in a circuit design in response to user input control. The first block is coupled to the second block, the second block is coupled to the shared memory, and the shared memory is coupled to the third block in response to user input control. During one cycle of a simulation, the second block, in response to the first block, accesses a set of scalar values in the shared memory using scalar accesses. During one cycle of the simulation, the set of scalar values is transferred between the second block and the first block. During the simulation, the shared memory is accessed by the third block using scalar accesses.

Abstract: There is disclosed a simulation model for designing a semiconductor device, comprising adding at least a part of a difference between a density of a carrier described in a quasi-static manner with respect to a voltage applied between electrodes at a first time and a density of the carrier described in a transient state at a second time before the first time to the carrier density at the second time in accordance with a running delay of the carrier between both the times to thereby describe the carrier density at the first time in the transient state with respect to a semiconductor element having the first and second electrodes. A current flowing between the electrodes is described as a sum of a current flowing between the electrodes in the quasi-static manner, and a displacement current between the electrodes.

Abstract: In one embodiment, the invention is a method for modeling electrical behavior of a packaged module having multiple integrated circuits (ICs), such as a multi-chip module (MCM). The method includes: (a) identifying one or more pin groups in the module, wherein a pin group comprises two or more buffers connected together and to a package-external pin, and (b) generating one or more corresponding unified behavioral models for the one or more pin groups based on the characteristics of the buffers of the one or more pin groups. The behavioral models are part of an integrated behavioral model file in accordance with the I/O buffer information specification (IBIS) standard.