Circuit Simulation Patents (Class 703/14)
  • Publication number: 20090281772
    Abstract: One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing at least one representative benchmark circuit, (2) establishing standard sensitization and measurement rules for delay and power for the at least one representative benchmark circuit and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation and (5) parsing and interpreting the data to produce at least one report.
    Type: Application
    Filed: February 3, 2009
    Publication date: November 12, 2009
    Applicant: Agere Systems, Inc.
    Inventors: Joseph J. Jamann, James C. Parker, Vishwas M. Rao
  • Publication number: 20090281781
    Abstract: A method, apparatus and program product are provided for performing a noise, timing, or other signal integrity simulation of a circuit under test. A simulation cache structure is accessed to retrieve cached simulation results for a first portion of the circuit under test. Simulation is performed on a second portion of the circuit under test to generate simulation results for the second portion. Simulation results are generated for the circuit under test by combining the simulation results for the second portion with the cached simulation results for the first portion.
    Type: Application
    Filed: May 6, 2008
    Publication date: November 12, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ronald D. Rose, Sanjay Upreti
  • Patent number: 7617084
    Abstract: Disclosed is a method, mechanism, and computer usable medium for simultaneous processing or debugging of multiple programming languages. A particularly disclosed approach provides a method and mechanism for resolving the issue of simultaneous debugging of hardware represented by an HDL, e.g., Verilog or VHDL, and software, e.g., represented by C, C++, SystemC code. This approach overcomes the problem of the HDL portion of the design being inaccessible when C, C++ or SystemC code is debugged.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: November 10, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Douglas J. Koslow, Leonardo Valencia, Mark Harris
  • Patent number: 7617467
    Abstract: Processor-implemented techniques for verifying ESD device connectivity in an IC include the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit; identifying ESD devices based at least in part on the input dataset; extracting devices and parasitic elements in at least a portion of the integrated circuit based at least in part on the input dataset; generating a file including connectivity information and dimensional characteristics for extracted devices and parasitic elements associated with at least the identified ESD devices in the integrated circuit; identifying at least one ESD test based on the identified ESD devices and on connectivity to the identified ESD devices; and performing a linear network analysis for each identified ESD test based at least in part on the file.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: November 10, 2009
    Assignee: Agere Systems Inc.
    Inventors: David Averill Bell, Che Choi Leung, Daniel Mark Wroge
  • Patent number: 7617085
    Abstract: According to a method of data processing, a data set including at least one entry specifying a signal group by a predetermined signal group name is received by a data processing system. In response to receipt of the data set, the entry in the data set is processed to identify the signal group name. Signal group information associated with an event trace file containing simulation results is accessed to determine signal names of multiple signals that are members of the signal group. Simulation results from the event trace file that are associated with instances of the multiple signals are then included within a presentation of simulation results.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: November 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Gabor Bobok, Wolfgang Roesner, Derek E. Williams
  • Patent number: 7617468
    Abstract: A computer increases coverage in simulation of a design of a circuit by processing goals for coverage differently depending on whether or not the goals are on input signals of the circuit. Specifically, goals on input signals are used to automatically formulate constraints (“directly-derived constraints”) on values of input signals in test vectors. Goals on non-input signals (e.g. internal/output signals) are used with correlations to automatically formulate more additional constraints (“correlation-derived constraints”), by use of goals on non-input signals. The correlations indicate which non-input signals are associated with which input signals. The correlations are received from, for example, a human designer of the circuit. Depending on the embodiment, one or more of the automatically derived constraints are used with human-supplied constraints, to generate test vectors e.g. using a constraints solver, such as a satisfiability (SAT) engine.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: November 10, 2009
    Assignee: Synopsys, Inc.
    Inventors: Shashidhar Anil Thakur, Rahul Hari Dani
  • Publication number: 20090276199
    Abstract: An inductive rotary joint for non-contact transmission of electrical energy between a stationary part and a rotating part of the rotary joint comprises a power generator for generating an alternating voltage or an alternating current, which feeds a load by means of a rotatable power transmitter. An electrical parameter on the primary side of the power transmitter is determined with a measurement means, and from this, the condition of another electrical parameter at the load is approximated by means of a functional unit. Regulation of the power generator is effected with this approximated value.
    Type: Application
    Filed: May 5, 2009
    Publication date: November 5, 2009
    Applicant: Schleifring und Apparatebau GmbH
    Inventors: Nils Krumme, Georg Lohr, Herbert Weithmann, Michael Bley
  • Patent number: 7613599
    Abstract: An integrated design environment (IDE) is disclosed for forming virtual embedded systems. The IDE includes a design language for forming finite state machine models of hardware components that are coupled to simulators of processor cores, preferably instruction set accurate simulators. A software debugger interface permits a software application to be loaded and executed on the virtual embedded system. A virtual test bench may be coupled to the simulation to serve as a human-machine interface. In one embodiment, the IDE is provided as a web-based service for the evaluation, development and procurement phases of an embedded system project. IP components, such as processor cores, may be evaluated using a virtual embedded system. In one embodiment, a virtual embedded system is used as an executable specification for the procurement of a good or service related to an embedded system.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: November 3, 2009
    Assignee: Synopsys, Inc.
    Inventors: Stephen L Bade, Shay Ben-Chorin, Paul Caamano, Marcelo E Montoreano, Ani Taggu, Filip C Theon, Dean C Wills
  • Patent number: 7613950
    Abstract: A method for testing floating point hardware in a processor while executing a computer program is disclosed. The method includes executing a first set of code of the computer program without employing the floating point hardware. The first set of code has a first floating point operation, thereby obtaining an emulated result. The method also includes executing the first floating point instruction utilizing the floating point hardware, thereby obtaining a hardware-generated result. The method also includes comparing the emulated result with the hardware-generated result.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: November 3, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: John W. Curry
  • Publication number: 20090271167
    Abstract: A method of analyzing power consumption for a DUT (device under test) that includes an integrated circuit or an electronic system includes: providing emulation data for states of the DUT in one or more time windows; determining operational mode values from the emulation data and a selection of operational modes that characterize circuit behavior in the one or more time windows; dividing each time window into one or more segments based on at least one power criterion; determining power-activity values for the one or more segments; determining power-consumption values for the one or more segments from the power-activity values; using the power-activity values and the power-consumption values to determine relative power activity across the one or more segments and adjusting the one or more segments to target high power activity over operational modes in the one or more time windows; and saving one or more values for power activity of the DUT in a computer-readable medium.
    Type: Application
    Filed: December 30, 2008
    Publication date: October 29, 2009
    Applicant: Cadence Design Systems, Inc.
    Inventors: Bing ZHU, Tsair-Chin Lin, Tung-sun Tung, Jingbo Gao
  • Publication number: 20090271166
    Abstract: Improved performance of simulation analysis of a circuit with some non-linear elements and a relatively large network of linear elements may be achieved by systems and methods that partition the circuit so that simulation may be performed on a non-linear part of the circuit in pseudo-isolation of a linear part of the circuit. The non-linear part may include one or more transistors of the circuit and the linear part may comprise an RC network of the circuit. By separating the linear part from the simulation on the non-linear part, the size of a matrix for simulation on the non-linear part may be reduced. Also, a number of factorizations of a matrix for simulation on the linear part may be reduced. Thus, such systems and methods may be used, for example, to determine current in circuits including relatively large RC networks, which may otherwise be computationally prohibitive using standard simulation techniques.
    Type: Application
    Filed: April 28, 2008
    Publication date: October 29, 2009
    Applicant: Sun Microsystems, Inc.
    Inventor: Douglas R. Stanley
  • Publication number: 20090265154
    Abstract: A method for simulating a circuit. The method includes, in response to a first mode change triggering event at a first time point and in response to a first data transfer triggering event at a second time point after the first time point, generating a random value of at least a first random value and a second random value. In response to the generated random value being the first random value, a first input value of an input of the circuit is assigned to an output of the circuit. In response to the generated random value being the second random value, an output value of the output of the circuit is maintained. In response to a second data transfer triggering event at a third time point after the second time point, a second input value of the input of the circuit is assigned to the output of the circuit.
    Type: Application
    Filed: April 16, 2008
    Publication date: October 22, 2009
    Inventors: John Joseph Bergkvist, JR., Serafino Bueti, Francis A. Kampf, Douglas Thomas Massey
  • Publication number: 20090265155
    Abstract: An initial reliability of a semiconductor device is predicted before the design layout of a semiconductor product.
    Type: Application
    Filed: April 20, 2009
    Publication date: October 22, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Shinji Yokogawa
  • Publication number: 20090265144
    Abstract: A method and apparatus for improving the fatigue life of a wobblefram utilized in a micro switch. The flexible circular wobblefram can be formed with a fixed edge and a solid center region utilizing a punch and die at elevated temperatures. An external lever can be attached to the solid center region of the wobblefram. The lever can be loaded and actuated to transmit motion from outside of the micro switch to a sealed internal mechanism in order to perform a switching function. Circular and/or sinusoidal shaped corrugations can then be added to the wobblefram and evaluated for performance utilizing a finite element analysis (FEA) model. The FEA model can precisely evaluate and optimize profile, number and height of the circular and/or sinusoidal corrugations. Such a wobblefram with circular and/or sinusoidal corrugations can achieve higher lifetime without affecting the operating characteristics of the micro switch.
    Type: Application
    Filed: April 22, 2008
    Publication date: October 22, 2009
    Inventor: Brian Speldrich
  • Patent number: 7606692
    Abstract: A method for analyzing a circuit design in preparation for a simulation. The method generally includes the steps of (A) marking each of a plurality of modules between a target module of the modules and a top module of the modules in a hierarchy of the circuit design as a first type by traversing upward through the hierarchy starting from the target module, (B) marking each of the modules as a second type where a parent module of the modules is marked as the first type by traversing downward through the hierarchy starting from the top module and (C) marking each of the modules as a third type where the parent module is not marked as the keep type by traversing downward through the hierarchy starting from the top module.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: October 20, 2009
    Assignee: LSI Corporation
    Inventors: Maurizio Spadari, Stefano Commodaro
  • Patent number: 7606693
    Abstract: A solution of a first set of equations of the time-varying electrical response of a circuit is determined between pairs of adjacent time points ti and ti+1 based on predicted electrical responses of the devices at time point ti+1 and as a function of the initial temperatures of the circuit devices at time point ti. A solution of a second set of equations of the time-varying temperature responses of devices of the circuit is determined (1) after each iteration of the first set of equations and as a function thereof or (2) at each time point ti+1 and as a function of the solution of the first set of equations at the time point to determine the corresponding temperature response of the circuit. The solutions of the first and second sets of equations at one or more of the points in time are displayed.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: October 20, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Min-Che Jeng, Yutao Ma, Zhihong Liu
  • Patent number: 7606694
    Abstract: A system for performing cycle accurate simulation of a circuit design can include a plurality of cycle accurate models, wherein each cycle accurate model is a software object representation of a hardware function, and a scheduler configured to execute each cycle accurate model at clock cycle boundaries determined during a simulation session.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: October 20, 2009
    Assignee: Xilinx, Inc.
    Inventors: Jorge Ernesto Carrillo, Satish R. Ganesan, Amit Kasat, Sivakumar Velusamy
  • Patent number: 7606165
    Abstract: A network troubleshooting framework is described. In an implementation, a method includes generating a first estimation of network performance by a simulator based on network settings obtained from a network, estimating the new performance under an alternative setting by providing the alternative setting to the network simulation and observing the simulation output, repeating the procedure for other alternative settings, and suggesting the alternative setting that improves network performance.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: October 20, 2009
    Assignee: Microsoft Corporation
    Inventors: Lili Qiu, Paramvir Bahl, Lidong Zhou, Ananth Rajagopala Rao
  • Patent number: 7606695
    Abstract: A system for evaluating a simulation includes a reference simulator configured to execute a simulation image to obtain golden data, a test simulator configured to execute the simulation image to obtain test data, and a comparator configured to generate a comparison result by comparing a portion of the golden data to a portion of the test data before the execution of the simulation image on the test simulator has completed.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: October 20, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Nasser Nouri, Victor A. Chang
  • Publication number: 20090259452
    Abstract: A simulation system includes electromagnetic field analyzing units that execute electromagnetic field analysis with respect to electromagnetic field analysis areas obtained by division of an area to be analyzed into the electromagnetic field analysis areas; one or more circuit analyzing units that execute circuit analysis with respect to a circuit unit in the area to be analyzed; and an aggregating unit that aggregates, from the electromagnetic field analyzing units, data for the circuit analysis by the one or more circuit analyzing units and transmits the data to the circuit analyzing units. The simulation system links plural processing units that mutually exchange data.
    Type: Application
    Filed: June 24, 2009
    Publication date: October 15, 2009
    Applicant: FUJITSU LIMITED
    Inventor: Atsushi TAKEUCHI
  • Publication number: 20090259453
    Abstract: A method of modeling an SRAM cell is provided. Initially, transistor models are provided based on transistor devices, and an SRAM cell model is provided including the transistor models. The present methodology streamlines the modeling process by modeling in order the pull up, pass gate and pull down transistors so as to minimize the number of transistor modeling iterations needed, and by focusing on the specific areas of transistor operation to achieve the desired level of operational accuracy. Variations to the model are provided, mimicking variations in data from actual devices, and yield based on failure estimation is measured using the model and its variations.
    Type: Application
    Filed: April 11, 2008
    Publication date: October 15, 2009
    Inventors: Vineet Wason, Ciby Thuruthiyil, Priyanka Chiney, Qiang Chen, Sriram Balasubramanian
  • Patent number: 7603646
    Abstract: Various approaches for generating an implementation of an electronic circuit design are disclosed. In one approach, one or more configuration bits that have don't care conditions are identified for a LUT block of a design. A dynamic power state for a subset of a first level of logic devices in the LUT block is determined as a function of each identified configuration bit that has a don't care condition. A dynamic power state for a subset of a second level of logic devices is determined as a function of the determined power state for the first level of logic devices. A respective value for each identified configuration bit of the LUT is selected in response to the determined dynamic power states. The respective value is placed into the design for each identified configuration bit.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: October 13, 2009
    Assignee: Xilinx, Inc.
    Inventors: Tetse Jang, Kevin Chung, Jason H. Anderson, Qiang Wang, Subodh Gupta
  • Patent number: 7603639
    Abstract: Designing integrated circuitry (“IC”) includes simulating noise of modeled IC operation and applying the noise to buffers of a clock tree of the modeled IC, responsively generating a first simulated clock tree output signal. Components of the first simulated clock tree output signal are scaled in a frequency domain responsive to their time domain variations at respective frequencies. A simulated, substantially noise-only, clock tree output signal is generated in a frequency domain, wherein some components are removed responsive to at least one clock signal frequency and scaled magnitudes of the components. A second simulated clock circuitry output signal is generated responsive to a transfer function of certain clock circuitry. A circuit structure or fabricating process is selected responsive to jitter of the second simulated clock circuitry output signal. The IC may be fabricated using the selected process and may include the selected structure.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: October 13, 2009
    Assignee: International Business Machines Corporation
    Inventors: Faraydon Pakbaz, Stephen Dale Wyatt
  • Publication number: 20090254323
    Abstract: Various embodiments of systems and methods are described in which system simulation techniques are combined with graphical programming techniques in a common environment. For example, various embodiments of the methods comprise displaying a graphical data flow diagram connected to a system diagram, e.g., where the graphical data flow diagram and the system diagram are displayed together in a compound diagram. In the displayed compound diagram, the graphical data flow diagram may be connected to the system diagram, e.g., by a line or wire. In one embodiment the wire may visually indicate that the graphical data flow diagram is executable to produce a value that is provided as an input signal for a simulation performed based on the system diagram. In another embodiment the wire may visually indicate that the graphical data flow diagram receives an output value from the system simulation as input.
    Type: Application
    Filed: June 16, 2009
    Publication date: October 8, 2009
    Inventor: Alain G. Moriat
  • Patent number: 7600169
    Abstract: Systems and methods for implementing test case generation with feedback are disclosed. An exemplary system for test case generation with feedback comprises a plurality of knobs identifying test values for a device under test. A plurality of buckets is each associated with at least one of the test values, each bucket having a weight value for the associated test value. A failure analysis module is operatively associated with the device under test, the failure analysis module changing at least some weight values based on feedback from test operations for the device under test. A test case generator selects test values for test operations based on the weight value for the associated test value.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: October 6, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Christopher Todd Weller
  • Patent number: 7599821
    Abstract: A method of simulating an analog mixed-signal circuit design using mixed-language descriptions includes initializing a mixed language simulation cycle, processing digital events during delta cycles at a current simulation time of the cycle, and, after the digital events are processed, determining an analog solution at the current simulation time.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: October 6, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Junwei Hou, Craig Winters
  • Patent number: 7599826
    Abstract: A system for generating various simulation conditions for simulation analysis is disclosed. The system includes: a signal generating module (301) for generating an N-bit binary sequence consisting of “1” and “0” according to signal source parameters; a application module (302) for applying the N-bit binary sequence to generate the various simulation conditions according to control parameters; a noise generating module (303) for generating N influence values of Gauss noises with N standard deviations to N signal bit-widths; and an addition module (304) for adding the Gauss noises to corresponding digital waveform positions of the generated simulation conditions. A related method is also disclosed.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: October 6, 2009
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Shou-Kuo Hsu, Cheng-Shien Li
  • Publication number: 20090248383
    Abstract: A method of simulating operation of a bitcell includes determining sensitivities of a bitcell model to different component characteristics and device parameters, such as device temperature, operating voltage, and process characteristics. The determined sensitivities are normalized, so that each normalized value represents the relative sensitivity of the bitcell, under the simulated device parameters, to the component characteristic associated with the value. The normalized sensitivity values can be scaled based on a tolerance factor, and the adjusted sensitivities used to model the behavior of each component of the bitcell in subsequent simulations.
    Type: Application
    Filed: March 25, 2008
    Publication date: October 1, 2009
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Russell Schreiber, Keith Kasprak, Donald A. Priore
  • Publication number: 20090248385
    Abstract: In a graphical modeling environment, bus signals, which group a plurality of signals together for simplifying a model, include a partial or complete physical definition. Models are simplified by passing bus signals through graphical objects representing functional entities, without degrouping the bus signal. During simulation of the model, code can be generated for the bus signal having a complete definition independent of other components of the graphical model.
    Type: Application
    Filed: May 18, 2009
    Publication date: October 1, 2009
    Applicant: THE MATHWORKS, INC.
    Inventors: Peter SZPAK, Matthew ENGLEHART
  • Publication number: 20090248384
    Abstract: A process control system is disclosed in an automation installation having field devices which are networked by means of a system bus and which can be operated using associated system control units which are connected by means of a terminal bus to at least one central engineering computer for configuring the system and to a central control station for monitoring and operating the system. For the purpose of linking at least one extraneous control unit to the terminal bus an interposed control computer is proposed which, under software control, simulates a system-compliant I/O unit on the terminal bus, which I/O unit is bi-directionally connected to an OPC client residing on the extraneous control unit.
    Type: Application
    Filed: March 19, 2009
    Publication date: October 1, 2009
    Applicant: ABB AG
    Inventor: Michael Gienke
  • Patent number: 7596482
    Abstract: Determining ampacity risks in a circuit comprises receiving geometry data of the circuit, initializing boundary conditions, initializing circuit geometry assumptions, modeling the circuit geometry data as a three-dimensional solid, computing non-Fourier heat conduction through the three-dimensional solid model using conjugate gradient numerical analysis with an incomplete Cholesky preconditioner, and generating an output indicative of a location in the three-dimensional solid model where potential thermal damage may occur in response to a predetermined excitation.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: September 29, 2009
    Assignee: Dell Products L.P.
    Inventors: Rajen J. Murugan, Sarat Kirshnan
  • Patent number: 7596775
    Abstract: IC design flow includes RTL design, synthesis, APR, and layout. An IC designer can choose a suitable standard cell for an integrated circuit according to the timing, area, and BCI (best cell index) of each standard cell. Further, the BCI of a standard cell can be generated by generating critical dimensions of a standard cell in a plurality of surroundings, generating a plurality of circuit parameters corresponding to the plurality of surroundings, calculating the differences of the plurality of circuit parameters and the ideal circuit parameter of the standard cell, and analyzing the distribution of the differences.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: September 29, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Dar-Sun Tsien, Chien-Kuo Wang, Chen-Hsien Hsu, Wei-Jen Wang
  • Patent number: 7596772
    Abstract: A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: September 29, 2009
    Assignee: Faraday Technology Corp.
    Inventors: Hanping Chen, Chih-Yang Peng, Alvin Hsin-Hung Chen, Jia-Jio Huang, Jim Jyh-Herng Wang, Kun-Cheng Wu
  • Patent number: 7596483
    Abstract: The present invention is directed to determining the timing for a synchronous integrated circuit, the circuit including a multiplicity of clocked elements interconnected by signal paths. Predictions are formed for timing delays in said signal paths in the integrated circuit. A first such path is selected, wires are traced in the integrated circuit forming the path, hereinafter referred to as victim wires, and adjacent and crossing wires thereto, hereinafter referred to as aggressor wires, are determined. For each aggressor wire, the amount of electromagnetic coupling to the victim wires of the first path is determined. The aggressor wires are divided into a plurality of categories depending on the clocked timing of the aggressor wires in relation to the clocked timing of the victim wires.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: September 29, 2009
    Assignee: LSI Corporation
    Inventor: William Eric Corr
  • Publication number: 20090236701
    Abstract: A chip arrangement is disclosed. The chip arrangement includes a first chip, a first bond wire having an inductive element and coupled with the first chip at its one end and an inductivity compensation structure including a first conductive plate coupled with the first bond wire at the other end of the first bond wire, and a second conductive plate arranged in parallel to the first conductive plate, wherein the first conductive plate and the second conductive plate are configured such that a resonant condition for a partial circuit formed by the first bond wire and the inductivity compensation structure is formed to compensate for the inductive element of the first bond wire. A method of determining an inductivity compensation structure for compensating a bond wire inductivity in a chip arrangement is also disclosed.
    Type: Application
    Filed: March 18, 2008
    Publication date: September 24, 2009
    Applicant: Nanyang Technological University
    Inventors: Mei Sun, Yue Ping Zhang
  • Publication number: 20090240362
    Abstract: A simulation model creating method computes, for measurement results of a line width of a resist pattern formed with varied an exposure amount and focus value, a permissible fluctuation range of the pattern line width from a distribution of the exposure amount and a distribution of the focus value; computes difference values between the measurement results and corresponding approximation values on a fitting function which has the exposure amount and focus value as parameters; compares the difference values with the permissible fluctuation range; deletes any measurement values for which the difference value is larger than the permissible fluctuation range, and recomputes the fitting function accordingly; and deletes measurement values outside a permissible fluctuation range of a pattern line width of the mask, and creates a simulation model.
    Type: Application
    Filed: March 18, 2009
    Publication date: September 24, 2009
    Inventors: Shoji Mimotogi, Masafumi Asano
  • Patent number: 7594206
    Abstract: The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor integrated circuit using a fault list corresponding to information on sites in the semiconductor integrated circuit where a fault is likely to occur or information required to reduce such faults. In addition, the fault detecting method and the layout method perform ordering of faults with their likelihood and weighting of the faults, taking into consideration physical information on a mask pattern within a chip or records of actual use of cells or functional blocks.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: September 22, 2009
    Assignee: Panasonic Corporation
    Inventors: Takaki Yoshida, Reisuke Shimoda
  • Patent number: 7594208
    Abstract: Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: September 22, 2009
    Assignee: Altera Corporation
    Inventors: Terry Borer, Ian Chesal, James Schleicher, David Mendel, Mike Hutton, Boris Ratchev, Yaska Sankar, Babette van Antwerpen, Gregg Baeckler, Richard Yuan, Stephen Brown, Vaughn Betz, Kevin Chan
  • Publication number: 20090234602
    Abstract: Disclosed is a method including: calculating power supply input impedance of the LSI from the number of output buffers of the LSI, output impedance of an output buffer, signal characteristic impedance and characteristic impedance of power supply/ground of an LSI terminal, a package, and a chip terminal part, characteristic impedance of wiring connected to an LSI output terminal, and output signal damping resistance calculating a reflected voltage of power supply noise at a semiconductor device mounted on an electronic circuit board, based on impedance characteristic between a power supply and ground of the semiconductor device; and analyzing power supply noise of the electronic circuit board, based on the reflected voltage of the power supply noise at the semiconductor device.
    Type: Application
    Filed: March 10, 2009
    Publication date: September 17, 2009
    Inventor: KAZUHIRO KASHIWAKURA
  • Publication number: 20090234605
    Abstract: Disclosed is a method of analyzing power supply noise including: extracting power supply and ground information as well as a capacitor and an LSI chip connected to a power supply and ground from electronic circuit design information; creating an analytical model of power supply noise by connecting respective models of the impedance characteristics of the capacitor and LSI chip to mounting positions of a board model; calculating reflected voltage at the LSI chip based on an impedance characteristic between the power supply of LSI chip and ground; calculating power supply noise from the LSI chip to the electronic circuit board; based on the reflected voltage at the LSI chip.
    Type: Application
    Filed: March 10, 2009
    Publication date: September 17, 2009
    Inventor: KAZUHIRO KASHIWAKURA
  • Publication number: 20090234631
    Abstract: A linear time-invariant system modeling apparatus comprises a processing resource arranged to receive, when in use, model data constituting to a model of a linear time-invariant system. The model data includes residual value data and scattering data. The processing resource is arranged to perform, when in use, a single value decomposition in respect of the scattering data; the scattering data corresponds, when expressed in matrix form, to a scattering matrix in a state-space representation of the model. The processing resource is also arranged to use, when in use, a result of the single value decomposition in order to generate residual value modification data. The residual value modification data is applied to the residual value data, the residual value data corresponding, when expressed in the matrix form, to a residual value matrix in the state-space representation of the model.
    Type: Application
    Filed: March 13, 2008
    Publication date: September 17, 2009
    Applicant: AGILENT TECHNOLOGIES, INC.
    Inventors: Nobby Stevens, Tom Dhaene
  • Publication number: 20090234630
    Abstract: The invention concerns a method for verifying, prior to fabrication, the proper operation of integrated circuit electronic systems using analog signals. It comprises the following steps: identifying (22) the noise-sensitive circuits, setting an acceptable sensitivity template for these noise-sensitive circuits, identifying (34) the noise-generating circuits, modeling the noise, determining (50) the function for transferring noise to the sensitive circuits, and comparing (58) the level of noise reaching the sensitive circuits to an acceptable sensitivity threshold template for the sensitive circuits.
    Type: Application
    Filed: July 28, 2006
    Publication date: September 17, 2009
    Inventor: Francois Clement
  • Publication number: 20090234777
    Abstract: An apparatus, method, and program product are provided to predict yield loss associated with performance screens or leakage screens. A leakage model is correlated to an on-chip measurement. Current limited yields are determined from the leakage model. A database is formed relating performance sigma cut-points to the circuit limited yields. A product is quoted based on the circuit limited yield for one of the performance sigma cut-points taken from the database. The quote is tied to the product design and testing.
    Type: Application
    Filed: March 11, 2008
    Publication date: September 17, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas S. Barnett, Jeanne Paulette Spence Bickford, Nazmul Habib, Susan K. Lichtensteiger, Raymond J. Rosner
  • Patent number: 7590518
    Abstract: Method of forming a reduced model of a circuit. A circuit parameter is selected, and a plurality of values for the parameter are selected. A circuit or operator equation is solved for the selected plurality of values to generate a result. The acts of selecting parameter and its plurality of values and solving the equation are repeated to generate sufficient results to form a reduced model. For each iteration, a rank revealing factorization is performed on the matrix for use in determining whether a sufficient number of results or vectors have been generated to form the reduced model so as to form a reduced model. In the plurality of values for a selected parameter, there may exist large deviation between two of the plurality of values for a selected parameter, and such deviation need not be based upon a nominal point or deviation thereof.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: September 15, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Joel R. Phillips
  • Patent number: 7587688
    Abstract: Users or applications provide optimization information that specifies performance-critical portions of the design. Users can identify performance-critical portions of their designs from a priori evaluation of their design or by analyzing the results of previous compilations of their design or similar designs. An application may extract and analyze performance information from previous compilations of the design or similar designs to automatically specify the performance-critical portions of the design. The compilation software uses this specification to focus the appropriate types and amount of optimization on different portions of the design. The compilation software may use additional optimization techniques and/or may allocate additional computing resources to optimize the performance of performance-critical portions of the design. Other portions of the design that are not performance-critical may be optimized using balanced optimization techniques.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: September 8, 2009
    Assignee: Altera Corporation
    Inventors: Babette Van Antwerpen, Jinyong Yuan, David Karchmer
  • Publication number: 20090222250
    Abstract: The present invention provides a hard/soft cooperative verifying simulator based on a SystemC simulator, capable of reducing overhead of context switching control thereby to shorten processing time. Time keepers for controlling simulation times of a plurality of threads are provided corresponding to the threads generated as simulation models for hardware and software. Each of the time keepers has a variable which holds a simulation time for each thread, a variable which holds a summation time, and a break request queue which stores a break time and its corresponding break method therein. The time keeper manages both variables and the queue in response to six types of method invocations from the thread, and invokes a wait function of the SystemC simulator when necessary. It is thus possible to reduce the number of times that a wait function invocation is performed, and shorten the entire processing time.
    Type: Application
    Filed: February 28, 2008
    Publication date: September 3, 2009
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Noriyoshi ITO
  • Publication number: 20090222776
    Abstract: A device for designing a sensor arrangement for an automated system, the device comprising a first input unit for receiving a specification of a plurality of sensor measurements to be carried out by the sensor arrangement, a second input unit for receiving a specification of a confidence region together with an associated confidence level for each of the specified sensor measurements, a third input unit for receiving a specification of a target confidence level for the automated system, and a configuration unit for configuring the plurality of sensor measurements and for configuring the combination of the sensor measurements in a manner to guarantee the target confidence level for the automated system.
    Type: Application
    Filed: November 22, 2006
    Publication date: September 3, 2009
    Applicants: MULTITEL ASBL, FACULTE POLYTECHNIQUE
    Inventors: Francois Meers, Marc Massar, Olivier Bilenne, Emmanuel Druet
  • Publication number: 20090222251
    Abstract: A design structure for a integrated circuit interfacing system may be embodied in a machine readable medium for designing, manufacturing or testing a integrated circuit. In one embodiment, the design structure specifies an integrated circuit that includes multiple interfaces. The design structure may specify that each of the interfaces couples to a respective set of registers or storage elements on the integrated circuit. The design structure may also specify a bridge circuit on the integrated circuit that switchably couples the two interfaces together such that one interface may communicate with the registers that associate with that interface as well as the registers that associate with the other interface.
    Type: Application
    Filed: December 31, 2008
    Publication date: September 3, 2009
    Applicant: International Business Machines Corporation
    Inventors: Tilman Gloekler, Ingemar Holm, Ralph C. Koester, Mack Wayne Riley, Shoji Sawamura, Iwao Takiguchi
  • Patent number: 7584450
    Abstract: One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a first area in a first layout, wherein the first area is associated with a first feature. Next, the system determines a first sample using the first check-figure, wherein the first sample represents the first layout's geometry within a first ambit of the first check-figure, wherein the first sample's geometry is expected to affect the shape of the first feature. The system then performs a model-based simulation using the first sample to obtain a first simulation-result which indicates whether the first feature is expected to have manufacturing problems. Next, the system stores the first simulation-result in a database which is used to quickly determine whether a second feature is expected to have manufacturing problems.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: September 1, 2009
    Assignee: Synopsys, Inc.
    Inventors: Zong Wu Tang, Daniel N. Zhang, Juhwan Kim, Hua Song, Weiping Fang, Lawrence S. Melvin, III
  • Publication number: 20090216515
    Abstract: Some embodiments of the present invention provide a system that profiles a serial simulation of a circuit to estimate the performance of a parallel simulation of the circuit. During operation, the system profiles execution of module instances during a serial simulation of the circuit, wherein each module instance includes code which simulates signal propagation through a corresponding circuit module. Next, the system uses execution times for the module instances obtained from the serial simulation to estimate the performance of a parallel simulation of the circuit.
    Type: Application
    Filed: February 27, 2008
    Publication date: August 27, 2009
    Applicant: Synopsys, Inc.
    Inventor: Philip R. Moorby