Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.

Abstract: A method of modeling the output drivers in an integrated circuit, for example a serializer/deserializer circuit, is provided. In accordance with embodiments of the invention, at least one parameter of the circuit is physically measured and a behavioral model utilizing that parameter is constructed. The behavioral model can then be utilized to predict the behavior of the integrated circuit output drivers.

Abstract: Single hardware subsystems that present two software views that appear to be two separate hardware subsystems attached in a hierarchy are implemented with PCI-type arrangements. According to an example embodiment of the present invention, a hardware arrangement is adapted to emulate two virtually separate hierarchical subsystems in a single hardware block. This emulation facilitates the coupling of devices to PCI Express-type communications links while addressing PCI-Express-type linking requirements for such devices.

Abstract: Co-simulation of an electronic circuit design using an embedded processor on a programmable logic device (PLD). The programmable logic resources of a PLD are used to perform hardware-based co-simulation of a first portion of the electronic circuit design. Software-based co-simulation of a second portion of the electronic circuit design is performed using the embedded processor.

Abstract: A simulation/debugging method for SOC designs that utilizes initial memory values loaded into a simulation model. A test program is then executed, and incremetal transaction records are generated for each incremental memory access (e.g., data write operations). Each transaction record includes a timestamp, address and data values. The transaction record information is stored/captured on a high level-based (i.e., system address-based) domain that takes into account all the tiling, interleaving, scrambling, and unaligned accessing used in the simulated SOC design, rather than on a low level-based (i.e., physical memory address-based) domain. Upon completing the simulation, the instantaneous memory contents at any selected point in time during the simulated execution are calculated by combining the initial data and intermediate transaction record information. Automatic memory dump and sanity check tests verify the integrity of the final data value and incremental transactions.

Abstract: According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event as an outlying count event. While simulating a design utilizing the HDL simulation model, occurrences of the outlying count event are counted to obtain a count event value. Simulation result data obtained from simulating the design is then received and processed. In the processing, the count event value is recorded within a data storage subsystem responsive to a determination of whether or not the count event value of the outlying count event exceeds a previously recorded count event value.

Abstract: In an embodiment, a computer-implemented method for modeling a system using a finite state machine representation is presented. An event-driven temporal logic operator may be associated with a first, active state in the finite state machine representation. A value of the temporal logic operator may be determined by a number of occurrences of an event during an existing activation of the first state associated with the temporal logic operator. A state transition from the first state to a second state may be executed based on the value of the temporal logic operator. The second state may be set as the active state.

Abstract: System and method for validating a circuit for simulation are disclosed. The system includes at least one processing unit for executing computer programs, a graphical user interface for viewing representations of the circuit on a display, a memory for storing information of the circuit, and logic for representing the circuit in a hierarchical data structure, where the hierarchical data structure has a plurality of subcircuits arranged in a connected graph, and where each subcircuit has circuit elements and one or more input and output ports. The system further includes logic for traversing the hierarchical data structure in a bottom-up fashion, logic for recording input port to output port (port-to-port) properties of the subcircuits in the hierarchical data structure, logic for traversing the hierarchical data structure in a top-down fashion, and logic for identifying illegal port paths using the port-to-port properties of the subcircuits.

Abstract: Methods and apparatuses to estimate delay for logic circuit optimization using back annotated placement and delay data. In one aspect of the invention, a method to design a logic circuit, the method includes: modifying a first path that is back annotated with first placement information and first delay information to generate a second path; and calculating a signal delay on the second path from second placement information for the second path, the first placement information and the first delay information (or, computing an adjustment to the first delay information from second placement information for the second path and the first placement information). In one example according to this aspect, the first placement information and the first delay information are back annotated from a timing analysis based on placing and routing at least the first path. An actual route is determined from the first placement information in calculating the signal delay.

Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.

Abstract: A method for designing a semiconductor device including a semiconductor substrate and an interconnect on the semiconductor substrate, with X-direction being one direction parallel to the semiconductor substrate, Y-direction being a direction parallel to the semiconductor substrate and perpendicular to the X-direction, and Z-direction being perpendicular to the semiconductor substrate, the method includes: determining a cross-sectional configuration in the X-Z direction; three-dimensionalizing the cross-sectional configuration with a range in the Y-direction being specified; and using the three-dimensionalized configuration as a model.

Abstract: A design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a circuit that compensates for variances in the resistance of the buried resistor during operation of the integrated circuit using a waveform that is representative of the thermal characteristics of the buried resistor.

Abstract: A simulation system includes glitch injection circuitry in one or more hardware design units to allow the injection of glitches or noise to evaluate the system's response to errors on signals between the hardware design units. The simulation system includes a stimulation module with a set of drivers to input simulation patterns into the design units. Some inputs to software models are driven by the outputs of software models of another design unit. The stimulation module can monitor these signals driven by the software model but it is difficult for the stimulation module to directly drive these signals. The added glitch circuitry allows injection of errors into the simulated hardware by the stimulation module on signals that are not directly driven by the stimulation module but are driven by the outputs of hardware design units.

Abstract: A method, computer program product, and apparatus for simulating circuits. The method comprises modeling a circuit with an appropriate system of equations, partitioning a time interval on which the system of equations is defined, producing an interpolating polynomial on the time interval, and applying a two tiered iterative approach to solve the system of equations. The approach begins by decomposing a candidate solution vector into its time domain and frequency domain components. The Fourier transform is applied to the frequency domain components and time domain methods are applied to both the time domain components and the Fourier transformed frequency domain components to generate the solution to the original system of equations. Newton's method can be used in combination with a Krylov iterative subspace solver to perform the two-tiered iteration. The computer program product and the apparatus implement the method of simulating circuits.

Abstract: Roughly described, signal propagation delay values are estimated for a plurality of interconnects in a circuit design. For each interconnect, the propagation delay value(s) are estimated in dependence upon a preliminary approximate determination of whether the signal propagation delay is dominated more by an interconnect capacitance term or by an interconnect capacitance and resistance product term. If it is dominated more by the interconnect capacitance term, then the parameter values used for a minimum propagation delay calculation are obtained assuming a smallest capacitance process variation case and the parameter values used for a maximum propagation delay calculation are obtained assuming a largest capacitance process variation case. If the signal propagation delay is dominated more by the interconnect capacitance and resistance product term, then the opposite assumptions are made. Preferably the approximate determination is made by comparing Rint to k*Rd.

Abstract: Testing a model of a logic circuit model. The testing includes generating valid random input stimulus sequences for a logic circuit model. Enumerating critical resource requirements, enumerating critical resource availabilities does this, and selecting of stimulus sequences and determining legal times for execution of said stimulus sequences based on resource availability. This includes generating a plurality of possible combinations of input stimulus sequences and generating an array representation of critical resource requirements. These are used to generate an array representation of critical resources availabilities.

Abstract: An Effective Current Density (ECD) method for continuum representation of conducting networks is disclosed. ECD is a method for representing large numbers of conductors in a single, compact model for use in circuit simulation and in other such applications. The models created through the application of ECD are continuum models, valid in both long and short wavelength limits, with the important property that the computation time does not grow with the number of wires in the network. Therefore, in circuits where the method can be applied, there is no limit to the number of conducting wires or components in the network to be simulated. Circuits with an unlimited number of conductors can be simulated using modest computing hardware and at an approximately constant order of simulation complexity.

Abstract: A passive macromodel for lossy, dispersive multiconductor transmission lines uses a multiplicative approximation of the matrix exponential known as the Lie product. The circuit implementation of the macromodel is a cascade of elementary cells, each cell being the combination of a pure delay element and a lumped circuit representing the transmission line losses. Compared with passive rational macromodeling, the Lie product macromodel is capable of efficiently simulating long, low-loss multiconductor transmission lines while preserving passivity. This result is combined with transmission line theory to derive a time-domain error criterion for the Lie product macromodel. This criterion is used to determine the minimum number of cells needed in the macromodel to assure that the magnitude of the time-domain error is less than a given engineering tolerance.

Abstract: One embodiment of the present application includes the preparation of an assertion for inclusion in an integrated circuit simulation performed with a processing device (21). In response to an input to this processing device (21), a set of integrated circuit waveforms are defined to test the assertion. The processing device (21) tests the assertion with these waveforms; and after successful testing, the integrated circuit simulation is performed with the assertion.

Abstract: The aid design system for analog ICs includes an analog IC database, a peripheral component database, an input module, a computing simulation module, a selection module and an output module. The analog IC database includes parameters of a plurality of analog ICs. The peripheral component database includes parameters of the peripheral components cooperating with the analog ICs. The input module is for use in inputting a desirable parameter specification or specific IC according to the user's discretion. The computing simulation module includes transfer functions of the analog ICs. The selection module is for use in picking out suggested peripheral components based on the computing result of the computing simulation module. The output module is for use in displaying the suggested peripheral components or analog ICs.

Abstract: Disclosed herein are methods and apparatus that automatically generate an electric circuit model from process parameters used to specify a semiconductor fabrication procedure, wherein at least one of the process parameters is specified as a statistical distribution. The methods and apparatus convert the process parameters into an electric circuit model. The electric circuit model is specified in terms of electric parameters, wherein at least one of the electric parameters is specified in terms of a statistical distribution. The methods and apparatus thus allow a process engineer whose expertise may not extend to state-of-the-art circuit modeling to develop insight into the effect of process parameter selection on the performance of the resulting electric circuit. The resulting insight is further enhanced since at least one of the electric parameters is specified in terms of a statistical distribution.

Abstract: A method for simulation of mixed-language circuit designs is disclosed. In one embodiment, an object-oriented language module is natively instantiated within a hardware description language based design. In another embodiment, a hardware description language module is natively instantiated within an object-oriented language based design. A system for simulation of mixed-language circuit designs is also disclosed. In one embodiment, a simulator is configured to natively manipulate an object-oriented language module within a hardware description language based design. In another embodiment, a simulator is configured to natively manipulate a hardware description language module within an object-oriented language based design.

Abstract: A system for interfacing hardware emulation to software simulation environments may include a simulation node configured to simulate a first portion of a system under test and a hardware emulation node configured to emulate a second portion of the system under test. The hardware emulation node may also be configured to exchange simulation information (such as representations of signal values obtained as output from the emulated portion of the system under test) with the simulation node. The hardware emulation node may contain a field programmable gate array devices (FPGA) configured to perform the hardware emulation. The FPGA may be mounted on an expansion board, such as a PCI (Peripheral Component Interconnect) board.

Abstract: A method for providing verification for a first simulation image involves removing nodes from the first simulation image to produce an optimized image and an optimized nodes image, simulating the optimized image, invoking the optimized nodes image if debugging is selected, reconstructing a second simulation image using the optimized image and the optimized nodes image, simulating the second simulation image to gather simulation data, and debugging the first simulation image using simulation data.

Abstract: A method and system are disclosed, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains are identified within the design of the chip that are independent of each other. The independent clock domains are grouped together, within said chip design, to form clock domain groups. A timing analysis is performed on the design of the chip by clocking the clock domain groups each with an independent scan test clock. The scan test clocks originate externally to the design and by-pass, within the chip design, the corresponding internal clocks. Capture mode violations are recorded from the timing analysis and are used to go back and form new clock domain groups, thereby repeating the method until no capture mode violations are generated.

Abstract: A circuit design is simulated in a simulation environment. When a simulation model in the simulation environment transfers state information to a second simulation model, the simulation environment receives the state information and makes it available to the second simulation model without simulating the transfer through the simulated circuit design.

Abstract: A method of creating a power pin model of an LSI having appropriate analysis accuracy in consideration of information on positions within the LSI is provided. A divided cell size decision unit automatically decides a divided cell size of the LSI from power supply circuit network wire information, transistor structure information, analysis frequency information, size information, and element arrangement information of the LSI as well as from a semiconductor integrated circuit entire power pin model. A model creation unit allocates a model of an active section and a model of an internal capacitance section, including the positional information, within the LSI to the cells at an appropriate proportion, and a model coupling unit couples the models in each cell to create a power pin model of the LSI.

Abstract: A method for data analysis of power modeling for a microprocessor has been developed. The method takes multiple values of power data from a power modeling simulator and generates summary data to characterize the power data behavior. Summary data views include results characterizing behavior in a single cycle and behavior across multiple cycles. Data is viewed both at an absolute level to characterize total power and relative to previous levels to characterize power derivatives. Summary data is derived from power generated every cycle when running specific benchmark programs on the power simulator.

Abstract: A method for generating a linear piecewise representation of a driver output current signal includes segmenting the driver output current signal such that an integral of each segment matches an actual voltage change in corresponding portion of an associated output voltage signal (within a desired tolerance). The beginning and ending current/time values for each segment can then be compiled into the piecewise linear representation of the driver output current signal. A method for generating a model driver output current signal includes conformally mapping first and second sets of precharacterization output current data based on a weighted average of the indexing parameter (e.g., input slew or output capacitance) values for the model driver output signal and the first and second sets of precharacterization data.

Abstract: A verifying method and apparatus verifies operation of a semiconductor circuit device by inputting, to a logical simulator, logical models representing a logic circuit and an analog circuit, adding, to the logical model representing the analog circuit, a function that generates a function value in accordance with the state of connections between terminals of the analog circuit and terminals of the logic circuit, outputting the result of comparing the function value generated by the function and an expected value, and, based on a result of the comparison, determining whether or not there is a connection error between the terminals of the analog circuit and the terminals of the logic circuit.

Abstract: Semiconductor device junction simulation is carried out utilizing models that are developed with series resistance extractions that improve their fidelity particularly in the high current regions of device operation. The models may also be tailored to account for geometric considerations of the semiconductor devices thereby allowing for a more flexible model and simulation by providing for geometric scaling capabilities.

Abstract: A simulator development system is disclosed, including a data file management part to create a data file storing data concerning a plurality of types of integrated circuits, for each update and to manage the data file with a file name including a date and time when the data file is updated; and a simulator generation part to specify a latest data file from a plurality of the data files retrieved based on a type name, by referring to the date and time included in the file name in response to a selection of the type name of the integrated circuit, and to generate the simulator corresponding to the type of the integrated circuit, which type is specified by a type name.

Abstract: Methods for improving the accuracy and performance of large complex circuit simulations including; special processing of clock structures, minimizing repetitive simulation of identical structures, partitioning designs into sub-systems for use by one of a variety of matrix inversion techniques, row partitioning matrices for parallel solving, applying two stage Newton-Ralphon's method and iteratively selecting one of a number of serial and parallel matrix solvers to perform circuit simulation.

Abstract: Disclosed is an architecture for automating testing tasks, which would otherwise have to be done manually using actual hardware, by providing the capability to dynamically create many types of networked computing devices with different network configurations, eliminating the need to have actual test machines physically networked. Virtual endpoints are virtual computing devices networked to virtual adapters on a real computer. The virtual endpoints architecture comprises a miniport driver, a filter engine, virtual networked computing devices, a virtual stack, and a user mode to kernel mode interface. The virtual endpoints architecture technology can be used to test bridge and Internet connection sharing features as well as for testing any NDIS driver or client/server application. The virtual endpoints architecture lowers the cost of testing and allows for the ability to run the aforementioned types of tests in a batch nodal stress suite and without the need for large test network topologies.

Abstract: Disclosed is a complete SAT solver, Chaff, which is one to two orders of magnitude faster than existing SAT solvers. Using the Davis-Putnam (DP) backtrack search strategy, Chaff employs efficient Boolean Constraint Propagation (BCP), termed two literal watching, and a low overhead decision making strategy, termed Variable State Independent Decaying Sum (VSIDS). During BCP, Chaff watches two literals not assigned to zero. The literals can be specifically ordered or randomly selected. VSIDS ranks variables, the highest-ranking literal having the highest counter value, where counter value is incremented by one for each occurrence of a literal in a clause. Periodically, the counters are divided by a constant to favor literals included in recently created conflict clauses. VSIDS can also be used to select watched literals, the literal least likely to be set (i.e., lowest VSIDS rank, or lowest VSIDS rank combined with last decision level) being selected to watch.

Abstract: A load electric current evaluating device includes a load electric current calculating section for calculating a load electric current flowing through a predetermined part of electric wiring including a load part, a protecting part for the load part, an electric wire and an electric power source at the normal time; a storing section for storing load part information showing electric characteristics of the load part and protecting part information showing electric characteristics and a rated value of the protecting part; an information reading section for reading the load part information and the protecting part information from the storing section; an evaluation reference providing section for making an evaluation reference for evaluating adaptability of the load electric current flowing through the predetermined part at the normal time with reference to the load part information and the protecting part information; an evaluating section for evaluating the adaptability of the calculated load electric current

Abstract: One embodiment of the invention provides a system for speeding up an iterative process that simulates and, if necessary, corrects a layout of a target cell within an integrated circuit so that a simulated layout of the target cell matches a desired layout for the target cell. The system operates by determining if the target cell is similar to a preceding cell for which there exists a previously calculated solution. If so, the system uses the previously calculated solution as an initial input to the iterative process that produces the solution for the target cell.

Abstract: A method of defining three-dimensional structure from mask layout for computer simulation, which provides a technology for defining a three-dimensional structure of liquid crystal cell which comprises a apparatus of liquid crystal display for designing and analyzing a apparatus of liquid crystal display. A method of generating three-dimensional structure which comprised of material layers between upper substrate and lower substrate, which provides a generation method of three-dimensional structure for computer simulation by depositing material layers under the upper substrate and over the lower substrate, and sandwiching a center insertion layer between the deposited upper and lower material layers for a case which includes tapered structure of material layer for the substrate.

Abstract: A method for simulating analog behavior of a circuit in a simulation system includes representing the circuit as a hierarchically arranged set of branches, which includes a root branch and a plurality of other branches logically organized in a graph. The hierarchically arranged set of branches includes a first branch that has one or more subcircuits and a second branch that also has one or more subcircuits. The first branch and second branch are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches.

Abstract: A system and method for deriving semiconductor manufacturing process corners using surrogate simulations is disclosed. The method may be used to determine individual performance metric yields, the number of out-of-specification conditions for a given number of simulation samples, and a total yield prediction for simultaneous multi-variable conditions. A surrogate simulation model, such as a Response Surface Model, may be generated from circuit simulation data or parametric data measurements and may be executed using a large number of multi-variable sample points to determine process corners defining yield limits for a device. The model may also be used to simulate process shifts and exaggerated input ranges for critical device parameters. In some embodiments, the derived process corners may better represent physically possible worst-case process corners than traditional general-purpose process corners, and may address differences in process sensitivities for individual circuits of the device.

Abstract: The response of linear and non-linear systems to an arbitrary pulse train is modeled for efficient and accurate circuit simulation. First, a harmonic balance analysis is performed for a system incorporating linear and non-linear components. Then, the even and odd frequency components of the harmonic balance result are separated and interpolated. Finally, the resulting interpolated components are combined to generate the frequency domain positive step response and the frequency domain negative step response of the system. These resulting frequency domain step responses are utilized to generate a low order pole/zero model of the step responses. The pole/zero model can then be used to efficiently and accurately model the response of the system to an arbitrary sequence of positive and negative going pulses.

Abstract: In a mutual immittance calculation apparatus, an input section inputs data of a model of an electric circuit apparatus, being a target for analysis of the electromagnetic-field strength and being divided into a plurality of patches. A mutual immittance calculation section calculates respective mutual immittance for combinations of patches corresponding to the main portion and to the additional portion. The mutual immittance calculation section uses a stored calculation result corresponding to the main portion when the model in which only the additional portion has been changed is calculated for a second time onward, and recalculates the mutual immittance corresponding to the changed additional portion.

Abstract: There is disclosed an apparatus for designing and optimizing a memory for use in an embedded processing system. The apparatus comprises: 1) a simulation controller for simulating execution of a test program to be executed by the embedded processing system; 2) a memory access monitor for monitoring memory accesses to a simulated memory space during the simulated execution of the test program, wherein the memory access monitor generates memory usage statistical data associated with the monitored memory accesses; and 3) a memory optimization controller for comparing the memory usage statistical data and one or more predetermined design criteria associated with the embedded processing system and, in response to the comparison, determining at least one memory configuration capable of satisfying the one or more predetermined design criteria.

Abstract: Sequential digital integrated circuits have stable state nodes that are capable of retaining their state (logic value) even in the absence of any input directly driving these points. However, in addition to stable state nodes, some custom-designed digital circuits have so-called transient state nodes. A transient state node is defined as node that can directly affect the value of a stable state node and is combinatorially driven by inputs of the circuit, but the transition delay from at least one input to the node is greater than a predefined threshold value. Identifying such transient state nodes, along with the stable state nodes, is critical for the efficient simulation of custom digital circuits by a hierarchical device level digital simulator. A method is provided herein for identifying transient state nodes in a digital circuit, given the circuit's netlist and the identity of the stable state nodes in the circuit.

Abstract: Methods and systems are presented for generation of a test suite in order to validate compliance of a process with its process specification. The methodology involves a formal description of the process using a flowchart, refinement of the flowchart to include misinterpretations of the process specification, defining compliance coverage models over the flowchart, and automatically generating test case scenarios that cover the models. Internal and external types of misinterpretation are distinguished. A compliance test suite is automatically generated and observations made of the details of the traversal through the flow chart when the tests are executed.

Abstract: For generating a simulation case to verify an operation of an IC device, a database including a plurality of device description files, a plurality of pattern files and a plurality of command files is established. Files stored in the database and corresponding to an IC device are collected. The collected files are parsed to find out entries to be edited. Specified entries are edited by a user according to the operation of the IC device. A simulation case or a plurality of simulation cases are generated according to the entries.

Abstract: A system and method for determining a guard band for an operating voltage of an integrated circuit device are provided. The system and method provide a mechanism for calculating the guard band based on a comparison of simulated noise obtained from a simulation of the integrated circuit device using a worst case waveform stimuli with simulated or measured power supply noise of a workload/test pattern that may be achieved using testing equipment. A scaling factor for the guard band is determined by comparing results of a simulation of a workload/test pattern with measured results of the workload/test pattern as applied to a hardware implementation of the integrated circuit device. This scaling factor is applied to a difference between the noise generated through simulation of the workload/test pattern and the noise generated through simulation of the worst case current waveform to generate a guard band value.

Abstract: A method is for controlling an impedance of a via of a printed circuit board. The Via is connected with a trace and includes a drill hole, a pad and an anti-pad. The method includes steps of: building a math model; testing whether an impedance of the via matching with an impedance of the trace; analyzing the impedance of the via if passing the testing; and adjusting parameters of the pad, the anti-pad, and the drill hole if fails testing, and returning to the simulating step, till impedance matching achieved. The method which can efficiently keep signals integrality and increase signal transmission speed.

Abstract: A method for forming a hybrid active electronic and optical circuit using a lithography mask. The hybrid active electronic and optical circuit comprising an active electronic device and at least one optical device on a Silicon-On-Insulator (SOI) wafer. The SOI wafer including an insulator layer and an upper silicon layer. The upper silicon layer including at least one component of the active electronic device and at least one component of the optical device. The method comprising projecting the lithography mask onto the SOI waver in order to simultaneously pattern the component of the active electronic device and the component of the optical device on the SOI wafer.

Abstract: A system for communicating simulation solutions between circuit components in a hierarchical data structure includes a simulator module having one or more computer programs for representing the circuit as a hierarchically arranged set of branches, which includes a root branch and a plurality of other branches logically organized in a graph. The hierarchically arranged set of branches includes a first branch that contains one or more driver leaf circuits and a second branch that also contains one or more receiver leaf circuits, where the first branch and second branch are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches.