Abstract: A substrate device is designed by identifying one or more criteria for handling of a transient electrical event on the substrate device. The one or more criteria may be based at least in part on an input provided from a designer. From the one or more criteria, one or more characteristics may be determined for integrating VSD material as a layer within or on at least a portion of the substrate device.

Abstract: Various techniques related to clocking signals used for automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving first and second asynchronous clock signals having a first phase relationship at a first time and sampling the second clock signal at transitions of the first clock. The method further includes storing the samples; and analyzing the samples to ascertain the first phase relationship of the second clock signal with respect to the first clock signal and provide a representation of the first phase relationship. Other embodiments are described.

Abstract: A mesh model creating method includes a mesh forming step to divide a region that is a target of a simulation into a plurality of polygonal meshes so that each node within the region is positioned within one mesh and a boundary line between two mutually adjacent meshes is formed by a perpendicular bisector with respect to a straight line that connects the nodes within the two mutually adjacent meshes, a computing step to compute an inductance value and a resistance value of an interval between the two mutually adjacent meshes based on the data of the meshes using predetermined computation formulas, and a mesh model creating step to create a mesh model based on the data of the meshes and the computed inductance value and resistance value.

Abstract: Herein disclosed is a system for testing a power management system (2) of a marine vessel (1), in which said power management system (2) is arranged for controlling systems (6) that produce electrical energy, in which said power management system (2) is arranged for receiving first signals (9) from a power consuming system (7).

Abstract: The present invention relates to a simulation-based verification apparatus and a verification method, which enhance the simulation performance and efficiency greatly, for verifying a digital system containing at least million gates. Also, the present invention relates to a simulation-based verification apparatus and a verification method used together with formal verification, simulation acceleration, hardware emulation, and prototyping to achieve the high verification performance and efficiency for verifying a digital system containing at least million gates.

Abstract: Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.

Abstract: A method of verifying a layout of an integrated circuit device is disclosed. The method comprises steps of receiving a physical layout for a schematic of a circuit implemented in the integrated circuit device; generating an implant table file having data showing a relationship between layers and device types of the integrated circuit device; and generating a layout-versus-schematic rules file using the implant table file.

Abstract: The invention provides a method for testing a circuit operation (circuit simulation), which is conducted by using a model of high precision. After parameters are extracted by using a model of which physical precision is low and parameter extraction time is short from measurement data, the parameters are converted to those obtained by a model of which parameter extraction time is generally long and a circuit operation test is performed by a model of high physical precision. In other words, a parameter is extracted first by a model of low physical precision and then, the extracted parameter is converted into a parameter obtained by the model of high physical precision. Finally, a circuit operation test is performed by using the model having high physical precision.

Abstract: A method of simulating a circuit parameter such as voltage or current for a dominantly linear circuit by constructing a circuit equation matrix whose elements correspond to nodes of the circuit, decoupling linear and nonlinear contributions to the circuit parameter based on a partition of an inverse matrix of the circuit equation matrix, computing linear and nonlinear components using the decoupled contributions, and combining the nonlinear and linear components to yield a state of the circuit parameter for a given time step. The computation of the nonlinear component includes Newton-Raphson iterations to linearize nonlinear devices of the circuit, wherein the Newton-Raphson technique is applied to the right-hand side of the circuit state matrix equation. The computations are iteratively repeated for successive time steps which are advantageously separated by a constant time interval to avoid further recalculation of the state matrix.

Abstract: A scripting approach to managing the test bench complexity issue is provided. Partitioning the functionality of a test bench between Verilog and a scripting language allows for a significant reduction in compile times during ASIC verification. If done correctly, partitioning also offers great potential for re-use of test bench components. The Tcl language was chosen as a basis for implementing a library of PLI routines that allow fully customizable interpreters to be instantiated in Verilog test benches. This library allows multiple Tcl interpreters to be instantiated in a Verilog simulation. The Tcl interpreters can interact with the simulation and cause tasks to be executed in the Verilog simulation. It has been found the TCL_PLI library is extremely valuable in speeding up verification efforts on multi-million gate ASICs.

Abstract: A system and method to analyze analog, mixed-signal, and custom digital circuits. The system and method displays to a user characteristic values of a circuit and statistical uncertainty values of the characteristic values early in a sampling or characterization run of the circuit. The characteristic values and their statistical uncertainties are updated as the sampling or characterization run progresses. The user can halt the sampling or characterization run once a desired level of uncertainty is attained. The system can automatically halt the sampling or characterization run, once the statistical uncertainty lie within a pre-determined range.

Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of

Abstract: A method is provided for power delivery analysis and design for a hierarchical system. The method includes building a model corresponding to each element of the hierarchical system, compiling a repository that contains the models corresponding to each element of the hierarchical system, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method further includes performing optimized gridding for each element of the hierarchial system, the net list, the domain list, the component list, the pin list, and the layer list and assembling a system model from the models contained in the repository. Also, the method includes flattening the system model by converting the system model to a flattened system model that consists entirely of resistors, and running a simulation on the flattened system model.

Abstract: A IC wafer is fabricated using a process of interest to have a plurality of FET devices with different channel lengths (Leff) form a plurality of channel length groups. The threshold voltage (VT) is measured of a statistical sample of the FET devices in each channel length group at two different drain-to-source voltage (VDS). The mean of VT is calculated for each channel length and each VDS. A slope coefficient ? relating VT to Leff is calculated at each VDS. The total variance of VT is calculated at each VDS. Two equations at each VDS, each relating the total variance of VT to the variance of VT with respect to dopant levels and the square of the slope coefficient ? times the variance of Leff, are solved simultaneously to obtain the variance of VT with respect to dopant levels and the variance of Leff.

Abstract: A system for testing components of a simulator has a slave device. A master controller is coupled to the slave device. The master controller transmits chip select and data signals to the slave device for testing a component of the simulator. A computer system is coupled to the master controller. The computer system displays at least one image of a control panel. A cursor of the computer system is placed on a desired component on the at least one image of the control panel. A test signal from the computer system is sent to the master controller for testing the component of the simulator.

Abstract: A system and method for simulating network connection characteristics by alteration of a network packet. In general, the method of the invention includes providing a driver that is capable of accessing all outgoing and incoming network packets and altering a network packet to simulate a connection characteristic of the network. In particular, the method of the invention includes receiving a network packet, assigning a new, simulated network address to the network packet and performing modification of the network packet to simulate certain network connection characteristics (including, for example, transmission delay, limited bandwidth, packet dropping, packet fragmentation, packet duplication and packet reordering). The system of the invention includes a modification module for altering certain characteristics of a packet.

Abstract: In order to decode a simulation instruction in accordance with the present invention, a new decoding program is generated, which includes flat-type decoding codes for at least one of the instructions having a high occurrence frequency. The remaining instructions are decoded using tree-type decoding codes. By combining both flat-type and tree-type decoding operations in a single decoding program, simulation speed is increased while reducing memory requirements.

Abstract: A system and a method are disclosed for circuit analysis. A circuit modeling system calculates sensitivities of gates for statistical static timing analysis of a circuit. Timing distribution sensitivities of gates and correlations between the sensitivities are determined. A Monte Carlo simulation is run using the sensitivities to determine timing distribution of paths and determine probabilities of paths being the critical path. Aggregate sensitivities for cells are also determined.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.

Abstract: A computer is programmed to automatically select a state or a set of states of a digital circuit that are visited during simulation, for use as one or more initial states by a formal verification tool. Such automatic selection of one or more simulation states reduces the set of all simulation states to a small subset, thereby to address the state space explosion problem. Depending on the embodiment, the programmed computer uses one or more criteria provided by a library and/or by the user, in making its selection of states. Such criteria may be based on a property (assertion/checker) of the digital circuit and/or a signal generated during simulation. Furthermore, after such criteria (also called “primary criteria”) are applied, the selected states may be pruned by application of additional criteria (also called “secondary criteria”) prior to formal analysis.

Abstract: A method, system and computer program product for generating a coverage model to describe a testing scheme for a simulated system are described. In a preferred embodiment, a simulated system is tested with a testing simulation program. A simple event database is generated with the testing simulation program. Results of a checker analysis from the testing with the testing simulation program are obtained, and coverage data is created from a coverage model configuration file, the simple event database and the results of the checker analysis.

Abstract: According to one method of simulation processing, a count event counter for a count event is created within instrumentation of a hardware description language (HDL) simulation model of a design and a threshold greater than 1 is established for the count event counter. The design is then simulated utilizing the HDL simulation model, and occurrences of the count event are accumulated in the count event counter to obtain a count event value. Thereafter, an indication of whether the count event value of the count event exceeds the threshold is recorded within a data storage subsystem.

Abstract: An integrated circuit design kit including one or more circuit components topologies, and one or more critical interconnect lines topologies. The interconnect line topologies may be predefined. The kit may further include one or more circuit components models and one or more critical interconnect lines models.

Abstract: Method and apparatus for security systems are provided to protect electronic designs from unauthorized usage. An obfuscation system is provided for creating secure simulation models of IP cores that allow efficient evaluation of an electronic design incorporating an IP core but do not allow practical implementation of the IP core. The obfuscation system identifies regions for obfuscation within an IP core. Logic obfuscation is inserted into these regions. Examples of obfuscation include additional circuitry that produces time dilatation, space dilatation, or a combination of the two in the circuitry of an IP core. Typically, the inserted obfuscation does not change the ultimate behavior of the internal signals, but is complicated enough to make an electronic design so slow and/or so large that it cannot be implemented practically. Further, the inserted obfuscation should be of a type is not normally removed by that normal logic optimizations such as synthesis.

Abstract: The invention is aimed to analyze the characteristics of a transmission line only by inputting the specific distributed parameters without mesh dividing the transmission line to be analyzed into minimal unit required for the analysis. An arithmetic operation section 12 solves a differential equation regarding electromagnetic interaction of each line segment based on the predetermined distributed parameters, including a distributed self-inductance Li, a distributed resistance Ri, and a distributed capacitance ci and a distributed conductance gi in relation to a reference potential plane in the transmission line, and a distributed mutual inductance Mij, a distributed capacitance Cij, and a distributed conductance Gij between the transmission line and another transmission line, which are input from an input section 11, and calculates the characteristic data of the transmission line.

Abstract: A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology.

Abstract: An application specific configurable logic IP module includes (1) a system level configuration controller; (2) at least one standardized interconnect communicatively coupled to the system level configuration controller; (3) at least one standardized configuration port for programming the application specific configurable logic IP module; (4) an embedded programmable logic fabric, communicatively coupled to the system level configuration controller and the at least one standardized interconnect, for mapping arithmetic functions into standard cells; (5) at least one scalable configurable logic module; and (6) a programmable routing matrix. The system level configuration controller is suitable for selecting a standard for the at least one standardized interconnect, the at least one standardized configuration port, and a number of embedded programmable logic functions, and for controlling the programmable routing matrix.

Abstract: In a transistor model generating apparatus, a transistor region extracting section extracts a non-rectangular transistor region, in which a gate region is formed above a non-rectangular diffusion layer region, from a mask layout data of a semiconductor integrated circuit. A dividing section sets a division line extending in a direction of a gate length of a transistor to divide the non-rectangular transistor region into a plurality of rectangular transistor regions. A relating section relates the non-rectangular transistor region and the plurality of rectangular transistor regions with the mask layout data. A size calculating section calculates a size data of each of the plurality of rectangular transistor regions. A correction value calculating section calculates a correction value of a diffusion layer length dependency parameter to the plurality of rectangular transistor regions based on the size data.

Abstract: One embodiment of the invention provides a system that dissects edges of a layout of an integrated circuit to produce a segmentation of the layout for a subsequent optical proximity correction (OPC) operation. In order to perform the dissection, the system first performs a model-based simulation on the layout to generate intensity gradients along edges of features in the layout. Next, the system generates a segmentation for edges in the layout based upon the intensity gradients. This segmentation is used during a subsequent optical proximity correction (OPC) process to generate corrections for the layout so that the layout prints more accurately on a semiconductor chip.

Abstract: Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.

Abstract: A method of emulation or functional testing of a first microprocessor in its functional environment including one or several peripherals and at least one internal bus of communication between this first microprocessor and its peripherals, from a second microprocessor, consisting of deactivating the first microprocessor, using the communication bus(es) to communicate between the two microprocessors and the peripheral(s), and activating the second microprocessor, wherein the first microprocessor communicates with the second microprocessor over a series link and wherein the second microprocessor is realized by a simulation model.

Abstract: A system for providing a runnable computer simulation model comprises a design automation software product for enabling a designer to create a simulation model including interconnected component and/or subsystem models. The system also comprises a simulation content file creation means for creating a simulation content file that includes information describing the simulation model; and a simulation player software product including means for reading the simulation content file. The simulation player software product enables an end user to run the simulation model based upon the information in the simulation content file, but does not allow the end user to add or remove component models, subsystem models or interconnections of the simulation model.

Abstract: One embodiment of the present invention provides a system that speeds up timing analysis by reusing delays computed for isomorphic subcircuit. During operation, the system receives a circuit block to be analyzed, wherein the circuit block is in the form of a netlist. The system then subdivides the circuit block into a set of subcircuits. The subcircuits are then partitioned into equivalence classes, which contain subcircuits which are topologically isomorphic to each other. Next, the system performs a timing analysis by tracing paths through a timing graph for the circuit block. During this timing analysis, whenever a delay is required for a subcircuit, the system determines if a corresponding delay has been already computed for the equivalence class associated with the subcircuit. If so, the system reuses the delay. If not, the system computes the delay for the subcircuit, and then associates the computed delay with the equivalence class so that the computed delay can be reused for isomorphic subcircuits.

Abstract: Method for simulating a response of an electronic circuit containing SOI transistors (220) and being in a steady state, characterised by the following steps: —creating of a list of transistors (220); memorising of the signals at the nodes (200, 201, 202) of each transistor (220) in the list, when inputs (201) of said circuit are excited during an established time; for each transistor (220), independently from the others, analysing a variation of a common electric property when we apply to, at their nodes (200, 201, 202), said corresponding memorised signals, in relation with a pre-set criterion of this variation; if the criterion is not respected modify once an initial electric environment of each transistor and return to the preceding step; excite the circuit, containing said transistors (220) with the new electric environment, during said time and check at each said transistor that said criterion is met.

Abstract: An apparatus and method for simulation and testing of electronic systems using a single model that has the composite behavioral information of multiple parts. The single model allows the designer to simulate using one model that captures the anticipated extremes (best case behavior to worst case behavior) across a collection of devices from different vendors.

Abstract: Exemplary techniques for verifying a hardware design are described. In a described embodiment, a method comprises compiling an error verification object corresponding to an error verification command to verify a portion of a hardware design of a device under test. The error verification object is compiled in accordance with data provided by an error scripting module. The error scripting module has access to hardware-specific data corresponding to the hardware design of the device under test. The compiled object is sent to the device under test and a response to the compiled object is received from the device under test. The received response from the device under test is parsed in accordance with data provided by the error scripting module.

Abstract: A method includes steps of calculating, for each predetermined operation included in a program, an execution time required when the operation is executed by a predetermined processor, or calculating, for each predetermined operation included in the program, a circuit size required when the operation is realized in a form of hardware according to a predetermined technology; and calculating, for the entirety of the predetermined program or operations corresponding to a part the entirety of the predetermined program, a total execution time required when the entirety of the predetermined program is executed by the predetermined processor, as a result of applying in sequence the required execution time, or calculating, for the entirety of the predetermined program or operations corresponding to a part the entirety of the predetermined program, a total circuit size required when the entirety of the predetermined program or programs corresponding to a part of the entirety of the predetermined program, as a result of

Abstract: Method and system for testing an Application Specific Integrated Circuit is provided. The system includes, a simulator that interfaces with a host computer emulation module; and a virtual interface driver (“VID”) that interfaces with the host computer emulation module and a bus interface module, wherein the VID maps plural stimulus to the simulator via the bus interface module. The method includes, loading a bus functional module in an ASIC simulator; determining configuration of devices supported by a host emulation system; and mapping configuration information to the host emulation system, wherein a virtual interface driver maps the configuration information to the host emulation system.

Abstract: A method for simulating an integrated circuit having a plurality of clock control modules includes simulating the integrated circuit, and automatically receiving from each clock control model during simulation an indication of a simulated power state of the clock control model. Accordingly, the simulated power state of the portion of the integrated circuit model to be clocked by a clock control model can be monitored based on the indicator from the clock control model, rather than on a higher level analysis of the simulated input/output behavior of the integrated circuit model.

Abstract: A method, apparatus and computer program product implement optimized channel routing in an electronic package design. Electronic package physical design data are received. A physical design including a netlist including a plurality of nets is generated. Finite impulse response (FIR) driver coefficients are determined for each net in the netlist from simulation with generation of impulse responses of the netlist.

Abstract: A system for analyzing a model of an electronic circuit, which includes at least one non-linear circuit element, includes a computer. The computer replaces the non-linear circuit element with a linearized circuit model that approximates a behavior of the non-linear circuit element. The computer also inserts into an element matrix a calculated value that corresponds to the linearized circuit model for a prescribed or desired time step. The computer further performs a numerical operation on the element matrix to effectively invert the element matrix.

Abstract: Techniques are disclosed for modeling a cell of an integrated circuit design. In one aspect of the invention, a full-space polynomial model is fit to cell information comprising measured data points associated with one or more independent variables such as voltage slew, capacitive load, supply voltage or temperature. Error values are generated indicative of error between the measured data points and the full-space polynomial model. The error values are used to partition the modeling space into domains. For at least a given one of the domains, a first polynomial model is generated based on a subset of the measured data points and at least one additional data point determined by interpolation from the measured data points in the subset. Error values are generated indicative of error between the measured data points of the subset and the first polynomial model.

Abstract: A method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips. More particularly, a method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips based on the parameters of test patterns measured at the “wafer sweet spots” so as to arrive at an accurate model.

Abstract: Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

Abstract: A method and system for verifying circuit designs through propagation of assertions within a circuit design. In an embodiment, a plurality of provided assertions a circuit design are propagated within the circuit design. The circuit design is then verified using at least one of the propagated assertions as an assumption.

Abstract: A method and system that utilizes a graphical interface that enables a user to select and capture building blocks of a Device Under Test (DUT) test scenario from a previously run test case or from multiple stimulation results. Each of these extracted building block events or “tags” are created from a slice of a graphical stimulation view, which slice is converted into a coded stimulus written in a high-level language code that represents the condition(s) that created the graphical simulation view. These coded stimuli (representing the tags) are stored in a library. To create a corner case scenario or sequence in the DUT, a user utilizes a graphical interface to select the different extracted tags from the library and combines them together.

Abstract: A CMOS model generating apparatus 1 according to the present invention generates a CMOS model by converting an In-Ip space into an xn-xp space such that a typical condition TT and corner conditions FF, SS in the In-Ip space become (0, 0), (?, ?) and (??, ??) in the xn-xp space, determining an ellipse fitting to the respective mappings of the corner conditions FF, SS, FS and SF with the mapping (0, 0) of the typical condition TT as a center, expressing two independent principal components in the form of a Gaussian distribution using the major and minor axes of this ellipse as axes of the principal components, and obtaining a probability distribution determining deviations of the Gaussian distribution such that the cumulative probability within this ellipse becomes equal to the one presumed by the corner conditions FF, SS, FS and SF.

Abstract: Methods for generating simulation vectors incorporating periodic jitter, or phase-shifted periodic jitter are disclosed. Periodic jitter, such as sinusoidal jitter, is preferably represented by a mathematical equation which defines the amount of jitter experienced at each cycle of a clock or data signal. The calculated periodic jitter for each cycle is used to form a new multi-cycle vector incorporating the jitter. If a particular signal to be simulated additionally needs to travel a particular distance such that it would experience a time delay, that time delay may also be incorporated into the jitter equation as a phase shift. So incorporating the time delay into the jitter equation allows for the easy simulation of circuits receiving the vectors without the need to actually design or “lay out” the circuits that imposing the time delay.

Abstract: A method and apparatus for debugging circuit designs having random access memory therein. The circuit design is emulated on a hardware logic emulator. The RAM emulated by the emulator can be rewound to a previous state, and then replayed. The RAM emulated by the emulator can also be reconstructed to a state the RAM maintained at some point during a trace window.

Abstract: A method and system for analyzing transaction level simulation data of an integrated circuit design. In an embodiment, a transaction fiber is plotted. The transaction fiber comprises a transaction block. A compact representation of a child block of the transaction block is provided when the transaction fiber is in a collapsed state. In one embodiment, the compact representation of the child block is provided by drawing a line segment below the transaction fiber.