Abstract: A computer-implemented method for verifying a design includes representing a verification directive, which pertains to the design and includes a local variable, by a finite state machine. The state machine includes multiple states, with transitions among the states, transition conditions associated with the transitions, and procedural blocks, which correspond to the transitions and define operations to be performed on the local variable when traversing the respective transitions. The finite state machine is executed by traversing the transitions in accordance with the respective transition conditions and modifying the local variable in accordance with the respective procedural blocks of the traversed transitions, so as to verify the design with respect to the verification directive.

Abstract: For application to analog, mixed-signal, and custom digital circuits, a system and method to begin with a complex problem description that encompasses many variables from statistical manufacturing, the circuit's environment, and the circuit's design parameters, but then apply techniques to prune the scope of the problem to make it manageable for manual design and more efficient automated design, and finally use that pruned problem for more efficient and effective design.

Abstract: A system and method is disclosed in an emulation environment that dynamically remaps user designs. In one embodiment, a request is received to load an integrated circuit design to be emulated in a desired partition within the emulator. The emulator automatically determines the availability of the partition requested. If the partition is not available, the design is dynamically remapped to a different partition that is available. In another embodiment, clocks associated with the integrated circuit design are also dynamically remapped. In yet another embodiment, the user can control the size of the partitions (e.g., the number of printed circuit boards in a partition).

Abstract: A method and an apparatus for indirectly simulating a semiconductor integrated circuit (IC) are described. A circle chain is formed using input pins and output pins to provide an intellectual property (IP) core model that substitutes for a real IP core circuit. A test bench for the IP core model is generated, the semiconductor IC that includes the IP core model is integrated using the generated test bench, and the semiconductor IC is simulated.

Abstract: The invention includes a method and a system for generating integrated circuit (IC) simulation information regarding the effect of design and fabrication process decisions. One embodiment includes creating and using a data store of profile-based information comprising metrology signal, structure profile data, process control parameters, and IC simulation attributes. Another embodiment includes creation and use of a simulation data store generated using test gratings that model the geometries of the IC interconnects. The interconnect simulation data store may be used in-line for monitoring electrical and thermal properties of an IC device during fabrication. Other embodiments include methods and systems for generating and using simulation data stores utilizing a metrology simulator and various combinations of a fabrication process simulator, a device simulator, and/or circuit simulator. Information from the simulation data store may be used in-line in-situ during the design or fabrication process steps.

Abstract: Apparatus and methods for calculating power consumption of circuitry within integrated circuits (ICs), such as programmable logic devices (PLDs) are disclosed and described. A method of estimating power consumption of a circuit in an IC includes decomposing the IC into a plurality of overlapping blocks. Each block in the plurality of blocks includes a portion of the circuitry in the IC. The method further includes estimating power consumption of each block in the plurality of blocks, and estimating power consumption of the IC based on the power consumption of the plurality of blocks.

Abstract: An integrated circuit design simulation method is provided that takes advantage of the fact that, when an instance of a circuit module has been simulated under a given set of input conditions, and the resulting output values and delays have been evaluated, another instance of the same module need not be re-simulated when it has the same input combination as the prior circuit module instance. The results computed earlier for the earlier circuit module instance can be re-used for the current circuit module instance.

Abstract: Provided is a computer system (1) including a storage (2) for storing a netlist (31), and a contents generator (12) for generating a program (32) containing a statement to execute a plurality of operations of an operation portion contained in the netlist (31). The operation portion includes an operation performing logic operations of multiple stages and having a plurality of inputs, and an operation of a previous stage for a plurality of input sources.

Abstract: A method for predicting and controlling leakage wherein an IDDQ prediction macro is placed in a plurality of design topographies and data is collected using the IDDQ prediction macro. The IDDQ prediction macro is configured to measure subthreshold leakage and gate leakage for at least one device type in a semiconductor test site and in scribe lines using the IDDQ prediction macro and establish a leakage model. The method correlates the semiconductor test site measurements and the scribe line measurements to establish scribe line control limits, predicts product leakage; and sets subthreshold leakage limits and gate leakage limits for each product using the leakage model.

Abstract: The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to predictive, pre-fabrication methodologies for determining inefficiencies in an integrated circuit (IC) design. The present invention, in one or more implementations, provides an effective pre-production methodology for predicting the efficiency and behavior of a designed ESD protective circuit and testing the ESD protective circuit with a simulated IC. The method of the present invention yields predictive results that have been comparatively tested.

Abstract: In one embodiment, a method includes simulating by one or more computer systems a larger circuit to assign one or more values to one or more latch variables associated with the larger circuit, generating by the one or more computer systems one or more reduced circuits from the larger circuit according to the values assigned to the latch variables, generating by the one or more computer systems a transition relation (TR) for each reduced circuit, and generating by the one or more computer systems an initial state set for one or more instances of validation on the reduced circuits according to the TRs.

Abstract: A simulator operable to simulate behaviors of a processor using software is provided. The simulator includes a command input unit, a memory element, a register element, a control element, a resource information storage unit, and a resource access-analyzing unit. The command input unit is operable to analyze/process entered commands. The memory element is operable to store executive instructions issued by the processor and data treated by the processor. The register element is operable to contain data for use in calculation. The control element is operable to access the memory element and register element in accordance with the executive instructions. The resource information storage unit is operable to contain specified resource information and a piece of read/write information for each piece of the resource information.

Abstract: In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in the layout. A contour simulation is performed to determine a generated contour object. The contour simulation simulates parametric variation factors that may occur in the photolithographic process. An adjusted width and adjusted length of the object is then determined based on the generated contour object. The adjusted width and the adjusted length are usable to determine a parametric model for simulation of the object. For example, a layout versus schematic (LVS) tool may back-annotate the layout. Then, a SPICE simulation may use the output of the LVS tool to verify the electrical behavior of the transistor using the adjusted width and adjusted length.

Abstract: A method for determining a maximum IR drop on a power grid of a circuit is disclosed. The method includes dividing a reference timing signal into multiple bins. Each one of the bins having a corresponding bin duration. The bins being divided by a corresponding fuzzy boundaries. Each one of the fuzzy boundaries having a corresponding boundary duration. Each one of the of bins is analyzed including selecting one of the bins, identifying a first set devices that transition to their corresponding maximum current states during the selected bin and identifying a second set of devices that transition to their corresponding maximum current states during at least one of the boundaries of the selected bin, but not within the selected bin. A maximum current demand equal to a sum of the maximum current states of the first and second plurality of devices is calculated. A system for testing a circuit is also disclosed.

Abstract: A method to simulate an electronic circuit includes determining process parameters and a process variation for each process parameter, and determining a value for each of a plurality of components of the circuit as a function of the process variations.

Abstract: A method for generating automatic design characterization patterns for integrated circuits (IC) is provided. The method includes selecting a routing scheme from a file containing the device description of the routings of the IC. The routing scheme may be of a phase locked loop, clock tree, delay element, or input output block in one embodiment. Resource types for the routing scheme are identified and a path is defined, within constraints, between the resources. Once a path is defined, alternate paths are defined by retracing the path within constraints from an end of the path to the beginning of the path. An alternative path is then built and the alternative path shares a portion of the path previously defined. A computing system providing the functionality of the method is also provided.

Abstract: A netlist description of a circuit is processed to classify some signals of the circuit as essential signals and to classify all other signals of the circuit as non-essential signals. Thereafter when simulating behavior of the entire circuit in response to input signals supplied over some time interval, a simulator saves first simulation data representing behavior of the circuit's essential signals during the time interval. Thereafter the simulator is programmed to re-simulate behavior of only a selected subcircuit of the circuit during only a selected subinterval of the full time interval based on behavior of essential signals described by the first simulation data. During the re-simulation, the simulator saves second simulation data representing behavior of both essential and non-essential signals of the subcircuit to provide a more complete picture of the behavior of the selected subcircuit during the selected subinterval.

Abstract: A chip design verifying and chip testing apparatus includes a storing means for storing an application program verifying an operation of a designed chip and testing a manufactured chip having a plurality of blocks, an I/O file, and a test vector; an interface means controlling a data transmission between the storing means and the chip, and having a data applying means for applying the I/O file and/or the test vector outputted from the storing means and a data storing means for storing data outputted from the chip; and a computer including a CPU for performing and controlling the application program.

Abstract: A semiconductor power network decoupling capacitance (decap) budgeting problem is formulated to minimize the total decap to be added to the network subject to voltage constraints on the network nodes of a semiconductor circuit design. Voltage constraints on the decap to be added are taken into consideration such that the decap can be distributed throughout a hot spot region of the semiconductor circuit design and not be limited to placement at a single location in the circuit. Dynamic network voltages are at all times maintained greater than a user-specified threshold voltage level.

Abstract: In a design system using virtual hardware models, a filtering manager for filtering execution results and determining which software instructions are candidates for restructuring. In some examples, illegal address range instructions are identified based on exception records and restructured software instructions may redirect memory access to an appropriate memory location thereby enabling the use of hardware device drivers in conjunction with hardware emulations, simulations or virtual models without requiring driver source code modifications. Using different filtering criteria, some or all legal and/or illegal memory access software instructions may be redirected to mapped memory locations enabling control over memory access functions. In some cases, debugging tools may be configured or altered to reduce, limit or disable exception handling trace messages, thereby improving overall processing performance by eliminating or reducing unnecessary or burdensome error or trace report generation.

Abstract: A method and apparatus for producing predictive performance and capacity information employing a type of factory to reduce the ongoing cost of providing simulation models to answer questions raised by the various business entities is provided. To achieve this, a continual process for providing on-going performance information is provided. The core concept is the development and long-term reuse of component models to create other, more broadly scoped performance models. This requires the implementation of standard simulation model constructs to facilitate reuse, processes for the development of models and their use by clients, and a stable yet flexible repository for component models. The invention comprises processes, standards, templates, and software tools that implement a performance service that consists of the long term maintenance of predictive performance models for repeated use by lines of business to provide capacity planning information.

Abstract: A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint.

Abstract: A system and method of designing the physical shape of and determining the electromagnetic characteristics of a bondwire in an electrical circuit, comprising the steps of enabling a user to define the position of the bondwire in the electrical circuit layout, defining the position and loop shape of the bondwire in a 3D representation of the electrical circuit, segmenting the bondwire into discrete segments, determining the electromagnetic characteristics of each of the bondwire segments thereby to determine the overall electromagnetic characteristics of the bondwire.

Abstract: A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over a set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.

Abstract: Techniques directed to realizing and verifying a logic model design are provided by first dividing the logic model design into two or more logic portions. The various model portions can then realized to form various realized logic portions. A first realized logic portion can then be wrapped and formally verified against its respective model. The wrapper can then be verified by first applying the wrapper to a second logic model portion and a second realized logic portion, then formally verifying them against each other. The resulting output can then be used to prove wrapper correctness.

Abstract: Various embodiments of systems and methods are described in which system simulation techniques are combined with graphical programming techniques in a common environment. For example, various embodiments of the methods comprise displaying a graphical data flow diagram connected to a system diagram, e.g., where the graphical data flow diagram and the system diagram are displayed together in a compound diagram. In the displayed compound diagram, the graphical data flow diagram may be connected to the system diagram, e.g., by a line or wire. In one embodiment the wire may visually indicate that the graphical data flow diagram is executable to produce a value that is provided as an input signal for a simulation performed based on the system diagram. In another embodiment the wire may visually indicate that the graphical data flow diagram receives an output value from the system simulation as input.

Abstract: The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added.

Abstract: An automated model componentization feature systematically converts duplicate or otherwise amenable patterns in a model into references. Multiple references are simplified to one unit that contains the otherwise duplicated functionality. Duplicated or selected functionality is identified based on a number of arguments that may be user supplied. These arguments include the level of polymorphism (i.e., which of the sample times, dimensions, and data types can be propagated in) but also the maximum size of the patterns to look for to address the general trade-off of generating few partitions with many blocks or many partitions with few blocks and which modeling constructs are used (e.g., whether Go To/From connections such as in Simulink® are present). Model conversions can result in potentially disjoint partitions.

Abstract: A computer-based simulation process executes a checkpoint operation while simulating behavior of an electronic circuit by forking an active checkpoint process having the same state as the original simulation process. While simulation time for the simulation process continues to increase after executing the checkpoint operation, simulation time for the checkpoint process remains unchanged so that the checkpoint process remains in the state of the simulation at the simulation time it executed the checkpoint operation (the “checkpoint time”). When the checkpoint process subsequently receives a request to resume simulating the circuit, it forks a new simulation process that mimics the original simulation process as of checkpoint time, and the new simulation process then begins to advance its simulation time, thereby enabling it to re-simulate behavior of the electronic circuit previously simulated by the original simulation process starting from the checkpoint time.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and a first epitaxial growth mask set (309) from the first data set, wherein the first epitaxial growth mask set is derived from the first data set by removing a subset (305) of the tiles defined by the first data set and incorporating the subset of tiles into the first epitaxial growth mask set; and (c) reconfiguring the first trench CMP mask set to account for the first epitaxial growth mask set, thereby defining a second trench CMP mask set (308).

Abstract: A method and system is disclosed for a multi-chassis emulator. A user can select between chassis and view additional information about the chassis of interest. In one embodiment, once the user selects a chassis, further information about the chassis can be displayed, such as through folders and files. The user can then navigate through the folders to the desired information for display. In yet another embodiment, after the user has selected a chassis of interest, the user can select particular boards in that chassis and view physical information about the board of interest, such as which ICs on the board are faulty.

Abstract: The present invention provides methods and apparatuses for an electromagnetic simulator. The method for circuit simulation comprises the steps of discretizing the circuit element into charge elements and current elements, generating internal data structures to include the charge elements and current elements wherein the internal data structures include Mixed-Potential Integral Equation Green's functions and Partial Element Equivalent Circuit (PEEC) incident matrixes, and calculating relationship between the charge elements and current elements using multilayer Green's function to provide electromagnetic interactions in the internal data structures.

Abstract: Exemplary methods, apparatuses, and products are described for creating a behavioral model of a hardware device for use in a simulation environment. The behavioral model is created by an iterative process that includes receiving in a simulated hardware device from a simulated device under test (‘DUT’) a stimulus waveform. The stimulus waveform includes data representing a number of stimuli. In response to receiving the stimulus waveform, the simulated hardware device presents a recorded response waveform from a recorded response file to the DUT. The stimulus waveform is also recorded. The recorded stimulus waveform is presented to the hardware device. A response waveform that results from presenting the recorded stimulus waveform to the hardware device is recorded in the recorded response file.

Abstract: Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the design may be generated and model checking applied to the abstraction. Results obtained using these techniques may be extended by performance analysis and/or verification of sequential operations.

Abstract: An ASIC based hardware accelerated simulation engine accelerates logic verification of integrated circuit designs utilizing a field of ASIC chips interconnected by direct connections. Communication between the chips has to be accomplished by switching technology internal to the chips. The switching technology employing programmable cross-point switches; i.e. hardware elements with input, output and command ports which propagate signals from the input ports to the output ports following a given permutation determined by values on the command port. The ASIC chip contains an instruction memory to program the logic elements thereof. A conveyor belt based implementation of the programmable cross-point switches provides reduced command bit requirements.

Abstract: A verification apparatus that efficiently performs hardware verification and software verification in the development of a system LSI with great accuracy. At the hardware verification, an equivalence verification section compares the result of the simulation of an HDL model by a logic simulator and an expected value generated from an expected value calculation model and verifies whether there is equivalence between them. At the software verification, the expected value calculation model is used via an interface section and a firmware is verified by a software debugger. The expected value calculation model is used as an expected value generation model at hardware verification time and is used as a C model of hardware at software verification time. By using the expected value calculation model both for the hardware verification and for the software verification in this way, verification can efficiently be performed with great accuracy.

Abstract: A better configuration for a computerized system is determined by performing a first stage and a second stage. In the first stage, the performance of each system configuration, including candidate configurations and a standard configuration, is evaluated, and the number of scenarios needed in the second stage is determined. In the second stage, the performance of each scenario of the standard configuration is evaluated, and the mean thereof is determined. For each candidate configuration, the performance of each scenario of the candidate configuration is evaluated, and the mean thereof is determined. Where the candidate configuration's mean is greater than the standard configuration's mean by a threshold, it is selected as the better configuration. Where no candidate configuration's mean is greater than the standard configuration's mean by the threshold, the standard configuration is selected as the better configuration.

Abstract: In a method, system and computer readable medium for determining a composite circuit model of a 3D geometry, first and second sides of an analytical model of the 3D geometry are discretize into first and second surface and/or volume meshes. For each mesh, a current that flows in each cell thereof and the a voltage induced in the cell in response to the application of an exemplary bias to the geometry are determined. For each mesh, from the currents flowing in the cells thereof and voltages induced in the cells thereof, a corresponding circuit model is determined. The circuit models of the meshes are then combined to form a composite circuit model for the geometry.

Abstract: A method and system for modeling and calibrating duty cycle distortion (DCD) of a Serializer and Deserializer (SerDes) device, including first generating a clock DCD signal. Once the clock DCD signal is generated, it is calibrating based upon results obtained from a filtering process of the clock DCD signal. Once the clock DCD signal is calibrated, a data DCD signal is generated and calibrated based upon results obtained from a filtering process of the data DCD signal.

Abstract: A database-aided circuit design system and method therefor is provided, which can be utilized to detect problems of the product in an early design stage through the early design stage error-detection function, by making use of an artificial intelligence simulation database, storing the determination criterions for the optimized circuits, searching for failure generating factors and correcting the errors relative to the problems generated, based on the post production stage error-diagnosis function, in cooperation with the records stored in the artificial intelligence simulation database after the product has been actually produced, thus achieving the reduction of the product design and development costs, shortening the product market delivery time, and raising the competitiveness of the product.

Abstract: An automated method for checking electrostatic discharge (ESD) guidelines ensures that a sufficient number of ESD protection cells have been provided in the neighborhood of each pad in an integrated circuit design to ensure adequate current sinking and voltage clamping during the occurrence of an ESD event.

Abstract: Systems, methods, software, and techniques can be used to provide and monitor simulation environments including one or more model components. A particular model component can have multiple different versions of the model component having varying levels of abstraction. Executing model components are monitored, and depending on certain performance characteristics, a model component can be replaced with a different version of that model component.

Abstract: A computer-implemented method may include defining an input bus signal in a graphical block diagram model by associating the input bus signal with a first group of signals, at least two of the first group of signals having a different data type; defining an output bus signal in the graphical block diagram model by associating the second bus signal with a second group of signals, each of the second group of signals corresponding to one of the first group of signals; defining an input to a non-virtual operation block in the graphical block diagram model as the input bus signal; defining an output to the non-virtual operation block in the graphical block diagram as the output bus signal; and simulating an operation performed on the input bus signal by the non-virtual operation block, the operation being performed on each of the first group of signals and output to each of the second group of signals.

Abstract: A method, apparatus and system for accepting a plurality of user-selected properties pre-designated for detecting errors in portions of a circuit, accepting a plurality of user-selected erroneous outputs, each of which may correspond to one of the plurality of user-selected set of properties, executing a simulation of the circuit for each of the plurality of user-selected properties, detecting in the output of the simulation, one of the plurality of user-selected erroneous outputs of the circuit for the corresponding one of the plurality of user-selected properties, and performing error correction on the circuit for the corresponding one of the plurality of user-selected properties. A method, apparatus and system for automatically selecting a subset of a set of inputs which when input into a circuit simulation generate erroneous output data to a primary output of the circuit and performing error correction on the circuit therewith. Other embodiments are described and claimed.

Abstract: Embodiments relate to a method of predicting a drain current that may accurately predict drain current in a linear region, a saturation region, and a breakdown region by modeling a drain current in the breakdown region, in which inconsistency occurs when a drain current depending on a drain voltage is calculated by a related are BSIM3-based modeling scheme, by an expression with a ternary operator, and adding the modeled drain current to the result of a related art BSIM3-based modeling scheme.

Abstract: A methodology for obtaining improved prediction of CA resistance in electronic circuits and, particularly, an improved CA resistance model adapted to capture larger than anticipated “out of spec” regime. In one embodiment, a novel bucketization scheme is implemented that is codified to provide a circuit designer with considerably better design options for handling large CA variability as seen through the design manual. The tools developed for modeling the impact of CA variable resistance phenomena provide developers with a resistance model, such as conventionally known, modified with a new CA model Basis including a novel CA intrinsic resistance model, and, a novel CA layout bucketization model.

Abstract: Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit design having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.

Abstract: Techniques are described for performing analysis of circuits with nonlinear circuit components such as transistors based on a two-stage Newton-Raphson approach.

Abstract: Disclosed is a method in which a simulation is performed using a macro model for carrying out a simulation of a high-withstand-voltage MOSFET. The macro model is obtained by adding first and second JFETs to drain and source sides, respectively, of an NMOSFET; connecting one end of a first diode to a gate of the first JFET and connecting the other end of the first diode to the source of the NMOSFET; and connecting one end of a second diode to a gate of the second JFET and connecting the other end of the second diode to the drain of the MOSFET.

Abstract: Disclosed are an apparatus and a method for modeling a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor). The method can include the steps of: establishing an equation and a variable that determine the driving current characteristics of the MOS transistor; generating a random number; converting the random number such that the random number has a value satisfying vertex points in an equation of a rotated lozenge and determining a variation degree of the variable based on the value of the random number; and outputting driving current distribution of the MOS transistor by using the equation and the variation degree of the variable.