Abstract: A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. When simulating performance, scalars for transient performance are determined for strongly couple components. The technique accurately estimates of the performance (e.g., transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.

Abstract: In this disclosure, based on change item definition information concerning system LSI development and design, software used for development and design of a system LSI that contains a processor having optional instructions defined therein is operated, and system LSI hardware description, verification environment and a development and design tools are generated, thus making it possible to develop a system LSI optimal to an application within a short period.

Abstract: A method, a system, and an apparatus for quantification of the quality of diagnostic software by applying a coverage tool are provided, wherein the diagnostic software is used for testing a computing system. The method involves executing the diagnostic software in an Integrated Circuit (IC) verification environment. The diagnostic software is executed by a Virtual Computer-processing Unit (V-CPU), which models (Central Processing Unit) CPU of the computing system to be tested.

Abstract: Methods and apparatus are described that allow an integrated circuit designer to design integrated circuits for more than one process technology using a single master design environment. The master design environment is achieved, in part, by the creation of a centralized master database that comprises device models belonging to more than one process technology. Creation of the master database occurs by parsing a plurality of external databases comprising device models belonging to more than one process technology. The use of a single master design environment simplifies the task of designing an integrated circuit, and also reduces the chance of error.

Abstract: The present invention provides a method, apparatus and program-product for a self-healing, reconfigurable logic emulation system, wherein if a signal wire becomes faulty in an emulation cable during an emulation run, the runtime software can automatically reconfigure the emulator to reroute the data destined for the faulty signal wire across a spare wire. Such a feature enables a user to restart the emulation run without having to recompile the simulation model to account for the hardware fault.

Abstract: An open-loop and closed-loop control unit for a safety-relevant apparatus, in particular for aviation applications, has a computer unit with a number of computer inputs and computer outputs, and a circuit unit with a number of circuit inputs and circuit outputs. The circuit unit has hardware components for simulating some of the logic operations that can be carried out in the computer unit. The circuit inputs and computer inputs that correspond to one another with respect to the simulated logic operations are each connected in parallel to a signal input line. The computer outputs and circuit outputs which correspond to one another with respect to the simulated logic operations are each connected to a decision-making unit, by which an output signal for open-loop control of the safety-relevant apparatus can be emitted as a function of the correspondence between the signals from the computer output and from the circuit output.

Abstract: A method for designing a system on a programmable logic device (PLD) includes translating a timing requirement of the system into a geographical constraint. Resources on the PLD are fitted onto locations on the PLD in response to the geographical constraint.

Abstract: A method of generating an application programming interface (API) for an electronic circuit. A graphical user interface is displayed through which a user can initiate generation of the API. A component is selected from a plurality of components for placement in said electronic circuit. The component represents an implementable function in the electronic circuit. The component is configured using the graphical user interface. The data pertaining to the selected component and the configuration of the component is stored. The graphical user interface is utilized to access the stored data. The interface is initiated to invoke a processing of said data which causes a generation of the application programming interface. The application interface is for controlling the function of the component in said electronic circuit.

Abstract: A multiple-pass synthesis technique improves the performance of a design. In a specific embodiment, synthesis is performed in two or more passes. In a first pass, a first synthesis is performed, and in a second or subsequent pass, a second synthesis or resynthesis is performed. During the first synthesis, the logic will be mapped to for example, the logic structures (e.g., logic elements, LUTs, synthesis gates) of the target technology such as a programmable logic device. Alternatively a netlist may be provided from a third party. Before the second synthesis, a fast or abbreviated fit may be performed of the netlist to a specific device (e.g., specific programmable logic device product). Before the second synthesis, the netlist obtained from the first synthesis (or provided by a third party) is unmapped and then the second synthesis is performed. Since a partial fit is performed, the second synthesis has more visibility and optimize the logic better than by using a single synthesis pass.

Abstract: A method for device level simulation of a circuit modeled by a set of CCR graphs, a computer system programmed to perform such a method, and a computer readable medium which stores code for implementing such a method. Typically, the circuit includes MOS transistors having unknown gate potentials, each CCR graph includes a top rail, and a bottom rail, and variable nodes, each of the transistors having unknown gate potential is modeled in the CCR graphs as a selectable resistor having a selected one of a first resistance and a much larger second resistance, and the method includes the steps of determining potentials at variable nodes of one of the CCR graphs with each selectable resistor of the graph having its first resistance (and also with each selectable resistor of the graph having its second resistance) without determining effective resistances between the variable nodes of the graph and the top rail or bottom rail.

Abstract: A computer-implemented method computes the steady-state and control voltage of a voltage controlled oscillator, given a known frequency or a known period of oscillation of the voltage controlled oscillator. Differential algebraic equations representative of the voltage controlled oscillator are generated, where the differential algebraic equations includes a known period or frequency of oscillation and an unknown control voltage of the voltage controlled oscillator. The differential algebraic equations are modified using a finite difference method, a shooting method, or a harmonic balance method, to obtain a set of matrix equations corresponding to the differential algebraic equations. A solution to the matrix equations is obtained using a Krylov subspace method, using a preconditioner for the Krylov subspace method that is derived from a Jacobian matrix corresponding to the matrix equations, where the solution includes the control voltage of the voltage controlled oscillator in steady state.

Abstract: A method and an apparatus for indirectly simulating a semiconductor integrated circuit (IC) are described. A circle chain is formed using input pins and output pins to provide an intellectual property (IP) core model that substitutes for a real IP core circuit. A test bench for the IP core model is generated, the semiconductor IC that includes the IP core model is integrated using the generated test bench, and the semiconductor IC is simulated.

Abstract: Input parameters for a circuit that is to be characterized are provided. A characteristic of the circuit is determined. A simulated output parameter of the circuit is determined using a supervised learning algorithm in accordance with the characteristic and at least two of the input parameters. A first pass/fail criterion is determined in accordance with the simulated output parameter.

Abstract: A method (10) of reducing a size of a netlist for a target architecture can include the steps of creating (12) a netlist of objects for the target architecture, identifying (14) objects specific to the target architecture that are repeated regularly to identify potential dummy objects, creating (15) a list of objects used by a design in the target architecture, and forming (16) a list of unused objects in the target architecture from the netlist of objects and the list of objects used by the design. The method can further include the steps of replacing (18) at least one object in the list of unused objects with an appropriate dummy object to form a modified netlist and simulating (19) the modified netlist.

Abstract: A method for building a hierarchical representation of a circuit for simulation includes 1) receiving a source file containing SPICE-like netlist descriptions of the circuit in a flattened representation; 2) generating a primitive database using the source file, where the primitive database includes a geometries-describing section for storing a plurality of primitive subcircuit blocks; 3) generating an instance database using the geometries-describing section, where the instances database includes instance subcircuit blocks corresponding to explicitly-expressed primitive subcircuit blocks with predefined geometric values; 4) generating a simulation database using the instance database, where the simulation database includes simulation subcircuit blocks corresponding to fully-flattened instance subcircuit blocks; and 5) simulating the circuit using the simulation database, the instance database, and the primitive database.

Abstract: A system and method are provided including a component in communication with a plurality of memory circuits and a system. The component is operable to interface the memory circuits an the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The component is further operable to perform a power saving operation.

Abstract: A simulation model of BT instability of a transistor in a semiconductor integrated circuit, wherein a bias condition of at least one terminal among the drain terminal, the source terminal and the substrate terminal of the transistor is set up as an independent bias condition from other terminals; and then a model parameter of the transistor is changed in the set bias condition.

Abstract: In one embodiment, the invention is an apparatus for testing differential delay correction of network elements using virtual concatenation. The apparatus includes a first PRBS (pseudo-random bit stream) generator dedicated to a first tributary. The apparatus also includes an interface between the first PRBS generator and a tester. The apparatus further includes an interface between the first PRBS generator and a device under test. The apparatus may further include a second PRBS dedicated to a second tributary. The apparatus may also include a control logic block to control the first PRBS generator and the second PRBS generator, and coupled to the first PRBS generator and the second PRBS generator.

Abstract: A method of and an apparatus for designing a test environment providing reliable test signal integrity, and of evaluating performance of the test environment and an electronic device during testing of the electronic device. A virtual test environment is created emulating an actual test environment in which the electronic device is to be tested. A virtual calibration of the virtual test environment may be performed, to more closely emulate the actual test environment. A virtual device emulating the actual electronic device is implanted into the virtual test environment, and that virtual device is stimulated with an input test signal emulating the actual input signal that is applied to the actual electronic device in the actual test environment. The integrity of the input test signal and the resulting output signal is evaluated.

Abstract: By using, as a model expression, an expression showing an inverse proportion between a change rate ?Idsat/Idsat of saturated current value and a product of a gate protrusion length E1 and a gate width Wg of a transistor and a coefficient, modeling is executed for a transistor property that depends on the gate protrusion length. This provides a circuit simulation that takes into consideration the gate protrusion length of a gate electrode.

Abstract: Behaviors of a transistor during a dose rate event can be modeled using a circuit simulation software package. A subcircuit model replaces a transistor in a circuit design to be simulated. The subcircuit model can be in the form of a schematic-based representation or a netlist. The subcircuit model provides a model of a source junction and a drain junction in the transistor during the dose rate event. The subcircuit model also includes the size of the transistor being replaced and the dose rate of the dose rate event. Once the transistor is replaced with the subcircuit model, a dose rate simulation may be performed to determine the dose rate hardness of the circuit design.

Abstract: New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.

Abstract: Present herein is a system and method for arbitration in multi-threaded programming. Task calls are directed to a task wrapper that associates the task call with a particular unique identifier, and stores parameters provided by the task call at memory locations associated with the unique identifier. The execution of the task is handled by a task loop. The task loop queues a plurality of memory portions into a circular queue. The contents of the queue are serially provided to the task, and the results are serially written to the circular queue and provided back to the calling threads.

Abstract: A complete hardware design environment is available through a system level simulator. This hardware design environment provides a bit accurate simulator for carrying out hardware simulations in the system level simulator. These simulations take advantage of the computational capabilities of the simulation processor. To take advantage of the simulation processor's resources (e.g., certain FPU components), the signals used in the simulation are made to conform to the native word type of the simulation processor. The hardware blocks deployed in a design frequently use non-native (from the simulation processor's perspective) word types. The bit accurate simulator casts words (signals) defined in the hardware design from a non-native format to a multi-bit native format suitable for use by the simulation processor. At various stages in the simulation, the simulator checks the “value” of the signal to determine whether that value is allowed by a word format specified by the hardware design.

Abstract: A method of building a verification environment within a software-based development tool for a programmable logic device can include determining an interface description for a bus functional model. The method further can include creating a hardware specification for the programmable logic device. The hardware specification can reference the bus functional model and at least one bus-based module interacting with the bus functional model. The verification environment for the programmable logic device can be automatically generated according to the interface description and the hardware specification.

Abstract: An apparatus for and method of generating test cases for testing simulated logic circuit designs. The test cases are basically generated automatically in a random fashion, manually, or using some combination of automatic and manual techniques. Each test case has a corresponding success indication. These test cases are provided to the simulated logic design for execution. Following execution, each test case is rated pass or fail by comparison of the result with the corresponding success indication and a reason for failure is recorded for each failure. A significantly smaller list of test cases is prepared by eliminating test cases which do not have a unique reason for failure. The smaller list of test cases is then presented for a simulation run which requires substantially less simulator time and substantially less manual analysis of the results.

Abstract: Methods of reducing the amount of logic in a digital circuit without affecting the functionality of the circuit. A circuit description and one or more test patterns are supplied to a fault simulator. The fault simulator runs the test patterns on the circuit, and identifies any nodes that did not transition in either direction (“non-transitioning nodes”). If the test patterns provide full coverage of the desired functionality for the circuit, each of the non-transitioning nodes is unnecessary to the logical functionality of the circuit in the target application. Therefore, the logic driving the non-transitioning nodes is removed from the circuit. The modified circuit can then be re-simulated, if desired, to verify that the relevant functionality of the circuit has not changed.

Abstract: The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part” of all nets and cells of a RRAM tiling netlist are set to a value 0. A boolean value 0 is assigned to all ground nets of the RRAM tiling netlist, and a boolean value 1 is assigned to all power nets of the RRAM tiling netlist. The RRAM tiling netlist is verified for each customer memory Memk, k=1, 2, . . . , N.

Abstract: The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the provided original layout pattern; (2) simulating DI CD at predefined boundary exposure conditions using the provided original layout pattern; (3) if the DI CD from step (1) meets the target DI CD definition, and the DI CD from step (2) meets process window specifications, convergence takes place; and (4) modifying the layout pattern and repeating steps (2) through (3) until DI CD from step (2) reaches the specification limit if any portion of step (3) is not achieved.

Abstract: A simulation method makes a noise analysis based on parameters including a conductor resistance which takes skin effect into consideration. The simulation method calculates a first resistance of one of conductors having a largest cross sectional area, obtains a predetermined pitch which saturates a diagonal component of a second resistance of a conductor with reference to the first resistance and makes the diagonal component approximately constant, by varying a pitch of the conductors, calculates the parameters for each pitch with respect to one of the pitches larger than or equal to the predetermined pitch and the pitches smaller than the predetermined pitch, and substitutes the parameters calculated for the one of the pitches with respect to the other of the pitches, and outputs calculation results.

Abstract: One embodiment of the present invention is a method for estimating a power requirement of a circuit design that includes steps of: (a) selecting a set of targeted Energy Arcs and/or Power Arcs; (b) creating one or more circuit states using the set of targeted Energy Arcs and/or Power Arcs; (c) back-tracing the one or more circuit states over one or more simulation clock cycles to form a start circuit state and a stimulus segment; (d) simulating the stimulus segment in forward time progression and determining which Event Arcs in Energy Arcs and/or which Condition Arcs in Power Arcs are satisfied at each stimulus clock cycle; and (e) recording data at each stimulus clock cycle that is utilized to estimate the power requirement.

Abstract: According to an aspect of the present invention, there is provided a simulation circuit pattern evaluation method including: designing an aggregate of simulation circuit patterns, which simulate a circuit pattern of a semiconductor integrated circuit, by combining plural geometrical structure defining parameters respectively having at least two states in such a manner that the respective states appear the same number of times in the respective geometrical structure defining parameters; forming the aggregate of the simulation circuit patterns on a substrate; and evaluating the formed aggregate of the simulation circuit patterns.

Abstract: A system and method for testing a development device includes extracting multiple parameters of the development device from a product specification for the development device. The parameters being arranged in a predetermined first order. The parameters are stored in a testing data file. The testing data file can be input into a test bench system being coupled to the development device. The test bench system can test the development device.

Abstract: A process and method for projection beam lithography which utilizes an estimator, such as a Kalman filter to control electron beam placement. The Kalman filter receives predictive information from a model and measurement information from a projection electron beam lithography tool and compensates for factors which cause beam placement error such as wafer heating and beam drift. The process and method may also utilize an adaptive Kalman filter to control electron beam placement. The adaptive Kalman filter receives predictive information from a number of models and measurement information from a projection electron beam lithography tool and compensates for factors which cause beam placement error such as heating and beam drift. The Kalman filter may be implemented such that real-time process control may be achieved.

Abstract: A method for predicting functionality of an integrated circuit segment to be lithographically printed on a wafer. Initially there is provided a two-dimensional design of an integrated circuit, including an integrated circuit segment having critical width, and a two-dimensional printed image of the critical width integrated circuit segment is simulated. The method then includes determining a ratio of perimeters or areas of the designed critical width integrated circuit segment to the simulated printed critical width integrated circuit segment, and predicting functionality of the critical width integrated circuit segment after printing based on the ratio of perimeters or areas.

Abstract: Disclosed is a permanent recloser simulator feature for use in a single-pole trip capable recloser control. The permanent recloser simulator feature includes a first logic circuit capable of enabling and disabling operation of the permanent recloser simulator feature in response to receipt of a binary logic signal, and a second logic circuit coupled to the first logic circuit where the second logic circuit is configured to provide an indication of a status of a first pole to a logic engine of the single-pole trip capable recloser control. The permanent recloser simulator feature may further include a third logic circuit associated with a second pole, and a fourth logic circuit associated with a third pole where both are coupled to the first logic circuit. Disabling means of the first logic circuit allow the first, second, third and fourth logic circuit to permanently reside in logic of the recloser control.

Abstract: Determining ampacity risks in a circuit comprises receiving geometry data of the circuit, initializing boundary conditions, initializing circuit geometry assumptions, modeling the circuit geometry data as a three-dimensional solid, computing non-Fourier heat conduction through the three-dimensional solid model using conjugate gradient numerical analysis with an incomplete Cholesky preconditioner, and generating an output indicative of a location in the three-dimensional solid model where potential thermal damage may occur in response to a predetermined excitation.

Abstract: A design method for a semiconductor integrated circuit includes a first step (S13) of grouping pins that configure a same net into a plurality of groups; a second step (S14) of defining sub-trunk wirings mutually connecting the pins that belong to a same group; a third step (S16) of defining a main trunk wiring substantially parallel to the sub-trunk wirings; and a fourth step (S17) of defining a lead-in wiring connecting at least the main trunk wiring and the sub-trunk wirings. Thus, a plurality of pins are grouped, and the groups are mutually connected by the sub-trunk wirings, making it possible to decrease the number of the lead-in wirings. Thereby, even when the number of nets is large relative to the area of a layout region, a probability of occurrence of nets where automatic wiring is impossible can be greatly reduced.

Abstract: An event queue for use with a software-enabled logic simulation tool can include a heap array and a hash table data structure. The heap array can include time slots organized such that each time slot conforms to heap properties which specify, at least in part, that a root node of the array indicates a time slot having a minimum simulation time value. The hash table data structure can include a plurality of entries, wherein selected ones of the entries specify references to at least one of the time slots.

Abstract: A logic circuit for board power-supply evaluation to be incorporated into a logic device loaded on a product board includes a circuit that simulates an operation of the logic device so that utilization rate is variable at an arbitrary frequency by use of a predetermined circuit in all available logic elements of the logic device; a circuit that judges normality/abnormality of an operation of the operation simulation circuit; a utilization control circuit that varies and controls utilization rate of the logic device by controlling execution of an operation of the operation simulation circuit based on a judgement result of the operation judgement circuit and sets a utilization rate when the operation simulation circuit is instructed to stop the operation; and a utilization output circuit that outputs the judgement result of the operation judgement circuit and the utilization rate set by the utilization control circuit to the outside.

Abstract: Process for determination of properties, particularly, the integrity, of an integrated circuit by calculation, wherein a calculation-simulated image of the circuit is compared with a design of the circuit, and deviations between the image and design are detected.

Abstract: An ESD protection device modeling method of modeling an electrical characteristic of an electrostatic discharge (ESD) protection device for simulating a circuit that include the ESD protection device, comprising the steps of (114) setting a parameter of at least one specific element that affects the electrical characteristic of the ESD protection device; and (116) modeling the electrical characteristic of the ESD protection device with the parameter of the specific element.

Abstract: A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.

Abstract: A method, system and computer program product for preserving constraints is disclosed. The method comprises receiving an initial design including one or more targets, one or more primary inputs, one or more constraints and one or more state elements. A cut of the initial design including one or more cut gates, and a relation of one or more values producible to the one or more cut gates in terms of the one or more primary inputs and the one or more state elements is computed. The relation is constrained to force one or more constraint gates representing the one or more constraints to evaluate to a forced valuation, and one or more dead-end states of the constraints are identified. The inverse of the dead-end states is applied as don't cares to simplify the relation and the simplified relation is synthesized to form a first gate set. An abstracted design is from the first gate set and verification is performed on the abstracted design to generate verification results.

Abstract: An electrical circuit can be described with a reference model that has a plurality of states and a plurality of state transitions. Acceptable and/or unacceptable instruction sets are predefined for each state. Acceptable and unacceptable instruction sets are generated randomly in succession from the reference model and applied to a mapping of the electrical circuit for processing. By comparing the instruction sets processed by the mapping of the electrical circuit with the instruction sets determined from the reference model, conclusive information relating to the mapping of the electrical circuit is obtained.

Abstract: A method for tracing paths within a circuit includes receiving a transistor level netlist description. After receiving the transistor level netlist, convert the transistor level netlist to a transistor level data structure. Then, convert the transistor level data structure to a set of channel connect groups (CCG). A directed graph of the CCG may be generated.

Abstract: A method for adjusting a data set defining a set of process runs, each process run having a set of data corresponding to a set of variables for a wafer processing operation is provided. A model derived from a data set is received. A new data set corresponding to one process run is received. The new data set is projected to the model. An outlier data point produced as a result of the projecting is identified. A variable corresponding to the one outlier data point is identified, the identified variable exhibiting a high contribution. A value for the variable from the new data set is identified. Whether the value for the variable is unimportant is determined. A normalized matrix of data is created, using random data and the variable that was determined to be unimportant from each of the new data set and the data set. The data set is updated with the normalized matrix of data.

Abstract: The present invention includes a method for generating a model of a circuit having an input port and an output port. The method determines an amplitude for current leaving the output port at a frequency ?k when a signal that includes a carrier at ?j modulated by a signal Vj(t) is input to the input port, wherein ?k is a harmonic of ?j. The determined amplitude is used to determine values for a set of constants, ak, such that a function fk(V,ak) provides an estimate of the current, Ik(t), leaving the output port at a frequency ?k when a signal having the form V ? ( t ) = Re ? ? k = 1 , H ? V k ? ( t ) ? exp ? ( j? k ? t ) is input to the input port. Here Vk(t) is a component of a set of values V. The fk(V,ak) are used to provide a simulator component adapted for use in a circuit simulator.

Abstract: A code coverage tool provides that a netlist is instrumented with gates for providing a comparison of an output of the design gates on one cycle with their output on a next cycle to determine if the gate was exercised during an emulation.

Abstract: A method for encoding elements of an electronic design generates a flattened hierarchy of a parameterized cell of the electronic design, selects common and unique parameters of each element in the parameterized cell, and generates a physical design quantization characteristic value from the selected common and unique parameters.