Circuit Simulation Patents (Class 703/14)
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Patent number: 7289945Abstract: In one embodiment, an interconnect structure may be analyzed to determine electromagnetic characteristics of the structure by identifying structure seeds corresponding to the structure; modeling the structure seeds to obtain field patterns; and processing the field patterns to obtain the electromagnetic characteristics.Type: GrantFiled: October 28, 2002Date of Patent: October 30, 2007Assignee: Intel CorporationInventors: Dan Jiao, Mohiuddin Mazumder, Changhong Dai
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Publication number: 20070244884Abstract: In one embodiment, a method for ranking webpages is provided. The method includes generating a web circuit model having a node representing each webpage. The model is simulated to identify the potential at each node. The webpages can then be ranked according to the potentials of the nodes to which the webpages correspond.Type: ApplicationFiled: April 17, 2007Publication date: October 18, 2007Inventor: Baolin Yang
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Patent number: 7283945Abstract: A state-transition system is extracted from a high-level description of a design. Assumptions regarding states of the design are determined for an initial clock cycle. Linear arithmetic relations are introduced to these assumptions. Guarantees are determine that provide properties of the design that hold after a fixed number of clock cycles. Symbolic simulation is performed for a limited number of clock cycles on the state transition system of the design. If the guarantees hold once simulation is performed, the design is verified. Otherwise, counter-examples are generated.Type: GrantFiled: September 18, 2001Date of Patent: October 16, 2007Assignee: Fujitsu LimitedInventor: Sreeranga P. Rajan
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Patent number: 7283943Abstract: Techniques for modeling a circuit cell of a microprocessor or other integrated circuit for hierarchical powergrid analysis are disclosed herein. Distribution coefficients, used to distribute node voltages and capacitances to respective parts of the cell, are determined for each internal node of the cell. Current distribution coefficients may also be determined for each resistor in the cell. Using the distribution coefficients, internal cell capacitances are modeled as port capacitors. Resistive elements are modeled as a resistor network having no internal nodes. Transistor elements are modeled as port current sources. Such a model permits back calculation of internal node voltages and currents.Type: GrantFiled: June 24, 2004Date of Patent: October 16, 2007Assignee: Sun Microsystems, Inc.Inventors: Xiaoning Qi, Anuj Trivedi, Kenneth Y. Yan
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Patent number: 7284218Abstract: A method and a system for inplace symbolic simulation of circuits. This method is applicable to both single clock and multiple clock domain designs. The method performs inplace symbolic simulation by appending slots to the various objects of the circuit. The slot associated with an object is a function of time, and it represents the functionality of the element at a given time. The method comprises the steps of determining a phase-list, determining ticks associated with each object of the circuit. Based on these ticks, slots are generated. Further, relations between the slots of the various objects of the circuit are captured.Type: GrantFiled: March 18, 2005Date of Patent: October 16, 2007Assignee: Calypto Design Systems, Inc.Inventors: Sumit Roy, Gagan Hasteer, Anmol Mathur
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Patent number: 7283942Abstract: The present invention provides techniques for high speed electrical simulation of circuits. According to one embodiment of the present invention, a delay path can be divided into sub-paths called simulation paths. Each simulation path is simulated separately to determine its contribution to the overall delay in the path. According to another embodiment of the present invention, linear and non-linear loads are modeled using linear circuit models to further increase the speed of the simulator. According to another embodiment, driver circuits are simulated using non-linear circuit models. Before a simulation is performed, sample input and output values for the non-linear models are computed and stored in memory. When a circuit design is simulated, the input and output values are accessed from the memory. Intermediate values are determined by interpolating from the values stored memory.Type: GrantFiled: November 26, 2002Date of Patent: October 16, 2007Assignee: Altera CorporationInventor: David Lewis
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Patent number: 7284212Abstract: Reducing the number of computations required to pre-characterize cells in a cell-library. In an embodiment, a worst case vector which propagates most noise on an arc (combination of input pin and output pin) of a cell is determined, and NP characteristics and NIC are generated only for the worst case vector. Noise analysis is then performed using such curves generated from the worst case vector. Since curves corresponding to only the worst case vector may need to be generated, the computational requirements may be reduced. The search ranges in determining the immunity transition points forming the NIC may be reduced, according to some aspects of the present invention. The data corresponding to NIC may be used to generate NP curves, and vice versa to reduce computational requirements further.Type: GrantFiled: July 16, 2004Date of Patent: October 16, 2007Assignee: Texas Instruments IncorporatedInventors: Gaurav Kumar Varshney, Sreeram Chandrasekar
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Patent number: 7280953Abstract: A noise countermeasure determination method includes the step of obtaining an analyzing circuit judgement result by judging acceptability of the analyzing circuit based on a comparison of features of the analyzing circuit and transmission circuit topologies, and outputting an improvement proposal for making the analyzing circuit closer to one of basic types of the transmission circuit topologies depending on the analyzing circuit judgement result.Type: GrantFiled: June 18, 2001Date of Patent: October 9, 2007Assignee: Fujitsu LimitedInventors: Shogo Fujimori, Yasuhiro Yamashita, Ryoji Yamada, Masaki Tosaka, Kazuhiko Tokuda, Jiro Yoneda, Makoto Suwada, Tatsuo Koizumi
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Publication number: 20070233447Abstract: A circuit simulation method for estimating electrical characteristics of a semiconductor device is provided. The circuit simulation method includes: (A) generating a device model parameter of a semiconductor device model used in a circuit simulation; and (B) executing the circuit simulation by using the semiconductor device model and the generated device model parameter. The (A) step includes: (a) generating a plurality of device model parameters with respect to a plurality of different temperatures; and (b) generating the device model parameter corresponding to a specified temperature by interpolating between the plurality of device model parameters.Type: ApplicationFiled: March 29, 2007Publication date: October 4, 2007Inventors: Ryo Miyata, Hironori Sakamoto
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Publication number: 20070233446Abstract: In a feedback simulation method applicable to air-conditioning system, an error signal is fed back when a non-acceptable difference between a simulation value and a required value is found; modification procedures are conducted in response to the error signal and according to system modification criteria to adjust control direction and modify initial parameters for input in next simulation. The feedback and modification are repeated until the system momentum balancing and energy balancing is reached.Type: ApplicationFiled: December 13, 2006Publication date: October 4, 2007Inventor: Hui Jiunn Chen
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Patent number: 7277835Abstract: Computer implemented methods and systems for CAD data exchange, and in particular for creating boundary representations (“breps”) on a feature-by-feature basis are disclosed. According to an embodiment of the techniques described herein, a parameterized feature from a parametric based design system is exported from a source CAD system (404). Iterative steps and complimentary extraction techniques are employed by one or more processors (452, 456) to create an importable design model of the parameterized feature (433), which is imported into a target CAD system (408). While the techniques can include API (436), pattern matching (440), and user emulation (444) techniques, they include a brep per feature (450) technique. By exporting the brep on a per feature (453) basis from the source CAD system (404), the design intent of a CAD designer can be preserved on importation into the target CAD system (408).Type: GrantFiled: August 30, 2001Date of Patent: October 2, 2007Assignee: Proficiency, Ltd.Inventors: Steven Spitz, Ari Rappoport
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Patent number: 7277804Abstract: A method, mechanism, and system for determining an effective resistance for a network of resistors, irrespective of the number of terminals is provided. An aspect of an approach relates to the reduction of any network of resistors to a single resistance value. Another aspect of an approach relates to the application of a power loss calculation to determine the effective resistance. Yet another aspect of an approach relates to the integration of the method/mechanism with an analog simulator.Type: GrantFiled: May 20, 2005Date of Patent: October 2, 2007Assignee: Cadence Design Systems, Inc.Inventors: Ian Gebbie, Ian Dennison, Zsolt Haag, Keith Dennison
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Patent number: 7278125Abstract: A semiconductor integrated circuit pattern verification method includes executing simulation to obtain a simulation pattern to be formed on a substrate on the basis of a semiconductor integrated circuit design pattern, comparing the simulation pattern and the design pattern that is required on the substrate to detect a first difference value, extracting error candidates at which the first difference value is not less than a first predetermined value, comparing pattern shapes at the error candidates to detect a second difference value, combining, into one group, patterns whose second difference values are not more than a second predetermined value, and extracting a predetermined number of patterns from each group and verifying error candidates of the extracted patterns.Type: GrantFiled: July 8, 2005Date of Patent: October 2, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Shigeki Nojima
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Patent number: 7277840Abstract: A method for efficiently detecting bus contention from a register transfer level (RTL) description is provided. A bus contention occurs if more than two components try to propagate data onto a bus at the same time. The provided method simulates possible input combinations and detects whether there is a possibility for a bus contention. In addition, the provided method is designed for testability, therefore using the method, the designer may identify contention that may exist in test mode at the RTL level of the design even when such conditions may not occur in system mode. The method provides the designer with the input combination as well as the RTL statement that caused the contention. The method detects the bus contention by simulating a small number of input combinations.Type: GrantFiled: June 18, 2002Date of Patent: October 2, 2007Assignee: Atrenta, Inc.Inventor: Ralph Marlett
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Patent number: 7272542Abstract: The present invention allows a designer to easily re-target the design optimized for the device of one integrated circuit vendor to the device of another vendor. The designer can start with a set of post-routed boolean equations optimized for a certain target integrated circuit. The present invention allows the automatic generation of a synthesizable, editable, and simulatable HDL description. The designer may edit the HDL code. Another target may be selected. Design optimization and placement and routing can be performed for the new target.Type: GrantFiled: April 30, 2001Date of Patent: September 18, 2007Assignee: Xilinx, Inc.Inventor: Lester S. Sanders
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Patent number: 7269470Abstract: An aligner evaluation system includes (a) an error calculation module configured to calculate error information on mutual optical system errors among a plurality of aligners; (b) a simulation module configured to simulate device patterns to be delineated by each of the aligners based on the error information; and (c) a evaluation module configured to evaluate whether each of the aligners has appropriate performances for implementing an organization of a product development machine group based on the simulated device pattern.Type: GrantFiled: August 8, 2003Date of Patent: September 11, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Takuya Kouno, Shigeki Nojima, Tatsuhiko Higashiki
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Patent number: 7269541Abstract: A system for supporting multi-rate simulation of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) partitioning the circuit into a plurality of group circuits, each group circuit includes one or more leaf circuits, where each leaf circuit produces a predictable set of output signals with a given set of input signals, 2) storing the group circuits in a scheduled event queue in accordance with priority in time which the group circuits need to be simulated, 3) retrieving from the scheduled event queue a set of group circuits for simulation within a predetermined time period, 4) distributing the set of group circuits into a set of predefined event lists, where each of the predefined event list stores one or more group circuits of a corresponding event type, and 5) simulating the one or more group circuits in each of the predefined event list in accordance with a rate of change of signal conditions of each individual group circuit.Type: GrantFiled: November 13, 2003Date of Patent: September 11, 2007Assignee: Cadence Design Systems, Inc.Inventors: Bruce W. McGaughy, Peter Frey, Jun Kong, Baolin Yang
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Patent number: 7269809Abstract: Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design.Type: GrantFiled: June 22, 2005Date of Patent: September 11, 2007Assignee: SiOptical, Inc.Inventors: Kalpendu Shastri, Soham Pathak, Prakash Gothoskar, Paulius Mosinskis, Bipin Dama
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Patent number: 7266488Abstract: A technique for performing signal integrity analysis of a system includes providing a stimulus pattern and a model of the system and performing analog simulation of the model utilizing the stimulus pattern. The stimulus pattern includes sequences of signal transitions with associated transition times and the sequences of signal transitions conform to a bus protocol and the associated transition times are according to characteristics of the system. The stimulus pattern is generated by initializing each of the sequences of signal transitions to an initial signal value and the associated transition times to an initial time, generating subsequent signal values and subsequent transition times by applying protocol rules and calculating timing adjustments for each of a list of transactions; the subsequent signal values and subsequent transition times to be added to the sequences of signal transitions.Type: GrantFiled: March 5, 2003Date of Patent: September 4, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Douglas E. Wallace, Jr., Jonathan P. Dowling
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Patent number: 7266487Abstract: This invention relates to matched instruction set processor systems and method, system, and apparatus to efficiently compile hardware and software designs. A method to efficiently design and implement a matched instruction set processor system includes analyzing and mapping design specifications of the matched instruction set processor into application components, wherein each application component represents a reusable function commonly used in digital communication systems. The method further includes decomposing the matched instruction set processor system into interconnected design vectors. The method also includes examining fields of the interconnected design factors and mapping the interconnected design vectors into specific hardware and software elements.Type: GrantFiled: May 28, 2002Date of Patent: September 4, 2007Assignee: Ellipsis Digital Systems, Inc.Inventor: Hussein S. El-Ghoroury
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Patent number: 7266489Abstract: A method for determining the configuration of a digital design first obtains a set of latch values of a plurality of latches within the digital design. A setting of a Dial instance is then determined based upon the set of latch values by reference to a configuration database that specifies a mapping table uniquely associating each a plurality of different settings of the Dial with a respective one of a plurality of different sets of latch values. The setting of the Dial instance is then output. In one embodiment, the setting of the Dial is contained in a simulation setup file utilized to configure a simulation model to a state approximating the state of the digital design represented by the set of latch values.Type: GrantFiled: April 28, 2003Date of Patent: September 4, 2007Assignee: International Business Machines CorporationInventors: Bryan Ronald Hunt, Wolfgang Roesner, Derek Edward Williams
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Patent number: 7263478Abstract: An extractor extracts descriptions unexecuted in the logic simulation according to code coverage information for the circuit description. An examiner examines whether or not there is a possibility of executing the extracted unexecuted descriptions. A prohibited-input-checker generator generates a test pattern. The test pattern is to execute descriptions including unexecuted descriptions that there is a possibility of executing and excluding unexecuted descriptions that there is no possibility of executing as determined by the examiner. The prohibited-input-checker generator also generates a prohibited-input checker to check whether or not an input pattern of a logic simulation to be carried out is equal to an input pattern of the test pattern to execute the unexecuted description if the test bench is regarded as a prohibited input under a specification at a logic simulation using the test pattern to execute the unexecuted description.Type: GrantFiled: September 25, 2001Date of Patent: August 28, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Takehiko Tsuchiya
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Patent number: 7263477Abstract: The present invention includes a method for modeling devices having different geometries, in which a range of interest for device geometrical variations is divided into a plurality of subregions each corresponding to a subrange of device geometrical variations. The plurality of subregions include a first type of subregions and a second type of subregions. The first or second type of subregions include one or more subregions. A regional global model is generated for each of the first type of subregions and a binning model is generated for each of the second type of subregions. The regional global model for a subregion uses one set of model parameters to comprehend the subrange of device geometrical variations corresponding to the G-type subregion. The binning model for a subregion includes binning parameters to provide continuity of the model parameters when device geometry varies across two different subregions.Type: GrantFiled: June 9, 2003Date of Patent: August 28, 2007Assignee: Cadence Design Systems, Inc.Inventors: Ping Chen, Zhihong Liu
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Publication number: 20070198957Abstract: A circuit simulator includes: a DC analysis section which analyses a static stable potential on a transmission circuit if a capacitor which blocks a DC current while allowing an AC current to pass therethrough is connected in series in the line of the transmission circuit; and an initial potential application section which applies, as an initial potential in the simulation, the stable potential obtained by the DC analysis section to an application position on the upstream side of the capacitor in the flow of the signal through the transmission circuit. The simulator also includes a circuit simulation section which performs the simulation of the transmission circuit under the initial potential applied by the initial potential application section.Type: ApplicationFiled: September 5, 2006Publication date: August 23, 2007Applicant: FUJITSU LIMITEDInventors: Makoto Suwada, Masaki Tosaka, Megumi Nagata
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Patent number: 7260516Abstract: An apparatus, system, and method for optimization. The apparatus, system, and method include a mechanism for ending an optimization when all models within one design tolerance of an optimum model have been simulated.Type: GrantFiled: August 31, 2002Date of Patent: August 21, 2007Assignee: OPTIMUM Power Technology, L.P.Inventors: Glen F. Chatfield, John G. Crandall
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Patent number: 7260797Abstract: One embodiment of the present invention provides a system for estimating parasitic capacitance for an integrated circuit. During operation, the system reads a technology file, which describes the composition of a vertical cross-section of the integrated circuit. Next, the system reads a design file, which specifies the layout of the integrated circuit. The system then identifies a set of dielectric configurations based on information contained in the technology file. It then computes Green's function for each of these configurations. Next, the system estimates a parasitic capacitance using information contained in the design file and using the set of Green's functions.Type: GrantFiled: September 7, 2004Date of Patent: August 21, 2007Assignee: Synopsys, Inc.Inventors: Shabbir H. Batterywala, Narendra Shenoy, Madhav Desai
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Patent number: 7260515Abstract: A method and apparatus for cycle-based simulation of a transparent latch includes classifying a phase of the transparent latch, classifying a phase of an input to the transparent latch, and classifying a phase of a simulation cycle. The transparent latch is simulated as a cycle-based simulation element based on the phase of the transparent latch, the phase of the input to the transparent latch, and the phase of the simulation cycle.Type: GrantFiled: March 28, 2002Date of Patent: August 21, 2007Assignee: Sun Microsystems, Inc.Inventor: Liang T. Chen
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Patent number: 7260799Abstract: A verification method foe an integrated circuit includes identifying an equivalence class including a set of candidate gates suspected of exhibiting equivalent behavior and identifying one of the candidate gates as a representative gate for the equivalence class. Equivalence gates of an XOR gate are sourced by the representative gate and a candidate gate. A speculatively reduced netlist is generated by replacing the representative gate as the source gate for edges sourced by a candidate gate in the original design. The speculatively reduced netlist is then used either to verify formally the equivalence of the gates by applying a plurality of transformation engines to the speculatively reduced netlist or to perform incomplete search and, if none of the equivalence gates is asserted during the incomplete search, any verification results derived from the incomplete search can be applied to the original model.Type: GrantFiled: February 10, 2005Date of Patent: August 21, 2007Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
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Patent number: 7260794Abstract: A design verification system utilizing programmable logic devices having varying numbers of logic processors, macro processors, memory processors and general purpose processors programmed therein is disclosed. These various processors can execute Boolean functions, macro operations, memory operations, and other computer instructions. This avoids either the need to implement logic or the need to compile the design into many gate-level Boolean logic operations for logic processors. Improved efficiency in the form of lower cost, lower power and/or higher speeds are the result when verifying certain types of designs.Type: GrantFiled: September 23, 2003Date of Patent: August 21, 2007Assignee: Quickturn Design Systems, Inc.Inventor: Michael R. Butts
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Patent number: 7260511Abstract: A design aid apparatus includes an input section, an antenna propensity determination section, an output section, and a memory storing design data for a plurality of structures comprising an electronic device to be designed. Conductivity of a structure is determined based on conductivity information of the structure read out from the memory. The antenna propensity determination section determines a contact relation, which expresses a state of electrical contact between a conductive structure having conductivity and another conductive structure, based on information relating to shapes and arrangements of structures stored in the memory. A length of a route between a reference conductive structure and the conductive structure is determined. The antenna propensity of the electronic device is evaluated based on the route length.Type: GrantFiled: February 5, 2003Date of Patent: August 21, 2007Assignee: Fuji Xerox Co., Ltd.Inventors: Osamu Ueno, Hitoshi Arakaki
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Publication number: 20070192078Abstract: A system for providing real-time modeling of an electrical system under management is disclosed. The system includes a data acquisition component, a virtual system modeling engine, and an analytics engine. The data acquisition component is communicatively connected to a sensor configured to provide real-time measurements of data output from an element of the system. The virtual system modeling engine is configured to generate a predicted data output for the element. The analytics engine is communicatively connected to the data acquisition system and the virtual system modeling engine and is configured to monitor and analyze a difference between the real-time data output and the predicted data output.Type: ApplicationFiled: February 14, 2007Publication date: August 16, 2007Applicant: EDSA MICRO CORPORATIONInventors: Adib Nasle, Ali Nasle, Kevin Meagher
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Patent number: 7257802Abstract: A system and method is presented for synthesizing both a design under test (DUT) and its test environment (i.e., the testbench for the DUT), into an equivalent structural model suitable for execution on a reconfigurable hardware platform. This may be achieved without any change in the existing verification methodology. Behavioral HDL may be translated into a form that can be executed on a reconfigurable hardware platform. A set of compilation transforms are provided that convert behavioral constructs into RTL constructs that can be directly mapped onto an emulator. Such transforms are provided by introducing the concepts of a behavioral clock and a time advance finite state machine (FSM) that determines simulation time and sequences concurrent computing blocks in the DUT and the testbench.Type: GrantFiled: October 26, 2004Date of Patent: August 14, 2007Assignee: Mentor Graphics CorporationInventors: Jyotirmoy Daw, Sanjay Gupta, Suresh Krishnamurthy
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Patent number: 7257524Abstract: A fully synthesizeable Simulation Control Module (SCM) controls and monitors the simulation of a design under test (DUT). A clock generator within the SCM and a Software clock facility residing on the host workstation are responsible for providing the clocks for the DUT. The SCM and the hardware clock facility are dynamically generated at build time to suit the needs of the DUT. They maximize performance by automatically generating clock waveforms for designs containing multiple asynchronous clocks, thereby decreasing the frequency of accelerator-workstation interaction. The software clock facility has the ability to directly drive the DUT and is responsible for managing the simulation time and clock parameters. The SCM is also responsible for monitoring an abort condition such as a trigger to execute an external software model. The SCM and the clock facilities allow the hardware accelerator to efficiently support multiple asynchronous clock domains, execution of external software models and co-simulation.Type: GrantFiled: September 18, 2002Date of Patent: August 14, 2007Assignee: Quickturn Design Systems, Inc.Inventors: William John Schilp, Pramodini Arramreddy, Krishna Babu Bangera, Makarand Yashwant Joshi
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Patent number: 7257525Abstract: A method for simulating a circuit includes representing the circuit as a hierarchically arranged set of branches, including a root branch and a plurality of other branches logically organized in a graph. The method further includes arranging the subcircuits from the hierarchically arranged set of branches into one or more groups, determining a data structure for each subcircuit in a group that supports a combination of selectively flattened and selectively expanded group of subcircuits, selecting a subcircuit as a simulation leader and identifying remaining subcircuits as followers in the group, where the simulation leader have states substantially equivalent to the followers, simulating the respective simulation leader of each group using a selectable simulation driver, and replicating simulation results of the respective simulation leader of each group to its followers.Type: GrantFiled: February 15, 2005Date of Patent: August 14, 2007Assignee: Cadence Design Systems, Inc.Inventor: Bruce W. McGaughy
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Patent number: 7254790Abstract: A moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each free and the corresponding links can be determined independently. By combining the conventional moment computation algorithms and the reduced ordered binary decision diagram (ROBDD), the proposed method can compute system moments efficiently. Experimental results demonstrate that the proposed method can indeed obtain accurate moments and is more efficient than the conventional approach.Type: GrantFiled: July 13, 2004Date of Patent: August 7, 2007Assignee: Chang Gung UniversityInventors: Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng, Ming-Hong Lai
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Patent number: 7254764Abstract: Selected test pattern sequences to be used in transient power supply current testing to detect path delay faults in an IC are easily and rapidly generated. A stored fault list of path delay faults is prepared. A train of transition signal values is calculated by simulation of transitions occurring in the IC when a test pattern sequence is applied to the IC, and respective path delay fault in the stored fault list is determined whether it is a detectable fault that is capable of being detected by the transient power supply current testing by using the transition signal values. Those detectable faults that exist in the stored fault list are deleted from the stored fault list and those test pattern sequences that are used to detect the detectable faults existing in the stored fault list are registered in a test pattern sequence list as the selected test pattern sequence.Type: GrantFiled: September 28, 2005Date of Patent: August 7, 2007Assignee: Advantest CorporationInventors: Masahiro Ishida, Takahiro Yamaguchi
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Patent number: 7246051Abstract: An improved method for extrapolating worst-case Simulation Program with Integrated Circuit Emphasis (SPICE) model parameters for an integrated circuit including manufacturing semiconductor devices, measuring typical data and worst-case data with respect to various electrical characteristics of the manufactured devices, determining a set of typical SPICE model parameters using the typical data, and determining a set of worst-case SPICE model parameters using the typical data and the worst-case data. Determining the set of worst-case SPICE model parameters preferably includes extrapolating statistical model parameters using the typical data and the worst-case data and determining the set of worst-case SPICE model parameters using the statistical model parameters.Type: GrantFiled: March 22, 2002Date of Patent: July 17, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Gi-young Yang, Sang-hun Lee
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Patent number: 7246333Abstract: In one embodiment of the invention, a method for unified debug for simulation, includes: generating a transaction from a hardware verification language (HVL) testbench; copying signal states in the HVL testbench after the transaction is generated, wherein the signal states are copied in a hardware description language (HDL) mirror; generating a response to the transaction from a device-under-test (DUT); and displaying the signal states in the HVL testbench on a display screen as a first waveform, and displaying the DUT response on the display screen as a second waveform. In another embodiment of the invention, an apparatus is provided for unified debug for simulation, where the apparatus can perform the above method.Type: GrantFiled: October 11, 2005Date of Patent: July 17, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventor: Dustin Bingham
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Patent number: 7243059Abstract: Methods, articles of manufacture, and systems for software simulation of hardware, for use in testing firmware, are provided. The software simulation may be accomplished through the creation and use of a set of intelligent buffer objects (hereinafter “smart buffers”) corresponding to registers (e.g., status, control, and results registers) in actual hardware targeted by the firmware. When accessed, the smart buffers may call specialized functions (or behavior actions) designed to simulate (expected or unexpected) behavior of the targeted hardware by modifying smart buffers associated with the same or other hardware registers. The simulated behavior of the hardware may allow the firmware code to be properly exercised as if running on an actual product platform.Type: GrantFiled: April 24, 2003Date of Patent: July 10, 2007Assignee: International Business Machines CorporationInventor: Daniel M. Crowell
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Patent number: 7239993Abstract: A method, data processing system, and program product for building an instrumented simulation model of a digital design are disclosed. According to the method, a model build tool locates, within design data collectively defining a simulation model of the digital design, a definition of a configuration construct specifying a relationship between values of one or more configuration latches within the digital design and settings of the configuration construct. In response to locating the definition of the configuration construct, the model build tool automatically creates an instrumentation entity within the design data. The instrumentation entity has one or more inputs logically coupled to the one or more configuration latches and one or more outputs for providing signals indicating characteristics of the configuration construct during simulation.Type: GrantFiled: August 28, 2003Date of Patent: July 3, 2007Assignee: International Business Machines CorporationInventors: Wolfgang Roesner, Derek Edward Williams
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Patent number: 7239997Abstract: A statistical delay simulation apparatus includes: a circuit simulator for simulating a circuit operation of a circuit cell constituting an LSI; a statistical delay library generator for driving the circuit simulator and generating, based on a process parameter and the like, a statistical delay library in which the dependency of a delay variation on a predetermined operation condition in each circuit cell is described; a delay calculator for calculating a delay amount of each circuit cell to generate a statistical LSI delay information file containing data on the calculated delay amount; and a static timing analyzer for simulating, based on data of the statistical LSI delay information file, an operation with a delay variation of the LSI to generate a statistical LSI delay analysis result file.Type: GrantFiled: January 14, 2004Date of Patent: July 3, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Hirokazu Yonezawa
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Patent number: 7240303Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.Type: GrantFiled: June 6, 2003Date of Patent: July 3, 2007Assignee: Synplicity, Inc.Inventors: Nils Endric Schubert, Kenneth S. McElvain, John Mark Beardslee, Mario Larouche
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Patent number: 7239994Abstract: A system and method for simulating network connection characteristics by alteration of a network packet. In general, the method of the invention includes providing a driver that is capable of accessing all outgoing and incoming network packets and altering a network packet to simulate a connection characteristic of the network. In particular, the method of the invention includes receiving a network packet, assigning a new, simulated network address to the network packet and performing modification of the network packet to simulate certain network connection characteristics (including, for example, transmission delay, limited bandwidth, packet dropping, packet fragmentation, packet duplication and packet reordering). The system of the invention includes a modification module for altering certain characteristics of a packet.Type: GrantFiled: November 15, 2004Date of Patent: July 3, 2007Assignee: Microsoft CorporationInventor: Kestutis Patiejunas
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Publication number: 20070150249Abstract: A verification operation supporting system which can automatically execute complicated verification operation is provided. This system is provided with an input device for an administrator for inputting test case common information common to all test cases and test case difference information different for every test case, a text editor for generating a template file containing basic information and, an input device for a verification person for inputting verification person individual information and test condition individual information, a parameter file automatic generating program for generating test case information file which describes the verification operation of each test case by adding individual information and to the basic information and in the template file, and a verification operation executing program for executing the verification operation in accordance with the test case information file while running a TOS and an HDL simulator.Type: ApplicationFiled: December 11, 2006Publication date: June 28, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Noriaki Asamoto
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Patent number: 7236917Abstract: A system for tracing a simulation design involves an encoded assertion asserting a value of a node of the simulation design at a point in a simulation, a fanin cone detection facility configured to obtain a fanin cone for the encoded assertion, a waveform trace facility configured to obtain waveform data including a history of signal values for the node, and a simulation toolkit configured to obtain node data using the fanin cone and the waveform data.Type: GrantFiled: October 31, 2003Date of Patent: June 26, 2007Assignee: Sun Microsystems, Inc.Inventors: Nasser Nouri, William K. Lam
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Patent number: 7236918Abstract: In a method of compiling a simulation model of a digital design, a compiler receives an indication of a desired set of instrumentation entities to be included within a simulation model of a digital design described by a plurality of hierarchically arranged design entities. The instrumentation entities monitor logical operation of one or more of the plurality of design entities during simulation for occurrence of events of interest. In response to the indication, the compiler determines by reference to a bill-of-materials of a previously compiled file whether or not the previously compiled file was compiled with instrumentation entities compatible with the desired set of instrumentation entities. In response to determining that the previously compiled file was compiled with compatible instrumentation entities, the compiler compiles the simulation model of the digital design utilizing the previously compiled file in accordance with the indication.Type: GrantFiled: December 31, 2003Date of Patent: June 26, 2007Assignee: International Business Machines CorporationInventors: Wolfgang Roesner, Derek Edward Williams
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Patent number: 7233889Abstract: A method of evaluating noise immunity of a semiconductor device is provided. An actual circuit including the semiconductor device is represented by an equivalent circuit which has a target equivalent circuit, a noise source equivalent circuit, and an external equivalent circuit connected in parallel. The target equivalent circuit represents the semiconductor device. The noise source equivalent circuit represents a noise source outside the semiconductor device, and supplies noise to the target equivalent circuit. The external equivalent circuit represents a circuit outside the semiconductor device. The noise immunity is evaluated based on a voltage or current which arises in the target equivalent circuit by the noise. In this way, the immunity of the semiconductor device against extraneous noise can be evaluated in consideration of the effects of the circuitry outside the semiconductor device.Type: GrantFiled: October 23, 2002Date of Patent: June 19, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Eiji Takahashi, Yoshiyuki Saito, Yukihiro Fukumoto, Hiroshi Benno
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Patent number: 7231336Abstract: In accordance with the present invention there is provided a method for performing a glitch check in simulating a circuit. Current maximum and minimum values for optimization parameters of the circuit are determined. Next, a signal pulse characteristic for the circuit simulation is determined based on the maximum and minimum optimization parameters. A current averaged optimization parameter is determined from the current maximum and minimum optimization parameters. A prime criterion parameter is calculated based on the optimization parameters and the signal pulse characteristic value. If the prime criterion parameter converges into a specified range then measurement results from the circuit simulation are parsed and reported as final. If the prime criterion parameter does not converge, then the process continues by recalculating the optimization parameters until the prime criterion parameter converges.Type: GrantFiled: December 5, 2003Date of Patent: June 12, 2007Assignee: Legend Design Technology, Inc.Inventors: You-Pang Wei, Yuhung Liao, Mingchi Liu, YuJiao Ping
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Patent number: 7231335Abstract: A method for performing input/output (I/O) floor planning on an integrated circuit design is disclosed. User design data related to I/O circuit associated with each package pin is initially collected. The collected user design data is then sorted according to operating conditions. Next, an I/O behavioral model and a package model are chosen based on the sorted data. A simulation deck is dynamically built with appropriate operating conditions. Finally, a simulation is performed through a circuit simulator using the chosen I/O behavioral model and the operating conditions.Type: GrantFiled: June 26, 2003Date of Patent: June 12, 2007Assignee: International Business Machines CorporationInventors: Jerry D. Hayes, Amol Anil Joshi, Natesan Venkateswaran, William John Wright
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Patent number: 7231338Abstract: A distributed simulation system is provided in which timesteps may be divided into a first phase (referred to as the zero time phase herein) and a second phase (referred to as the real time phase herein). In the first phase, each distributed simulation node in the system may process one or more received commands without causing the simulator to evaluate the model in that distributed simulation node. In the second phase, each distributed simulation node may cause the simulator to evaluate the model in response to a command supplying one or more signal values to the model. In one embodiment, the second phase may iterate the evaluation of the model for each command received which supplies signal values. Each iteration may optionally include transmitting a command including the output signal values produced by the model during that iteration.Type: GrantFiled: November 9, 2001Date of Patent: June 12, 2007Assignee: Sun Microsystems, Inc.Inventors: Carl Cavanagh, Steven A. Sivier, Carl B. Frankel, James P. Freyensee