Abstract: A method and apparatus used for designing printed circuit boards to meet current leakage requirement by determining an approximate model of electric fields based on a structure between two conductors on an outer surface of a printed circuit board; deriving an effective permittivity of the model of the electric fields; calculating a plurality of electric fields using the derived effective permittivity by varying a distance between the two conductors, a thickness of the printed circuit board, and an applied voltage between the two conductors; plotting a graph of the calculated plurality of electric fields; and selecting by using the graph a configuration of the two conductors so as to meet the current leakage requirement. A printed circuit board has a set of conductors on the outer surfaces of the printed circuit board; another set of conductors interior to the printed circuit board; and a solder mask that covers only the set of conductors on the outer surfaces of the printed circuit board.

Abstract: An aspect of the present invention provides a semiconductor integrated circuit verification system that includes a compiler configured to receive circuit descriptions of a semiconductor integrated circuit to be verified and create a circuit database, a circuit analysis unit configured to receive the circuit database to analyze the circuitry inside the semiconductor integrated circuit based on the circuit database, the circuit analysis unit configured to determine the timing at which the abstraction level of the circuit is switched and generate a simulation object, and a simulation execution unit configured to receive the simulation object and conduct a simulation of the semiconductor integrated circuit based on the simulation object.

Abstract: The invention relates to a method for eliminating routing congestion in an integrated circuit (IC) layout defined by a placement plan indicating a position within the layout of each cell forming the IC and routing plan describing routes followed by nets interconnecting the cells. Routing congestion is eliminated by estimating routing congestion in various areas of the layout and relocating each cell to least routing congested areas of the layout for which cell relocation results in a reduction in the total lengths of the nets connected to the cell that exceeds a predetermined minimum reduction.

Abstract: Methods and apparatus are provided for efficiently generating test components for testing and evaluating a design under test. As a design is being configured, generated test components are made available. In one example, test components are automatically generated and included in a simulation testbench based on selected components in the design. Generally, the test components complement the selected components in the design. Moreover, the test components can be automatically seeded with initial contents.

Abstract: In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.

Abstract: A system of finite state machines built with asynchronous or synchronous logic for controlling the flow of data through computational logic circuits programmed to accomplish a task specified by a user, having one finite state machine associated with each computational logic circuit, having each finite state machine accept data from either one or more predecessor finite state machines or from one or more sources outside the system and furnish data to one or more successor finite state machines or a recipient outside the system, excluding from consideration in determining a clock period for the system logic paths performing the task specified by the user, and providing a means for ensuring that each finite state machine allows sufficient time to elapse for the computational logic circuit associated with that finite state to perform its task.

Abstract: The present invention provides a system and method for multi-path simulation that employs a shielded anechoic chamber to avoid external electromagnetic interference and other uncontrollable transmission paths generated in testing, and divides and adjusts a signal into multiple simulation signals to simulate the attenuations and delays generated in multi-path transmission of the signals. The shielded anechoic chamber includes a turntable, controlled by a control unit, for carrying a wireless communication device to be tested and for changing the reception azimuth of the device, thereby measuring the electric wave transceiving of the device.

Abstract: A method for routing a message from a source node to a destination node, where the source node and the destination node are connected by a plurality of nodes in a cycle-based system, is disclosed. The method includes generating a maze data structure including the plurality of nodes, where each of the plurality of nodes is associated with a dimension corresponding to time, and routing the message from the source node to the destination node using the dimension corresponding to time.

Abstract: A test pattern sequence to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur is prepared. One of the faults is selected and an initialization test pattern v1 which establishes an initial value for activating the fault at the location of a fault is determined by an implication operation. A propagation test pattern v2 which causes a stuck-at fault to be propagated to a following gate is determined by another implication operation. A sequence formed by v1 and v2 is registered with a test pattern list and the described operations are repeated until there remains no unprocessed fault in the fault list.

Abstract: Selected test pattern sequences to be used in transient power supply current testing to detect path delay faults in an IC are easily and rapidly generated. A stored fault list of path delay faults is prepared. A train of transition signal values is calculated by simulation of transitions occurring in the IC when a test pattern sequence is applied to the IC, and respective path delay fault in the stored fault list is determined whether it is a detectable fault that is capable of being detected by the transient power supply current testing by using the transition signal values. Those detectable faults that exist in the stored fault list are deleted from the stored fault list and those test pattern sequences that are used to detect the detectable faults existing in the stored fault list are registered in a test pattern sequence list as the selected test pattern sequence.

Abstract: From the data of diffusion-length-dependent parameters extracted from the parameters of the transistor model of MOS transistors and from the parameters of transistors having various diffusion lengths, a diffusion-length-dependent parameter correcting unit creates approximate expressions of the diffusion length dependence of these parameters, and calculates parameter correction values to be used instead of original parameter values by using the created approximate expressions. Hence, the correction values can be used easily instead of the original parameter values, whereby a transistor model of MOS transistors having a different diffusion length DL can be created easily. Circuit simulation in consideration of the diffusion length dependence of the drain currents of MOS transistors can thus be carried out, whereby highly accurate simulation can be attained.

Abstract: An apparatus in one example comprises one or more control components that regulate one or more thermal test components to adjust one or more emulated operational characteristics for one or more electronic devices. The thermal test components are coupled with one or more rack-mount frames. The thermal test components create the emulated operational characteristics for the one or more electronic devices to generate one or more emulated environmental effects. The one or more control components obtain one or more measurements of one or more of the one or more emulated operational characteristics and the one or more emulated environmental effects. The one or more control components make a prediction of one or more of one or more actual operational characteristics and one or more actual environmental effects of the one or more electronic devices through employment of one or more of the one or more measurements.

Abstract: The present invention is directed to methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects by allowing design rules on degradation to be included in the netlist. Once the hot-carrier circuit simulation is launched, the rules are checked and the reliability design rule violations are reported. The process can be performed on either the layout or schematic window. The design rule criteria can be any device parameter and can be expressed in absolute or relative terms. The criteria can be based on device type, model card name, instance geometry, or temperature. Additionally, values can be set prior to beginning the simulation.

Abstract: A method, apparatus, system, and signal-bearing medium that in an embodiment select a simulator input fragment, characterize an I/O model using a set of simulator input fragments, create a set of behavioral models based on the characterization and compare the set of behavioral models to the I/O model. In an embodiment, the set of behavioral models is compared to the I/O model by creating simulator input decks that include net topology for the I/O model and the set of behavioral models, simulating the decks, and comparing the output from the simulating.

Abstract: Disclosed is a method of simulating semiconductor circuitry in which trace data received from a first simulation of the semiconductor circuitry, is processed and the values of inputs to the semiconductor circuitry read from the trace data are output to a second simulation of semiconductor circuitry. There is also disclosed a method of determining whether first and second simulations of semiconductor circuitry are equivalent in which transitions in the values of registers simulated by the first and second simulations are analysed, and an error is declared if, following a register in either simulation making a transition to a value which is not equivalent to the corresponding register in the other simulation. The value of the register in the same simulation makes a further transition to a non-equivalent value before the value of the register in the other simulation makes a transition to an equivalent value.

Abstract: A server apparatus and a transit control method allow a noise countermeasure to be determined efficiently and conveniently in designing electronic circuits. A registered noise countermeasure information storing unit stores noise countermeasure list information requested for registration by a registration terminal in the registration terminal connected via a network. A circuit information acquiring unit acquires circuit information from a user terminal connected via the network, which can use the registered noise countermeasure information. A noise countermeasure list information generating unit generates noise countermeasure list information based on the registered noise countermeasure information and the circuit information, and transmits the generated noise countermeasure list information to the user terminal.

Abstract: A method for prototyping an integrated circuit may include selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide functionality corresponding to a specific integrated circuit device. The at least one daughter card is connected to the motherboard so that the daughter card is communicatively connected to common memory provided on the motherboard. The motherboard is connected to an information handling system utilizing a prototyping interface device, the information handling system providing a virtual software modeling environment for an integrated circuit. The at least one daughter card, information handling system, prototyping interface device and motherboard emulate an integrated circuit design. At least one of software and system integration of the integrated circuit emulated by the motherboard, information handling system, prototyping interface device and the at least one daughter card is tested.

Abstract: A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for directing initial inputs and intermediate result values.

Abstract: A host-terminal emulation program which permits secure host linkage communication between a host within a protected network and a client outside the network. The client establishes in advance a receiving connection with a relay device, for receiving data compliant to a second protocol (Step S1). Subsequently, the client establishes a transmitting connection with the relay device, for transmitting data compliant to the second protocol (Step S2), and transmits data to the relay device via the transmitting connection (Step S3). The relay device converts the data to a first protocol (Step S4), and transmits the converted data to the host (Step S5). On completion of data processing by the host (Step S6), the processing result is transmitted to the relay device by means of the first protocol (Step S7). The processing result is converted to the second protocol in the relay device (Step S8) and transferred to the client (Step S9).

Abstract: A computer program product and method of simulation involve the present computer simulation model of a lossy transmission line. The model uses a hybrid model at each end of the transmission line, each hybrid model coupled to a port of the transmission line. Each hybrid model is coupled to a forward path model and a reverse path model, such that simulated signals pass through the forward path mode enroute from a first hybrid to the second hybrid, and through the reverse path model enroute from the second hybrid to the first hybrid. At each end of the transmission line there is also a reflection model coupling between the reverse path model and the forward path model.

Abstract: An improved system and method are disclosed for indicating the validity of airport runway visual approach slope indicators on an aircraft display. An aircraft display system is provided, which includes a database for storing data about the specific visual approach slope lighting indicator system being used by each airport of a plurality of airports and any special distance and/or usage limitations associated with each such visual approach slope indicator system, a processing unit, a position determination unit, and a visual display. As an aircraft approaches an airport, the processing unit receives the aircraft's current position from the position determination unit, and compares the aircraft's current position data with the distance and/or usage limitation data stored in the database for the approach slope indicator system being used by that airport.

Abstract: The present invention describes a VHDL preprocessor. Configurable and flexible VHDL sources comprise statements that are replaceable by specific values dependent on design requirements.

Abstract: A method is provided for selecting a frequency-based ramptime limit for a technology. The method includes creating a logic chain with cells from the technology and applying a sequence of signals to the logic chain. Each signal has a different ramptime relative to a clock period. At least one signal quality characteristic is measured along the logic chain for each of the signals. The frequency-based ramptime limit is selected based on a comparison of the measured signal quality characteristics measured to at least one predefined signal quality value.

Abstract: Simulation of electromagnetic characteristics of an electrical circuit uses netlist data defining component instances, including layout component instances, and their topological interconnection in an electrical circuit. A circuit simulation is performed using the netlist data, involving use of a model for each layout component instance. An attempt is made to retrieve an existing simulation model of the layout component instance from a database of such layout component simulation models. If no suitable simulation model can be found in the database, an attempt is made to interpolate a new simulation model from among existing simulation models in the database. If interpolation is determined not to be feasible, then an electromagnetic simulation of the layout component instance is performed to develop a new electromagnetic simulation model. This new model is used in the circuit simulation, and added to the database for future use.

Abstract: A method and system for instrumenting testcase execution processing of a hardware description language (HDL) model using a simulation control program. In accordance with the method of the present invention, a set name application program interface (API) entry point is called wherein the set name API entry point includes program instructions for naming a simulation control program in association with testcase execution of the HDL model. A create event API entry point is called, wherein the create event API entry point includes an event identifier input parameter which identifies a testcase execution event with respect to the named simulation control program. In response to executing a testcase simulation cycle, signal values are retrieved from the HDL model into an instrumentation code block, wherein the instrumentation code block includes program instructions for processing the retrieved signals to detect whether the testcase execution event has occurred during the testcase simulation cycle.

Abstract: Disclosed herein is a method of storing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, result data obtained by simulation of at least one HDL model are received. In association with the result data, a plurality of value sets is received, where each value set includes at least one keyword having an associated value. Each keyword identifies a parameter external to the HDL model that affected the result data. The data results are stored within a data storage subsystem in association with the plurality of value sets such that particular result data are attributable to particular ones of the plurality of value sets. In one embodiment, a keyword table is built in the data storage system that indicates which data subdirectories store result data associated with particular value sets. The result data can then be queried based upon selected keywords of interest, for example, by reference to the keyword table.

Abstract: Briefly, a system and a method of formal verification and failure analysis and rectification of models or designs, e.g., VLSI designs, of processors, circuits and logical systems. Embodiments of the system may include a multi-value annotation scheme for annotating different types of values of signals, and a post-annotation scheme for further analysis based on the annotated values. Some embodiments of the invention may optionally include a generator of counter-examples of a given length.

Abstract: Methods and apparatus for substrate modeling are disclosed. In one disclosed method, for example, the substrate modeling comprises determining scalable Z parameters associated with at least two substrate contacts, constructing a matrix of the scalable Z parameters for the at least two substrate contacts, and calculating an inverse of the matrix to determine resistance values associated with the at least two substrate contacts. Computer-readable media containing computer-executable instructions for causing a computer system to perform any of the described methods are also disclosed.

Abstract: Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.

Abstract: There is disclosed an IC simulation system operable to (i) store a plurality of HDL modules, each of which is representative of a circuit element, (ii) receive a HDL description of a desired circuit, and (iii) synthesize a circuit netlist as a function of the received HDL circuit description and ones of the plurality of HDL modules, the circuit netlist is responsible for defining behavioral relationships among associated ones of the HDL modules, and associate a timing-violation controller with the circuit netlist to ignore selected timing violations sensed as a function of various ones of the behavioral relationships during simulation of the desired circuit.

Abstract: A utility for enhancing the interface of a electronic circuit simulator provides for selecting signals for monitoring, selecting groups of components for variation of tolerances and inserting faults to an underlying model of the circuit.

Abstract: A system and method is provided for simulating computer network devices. The method executes a user interface which presents a scenario which includes tasks a user is to perform by interacting with one or more simulated network devices. A network diagram having icons displays a network topology. By selecting an icon a simulated network device is executed and a communication interface to the simulated network device is opened. Commands to the simulated network device issued through the communication interface are interpreted and responded to in substantially the same manner as a corresponding actual network device. In addition, for each simulated network router a routing table is generated and maintained to allow the simulated network devices to respond to commands as realistically as possible. Tasks completed by a user are monitored and evaluated to determine whether the user successfully completed the required tasks.

Abstract: A method for identifying predictable data sharing locations includes generating a testcase thread of code, creating a list of data lines used by the generated testcase thread of code, and generating a list of predictable data sharing locations based on the data line list.

Abstract: The invention relates generally to a method of power supply noise and signal integrity analysis for creating frequency-dependent electrical models particularly related to microelectronic packages. The method discloses creation of equivalent circuits for geometries encountered in a typical chip package, including how to partition the geometry into cells which are less then 1/20 the minimum wavelength (?) in size, and how to handle signal and power supply vias, signal wires, and power planes. The method also instructs how to assign values to each of the inductors, capacitors, resistors, and transmission lines in each equivalent circuit. The method further provides modeling of only those interactions which occur between adjacent cells.

Abstract: The present invention describes a method including: determining field-clustering scheme; selecting initial sample plan; establishing initial model of overlay, the initial model of overlay comprising components; and establishing efficient model of overlay from the initial model of overlay including: constructing matrices; identifying redundant components and eliminating the redundant components; and identifying highly-correlated components and determining whether to eliminate the highly-correlated components.

Abstract: A memory compiler characterization system and method for determining parametric data, wherein memory compilers of a first type are rigorously characterized and memory compilers of a second type are sparsely characterized with respect to a particular parameter. Absolute scale factors are determined based on the ratio of the parametric data points of two congruent memory compilers, one from each type. Interpolated scale factors are obtained based on the absolute scale factors. Parametric data for the remaining compilers of the sparsely characterized compiler set is filled out by applying the interpolated scale factors in conjunction with the data of the congruent memory compilers of the first type.

Abstract: A method (900) of modeling transactions and performing inertial rejection can include representing a plurality of scalar signals as one or more transaction objects, wherein each transaction object comprises a start index, an end index, values for each constituent scalar signal which correspond to an index within a range specified by the start index and end index inclusive, and a time at which the values are transacted. (400) The method further can include constructing and adding a new transaction object for the plurality of scalar signals (920) and comparing the new transaction object with at least one existing transaction object (925) wherein the at least one existing transaction object occurs earlier in time than the new transaction object and is within a rejection window. At least one of a start index and an end index of the at least one existing transaction object can be manipulated (975).

Abstract: A system for analyzing a circuit includes a computer. The computer operates on a model of the circuit. The model has an input, an output, and multiple controlled sources. The computer is configured to supply a stimulus to the input of the model of the circuit. The input stimulus has an associated value. Each of the multiple controlled sources has a current value derived from the input value. The computer is also configured to supply a stimulus to the output of the model. The output stimulus has an associated value. The computer is further configured to sweep the values for the input and output stimuli through a two sets of swept values, and to obtain an output current of the model of the circuit as a function of the swept values.

Abstract: A predictor allows the computation of the greatest lower bound of the noise figure pertaining uniformly over the operating band of a wideband amplifier. This computation is done directly from noise-parameter data of the amplifier.

Abstract: An improved hardware circuit simulation method in particular for history-dependent and cyclic operation-sensitive hardware circuits, like SOI-type hardware, checks for correct cyclic boundary conditions by performing a first run of a DC simulation with input voltage conditions belonging to CYCLE START, and by carrying out a second DC simulation with input voltage conditions belonging to CYCLE STOP. After comparing the results, e.g., comparing the node voltages, any mismatches can be determined which serve as a hint to non-compatibility with cyclic operation. Thus, the design is able to be re-designed before being simulated in vain with a great amount of work and computing time. A transient simulation can be appended for automated correction of dynamic errors.

Abstract: A simulation control program receives a hardware description language (HDL) model including design entities and count event registers. Each count event registers is associated with a respective instance of an event. The count event registers include first and second registers for counting occurrences of a same replicated event generated within different instances of a same design entity having a same hierarchical level within the HDL model. The simulation control program also receives a correlation data structure indicating which count event registers are associated with instances of the same replicated event. During simulation processing, each of the count event registers maintains a respective count value representing a number of times an associated event instance occurs. The simulation control program sums count values of the first and second count event registers in accordance with the correlation data structure and outputs a count event data packet containing the aggregate count value.

Abstract: A method and system for short-circuit current modeling in CMOS circuit provides improved accuracy for logic gate power dissipation models in computer-based verification and design tools. The model determines the short circuit current for each complementary pair within a CMOS circuit. Input and output voltage waveforms provided from results of a timing analysis are used to model the behavior one device of the complementary pair. The device is selected as the limiting device (the device transitioning to an “off state) from the direction of the logic transition being modeled, which is also the device that is not charging or discharging the output load. Therefore, the current through the selected device can be determined from the input and output waveforms and is equal to the short-circuit current prior to the saturation of the selected device.

Abstract: An integrated circuit design apparatus includes a block placement processing unit which performs processing of creation of a lower-rank mounting block in a higher-rank mounting block, and performs processing of creation of virtual placement regions in each of the lower-rank mounting block and the higher-rank mounting block. A functional block assignment processing unit performs processing of assignment of functional blocks to each of the virtual placement regions provided by the block placement processing unit. An evaluation processing unit provides a display of a condition of the functional blocks assigned to each of the virtual placement regions of both the lower-rank mounting block and the higher-rank mounting block, in order to evaluate the condition of the assigned functional blocks.

Abstract: Test benches, simulations, and scripts are invoked in parallel for testing multiple points in a circuit being synthesized in an Analog Mixed Signal environment. A simulation system for simultaneously optimizing performance characteristics in circuit synthesis uses a set of design parameters. At least one circuit model is used to incorporate the set of design parameters, each circuit model adapted to model a portion of the circuit pertaining to a performance characteristic. At least one analysis test bench is then connected to each circuit model. Each analysis test bench is adapted to model circuitry external to the circuit and control the type of analysis to be performed for each performance characteristic of the circuit.

Abstract: At least one predominant color in a digital image is identified by applying a detection rule to randomly-selected pixels in the image. The detection rule includes testing specific colors to reduce the probability of at least one of a false-positive outcome and a false-negative outcome.

Abstract: Dynamic cosimulation is implemented using a cosimulation bridge for data exchange between a primary simulator and a secondary simulator, and a plurality of user selected optimization control signals defined over the cosimulation bridge. At least one user selected optimization control signal is identified for disabling the cosimulation bridge. The primary simulator and secondary simulator are dynamically disengaged for ending data exchange responsive to disabling the cosimulation bridge. Responsive to optimization control signal going inactive, the primary simulator and secondary simulator are dynamically re-engaged for data exchange. The optimization control signals include a single sided disable; a two independent disable; a functional OR disable; a functional AND disable, and suspend signals. The single sided disable and the two independent disable enable disabling one side of the cosimulation bridge and not the other side.

Abstract: A method and apparatus for emulating a high-precision, high-accuracy clock. In one embodiment, two clocks are used in the emulation. The first clock has precision greater than precision of the second clock and accuracy less than accuracy of the second clock. A checkpoint time relative to elapsed cycles of the second clock and a checkpoint cycle count of cycles of the first clock are periodically stored relative to a checkpoint period that lasts for a selected number of cycles of the second clock. A reference cycle rate of the first clock is calculated relative to the cycle rate of the second clock. The current time is determined as a function of the checkpoint time, a number of cycles of the first clock elapsed since storing the most recent checkpoint cycle count, and the reference cycle rate of the first clock.

Abstract: Various methods, apparatuses and systems in which a memory uses a noise reduction circuit to sense groups of memory cells. The memory has a plurality of memory cells organized into groups of memory cells. The noise reduction circuit performs a sense operation on a first group of memory cells at the substantially the same time. The noise reduction circuit performs a sense operation on a second group of memory cells at substantially the same time. The noise reduction circuit has timing circuitry to sense the second group of memory cells after the sense of the first group initiates but prior to the completion of the sense operation on the first group of memory cells.

Abstract: An apparatus in one example comprises one or more control components that emulate one or more operational characteristics of one or more electronic devices through employment of one or more thermal components coupled with a frame.

Abstract: Method and apparatus for interfacing a high-level modeling system (HLMS) with a reconfigurable hardware platform for co-simulation. In one embodiment a boundary-scan interface is coupled to the HLMS and is configured to translate HLMS-issued commands to signals generally compliant with a boundary-scan protocol, and translate signals generally compliant with a boundary-scan protocol to data compatible with the HLMS. A translator and a wrapper are implemented for configuration of the hardware platform. The translator translates between signals that generally compliant with the boundary-scan protocol and signals that are compliant with a second protocol. A component to be co-simulated is instantiated within the wrapper, and the wrapper transfers signals between the translator and the component.