Abstract: The operating characteristic of a transistor, modeled by a resistive element having fixed resistance and a power source voltage that varies with time, is segmented into a linearity region in which a current increases as a gate potential varies and a saturation region in which the current gradually decreases as the gate potential remains at a constant level, so that gradual decrease in current in a saturation region of the transistor is properly reflected and a delay time is estimated in a precise manner.

Abstract: For deriving an RTL description through several steps from a behavioral description, a behavioral synthesis device outputs an associated relation between intermediate level descriptions subsequent to the respective steps and intermediate level descriptions prior to the respective steps. A model extracting device extracts a model capable of expressing a control structure based on a finite state machine and an update of a signal from the behavioral description, each of the intermediate level descriptions, and the RTL description, as a model corresponding to those descriptions. A signal value function extracting device extracts signal value functions from the model. A function equivalence comparing device checks the equivalence between signal value functions prior and subsequent to the steps of the behavioral synthesis device.

Abstract: There is provided a set of methods with the exact accuracy to effectively calculate the n-th order state space models of RC distributed interconnect and transmission line in closed forms in time domain and transfer functions by recursive algorithms in frequency domain, where their RC components can be evenly distributed or variously valued. The main features include simplicity and accuracy of the said closed forms of the state space models {A,B,C,D} without involving matrix inverse and matrix multiplication operations, effectiveness and accuracy of the said recursive algorithms of the transfer functions, dramatic reduction of the calculation complexity to O(n) for the state space models, simulation methodology, and practice of various model reductions and their optimization. For evenly distributed RC interconnect and transmission line, the said closed form of state space model has its computation complexity of only a fixed constant, i.e., O(1).

Abstract: Integrated proof flow methods and apparatuses are discussed. Integrated proof flow refers to attempting both formal verification and nonformal verification. A coverage metric can be changed by both attempting formal verification and by attempting nonformal verification. Some embodiments of the present invention provide proof flow methods that integrate verification and nonformal verification (e.g., bounded verification, multi-point proof, and/or vector-based simulation) to prove one or more properties in a circuit design.

Abstract: A system and method for creating a graphical program including a plurality of portions to be executed sequentially. User input may be received, e.g., during development of the graphical program, wherein the user input indicates a desire to specify a plurality of portions of graphical source code to be executed sequentially. In response, a plurality of frames may be displayed in the graphical program, such that two or more frames from the plurality of frames are visible at the same time. A portion of graphical source code may be included in each frame in response to user input. The plurality of frames may define an execution order for the corresponding portions of graphical source code, such that during execution of the graphical program, the portions of graphical source code are executed sequentially according to this execution order. In the preferred embodiment, all of the frames are visible at the same time, thus giving the program developer a complete view of the graphical program.

Abstract: In the circuit operation verifying method, initialization includes inputting circuit diagram data (a net list), specification information on respective circuit elements, and input data representing waveforms with time of voltages or currents used for operation simulation, and storing the circuit diagram data to memory. Operation of a semiconductor circuit to be verified is simulated using the circuit diagram data and the input data, and momentary voltage/current values at input terminals and the like of the circuit elements are stored in the memory. During the operation simulation, whether or not the circuit elements satisfy their voltage/current specifications and time specifications are concurrently verified based on the voltage/current values stored in the memory.

Abstract: A method of evaluating the exposure property of data to a wafer in which errors in the production of a photomask and the formation of patterns caused by defocus in the transfer of data to the wafer are considered. Accordingly, errors in the production of the photomask and deformation of patterns caused by defocus can be evaluated in the stage of design data.

Abstract: A method for designing an electronic system having at least one digital part. The method includes representing a behavioral description of the system as a first set of objects with a first set of relations therebetween. Furthermore, the method includes refining said behavioral description into an implementable description of said system, said implementable description being represented as a second set of objects with a second set of relations therebetween. Also, the method includes retaining at least one of said second objects for reuse in the design of a second electronic system.

Abstract: In an integrated circuit, test signals are routed from test points through a hierarchy of distributed multiplexers to output pads. The multiplexers are distributed locally to various regions that are arranged in a hierarchy of regional levels. Thus, each test signal is routed to the locally distributed multiplexer, and only a portion of the test signals reach the top-level multiplexer.

Abstract: A simulation template and method therefor is disclosed that modifies a SPICE netlist that describes a circuit in order to provide customized or pre-installed additional analysis. More specifically, a simulation template is an interactive command language (ICL) script that has embedded instructions telling a netlist where to insert information and which options are to be provided. It is used to expand SPICE beyond the traditional limitations of the basic alternating current (AC), direct current (DC), and transient analysis by allowing parameter variations and multiple simulations passes to be run under one analysis umbrella. Such additional analysis employing parameter variations and multiple analysis passes include sensitivity analysis, root means square (RSS) analysis, extreme value analysis (EVA) and worst case sensitivity (WCS), to name a few.

Abstract: An advanced electronic signal conditioning circuit and associated housing elements. In one embodiment, the circuit comprises a plurality of coupled inductors and capacitors arranged in a signal filtering configuration which achieves enhanced voice- and DSL-band performance through the use of complex-impedance modeling during the circuit design phase. Free-standing and fixed device housings are also disclosed. Methods for manufacturing the aforementioned components are also described.

Abstract: A method and circuit arrangement for determining performance of a digital circuit to a critical degree by the transit time of signals of the longest signal path, also called the critical path. Since the signal transit time is influenced by the operating voltage, by regulating the operating voltage, to compensate for the effects caused by temperature and process fluctuations on the signal transit time in the digital circuit. In particular, the operating voltage can be regulated as a function of the signal transit time in such a way that a required minimum operating frequency can always be achieved. To determine signal transit time, the digital circuit has associated with it a number of replicas of the critical path in the digital circuit upon which the signal transit time is determined. In order to determine the transit time, the signal path replicas are exposed to the same operating conditions as the digital circuit.

Abstract: A method of a modeling metallization parasitics with the use of a simulation program. In one embodiment, a method of simulating interconnect lines in an electronic design automation simulation is disclosed. The method comprises partitioning the interconnect lines into groups of interconnect lines. Each group of interconnect lines does not have interactions with any of the other groups of interconnect lines. Moreover, at least one of the groups of interconnect lines contains at least three interconnect lines. The interconnect lines in each group are modeled. The modeling includes at least one of modeling mutual inductances and modeling of mutual capacitances.

Abstract: A method, system and program product for creating a simplified equivalent model for an IC that can be used for detailed analysis. The equivalent model takes into consideration the effects of all the I/O placement regardless of the non-uniformity of I/O placement. The equivalent model is generated, in part, by partitioning the IC into simulation windows and converting I/Os within each simulation window to a current source having the same current change rate, and then running a simulation on this intermediate model. A current change rate observed for a simulation window is then used to convert back to actual I/Os to create the equivalent model. The equivalent model can be simulated using conventional software, e.g., SPICE, for more detailed analysis such as signal integrity, timing of I/Os and noise.

Abstract: A method, apparatus and system for building a filter is disclosed. In a particular embodiment, the filter is a finite impulse response (FIR) filter and a compiler suitable for implementing the FIR filter is described. The compiler has a filter coefficient generator suitably arranged to provide a first set of filter coefficients corresponding to the desired FIR filter spectral response and a filter spectral response analyzer coupled to the filter coefficient generator for providing expected FIR filter spectral response based in part upon the first set of filter coefficients. The compiler also includes a filter resource estimator coupled to the filter spectral response simulator for estimating an implementation cost of the FIR filter based upon the second set of filter coefficients as well as a filter compiler unit coupled to the resource estimator arranged to compile a FIR filter implementation output file.

Abstract: A tool for automatically generating a reduced size circuit model including inductive interaction properties is provided. Such inclusion of inductive properties in the reduced size circuit model allows for a more complete and accurate circuit model than those created by conventional methods. Further, a technique for automatically generating a reduced size circuit model including inductive properties that uses less memory space and operates faster than conventional methods is provided.

Abstract: A wiring harness design is analyzed and module data is created automatically and stored for a plurality of harness modules representing wire and component element requirements for those modules, the modules being capable of assembly in selected combinations to create a complete harness.

Abstract: Techniques for estimating a body voltage of one or more transistors which form digital partially depleted silicon-on-insulator circuit, and for using estimated voltages to analyze electrical properties of the circuit, are disclosed. In one technique, device models are obtained and abstracted to generate simplified electrical descriptions of the transistors. The circuit topology is checked to generate sets of accessible states for the transistors that are indicative of whether a connection between a source or a drain of a transistor and either a power supply or ground exists. Next, sets of reference state body voltage minima and reference state body voltage maxima are determined for each of the transistors based on corresponding simplified electrical descriptions and corresponding sets of accessible states.

Abstract: A system for using machine learning based upon Bayesian inference using a hybrid Monte Carlo method to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Then, for each of the smaller simpler extraction problems, complex mathematical models are created using machine learning techniques.

Abstract: A method and apparatus are provided for implementing multiple configurations of multiple input/output (IO) subsystems in a single simulation model. At least one bus routing switch is included in the single simulation model. Each bus routing switch includes a plurality of ports respectively connected to a plurality of IO busses. Predefined ones of the plurality of IO busses are connected to respective multiple input/output (IO) subsystems in the single simulation model. The bus routing switch is selectively configurable for interconnecting predetermined ones of the plurality of ports. The bus routing switch includes a variable delay latch structure to simulate the effect of long wires. Each bus routing switch includes a plurality of multiplexers. Each of the plurality of multiplexers includes inputs connected to the plurality of ports, an output connected to a respective one of the plurality of ports and has a control input for configuring the bus routing switch.

Abstract: A method and apparatus for determining capacitance of wires in an integrated circuit is described. The capacitance information derived according to the invention can be used, for example, to calibrate a parasitic extraction engine or to calibrate an integrated circuit fabrication process. The capacitance information can also be used for timing and noise circuit simulations, particularly for deep sub-micron circuit design simulations. Briefly, a measurement of both total capacitance of a line and cross coupling capacitance between two lines is determined by applying predetermined voltage signals to specific circuit elements. The resulting current allows simple computation of total capacitance and cross coupling capacitance. Multiple cross coupling capacitance can be measured with a single device, thus improving the art of library generation, and the overall method is free of uncertainties related to transistor capacitance couplings.

Abstract: A sizing processing system according to the present invention generates an offset figure based on an offset point set obtained by offsetting the respective sides of a source figure by a distance equal to a prescribed sizing amount. When an inside-out side is detected on the offset figure, two sides of the source figure that intersect at a vertex thereof associated with the detected inside-out side are translated by a distance equal to the prescribed sizing amount, and the respective end points of the thus translated sides corresponding to that vertex are taken as offset points. Then, the offset points are added to the offset point set to generate an offset figure that does not entail the generation of an inside-out side. This can also address the problem of an inside-out side that occurs when an edge cut is inserted in the offset figure.

Abstract: Systems, methods and computer program products create an equivalent circuit of electric and/or electronic circuit components, by identifying groups of components and hierarchically modeling aggregate interactions among the groups of components, to create increasingly higher level circuit models, until the equivalent circuit for the components is produced. Hierarchical modeling is provided by defining global components that reflect aggregate parameters of the groups of components and modeling the aggregate interaction among the groups of components as interactions among the global components. Moreover, next higher level global components also are defined that reflect aggregate parameters of at least some of the global components, and the aggregate interaction among the groups of components is modeled as interactions among the next higher level global components.

Abstract: A threshold voltage model with an impurity concentration profile in a channel direction taken into account is provided in the pocket implant MOSFET. With penetration length of the implanted pocket in the channel direction and the maximum impurity concentration of the implant pocket used as physical parameters, the threshold voltage model is obtained by linearly approximating the profile in the channel direction. By analytically solving the model by using a new threshold condition with inhomogeneous profile taken into account, the threshold voltage can be accurately obtained. Based on thus obtained model, the threshold voltage can be predicted and can be used for circuit design.

Abstract: A system for automatic control of a process, comprising a process model using data and further comprising a data model for generating data for said process model and an empirical data extractor for extracting data from said process for said model, and wherein said data used by said process model is interchangeable between data obtained by said data model and data obtained by said extractor. The data model may be a partly statistical partly empirical orthogonal process model. The system is useful in allowing control systems using empirical prediction methods to perform automatic control before having built up a full results database.

Abstract: A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner on random logic macros that adjusts transistor sizes in a continuous domain. To accommodate this tuning, logic gates are mapped to parameterized cells for the tuning and then back to fixed gates after the tuning. Tuning is constrained in such a way as to minimize “binning errors” when the design is mapped back to fixed cells. Further, the critical sections of the circuit are marked in order to make the optimization more effective and to fit within the problem-size constraints of the tuner. A specially formulated objective function is employed during the tuning to promote faster global timing convergence, despite possibly incorrect initial timing budgets. The specially formulated objective function targets all paths that are failing timing, with appropriate weighting, rather than just targeting the most critical path.

Abstract: A computer aided design (CAD) system. A template generation engine generates templates from interconnect configuration files. A field solver generates high frequency passive element relationships from the templates. A circuit builder generates circuit description files from device technology models and from high frequency passive element relationships. Parameterized circuit description models may be generated for large range of sensitivity analyses. A simulator simulates circuit responses for transmission line models from the circuit description files. Interconnect configuration files may be generated by a geometry and material definition module that receives process description data from a designer.

Abstract: A method, system, and data structure for overriding a signal during model simulation. An override signal port is instantiated within a model for delivering an override signal from an instrumentation entity to a signal selection means, wherein the signal selection means selects between the signal and the override signal. A signal override is declared during model simulation, and in response to the declared signal override, the override signal is selected utilizing the signal selection means.

Abstract: Method and apparatus for timing modeling is described. More particularly, sub-processes for obtaining timing information are described. Each of these sub-process is limited to a portion of a gasket module for coupling an embedded device to a host device, and each of these sub-process may be limited to a lithographic process dimension or adjusted accordingly. By dividing timing information gathering into sub-process, output from each of the sub-process may be combined with timing information provided with an embedded core to determine path delays.

Abstract: A system for testing an embedded system containing a target processor executing a target program and target hardware that has a physical portion and a simulated portion. A target monitor determines when the target processor is attempting to access simulated hardware. The address bus of the microprocessor is monitored to detect an address in the address space of the simulated hardware. Lack of an acknowledge signal from the physical hardware within a predetermined period after the target processor attempts to access the target hardware may also indicate simulation. A bus capture circuit captures output signals on the bus connections of the target processor and converts the output signals to output data. The output data is then coupled through a communications interface to a hardware simulator. The hardware simulator processes the data in the same manner that the physical hardware would respond to signals corresponding to the output data.

Abstract: A matrix reordering method performs reordering of elements of a coefficient matrix created based on coefficients of linear simultaneous equations whose solutions are to be produced by parallel processing of processors of a computer in accordance with Gaussian elimination. Herein, degrees corresponding to numbers of non-zero elements are calculated with respect to all pivots included in the coefficient matrix. Then, a first pivot whose degree is under a threshold (mindeg+?) is selected from among the pivots of the coefficient matrix, while a second pivot whose critical path length is minimum is also selected from among the pivots of the coefficient matrix. Replacement of elements is performed between the first pivot and second pivot to complete reordering with respect to the first pivot. In addition, non-zero elements, which are newly produced by the Gaussian elimination of the first pivot, are added to the coefficient matrix.

Abstract: One embodiment of the present invention provides a system that uses a block-partitioned technique to efficiently solve a system of linear equations. The system first receives a matrix that specifies the system of linear equations to be used in performing a time-based simulation. This matrix includes a static portion containing entries that remain fixed over multiple time steps in the time-based simulation, as well as a dynamic portion containing entries that change between time steps in the time-based simulation. Next, the system performs the time-based simulation, wherein performing the time-based simulation involves solving the system of linear equations for each time step in the time-based simulation. In solving the system of linear equations, the system factorizes the static portion of the matrix only once, and reuses the factorization of the static portion in performing an overall factorization of the matrix for each time step of the time-based simulation.

Abstract: Methods are disclosed for quantitatively characterizing the accuracy of a simulated electrical circuit model. In particular, available circuit simulation programs make use of “black box” models of transmission lines used to carry high-speed electrical signals. Electrical transmission lines are characterized by resistance, inductance, capacitance, and dielectric conductance, all values of which may vary with frequency. The “black box” model must accurately model the transmission line over a wide range of frequencies in a time-domain simulation. Algorithms used in the “black box” model may not accurately model the transmission line over the frequency range. Such inaccuracies must be quantified, and if excessive, must be corrected.

Abstract: A method for providing interactive and iterative testing of integrated circuits including the receiving of a first failing region. The first failing region corresponds to one or more circuits on the integrated circuit. The method generates a set of adaptive algorithmic test patterns for the one or more circuits in response to the first failing region and to a logic model of the integrated circuit. Expected results for the test patterns are determined. The method includes applying the test patterns to the first failing region on the integrated circuit resulting in actual results for the test patterns. The expected results to the actual results are compared. The method also transmits mismatches between the expected results and the actual results to a fault simulator.

Abstract: Method and system for modeling and automatically generating an embedded system from a system-level environment. A plurality of user-selectable system-level design objects are provided in the system-level environment. Each system-level design object is defined by a system-level function and is selectable by a system-level designer. A plurality of hardware-level design objects are also provided. Each hardware-level design object is configured to generate a hardware definition of a hardware-level function. Each system-level design object maps to one or more hardware-level design objects. A processor design object is provided which defines a processor. In response to selections made by the designer, a system-level design is instantiated in a system-level design file. The system-level design includes user-selected ones of the system-level and processor design objects.

Abstract: A method for functional verification of a design for a parallel processing device includes receiving a sequence of single instructions from a dynamic test program generator, and assembling a plurality of the instructions from the sequence into an instruction word, in accordance with predetermined rules applicable to the parallel processing device. The instruction word is input to a simulator of the parallel processing device so as to determine a response of the device to the instruction word.

Abstract: A method, system and program product to measure performance of a device dedicated to a phase locked loop (PLL). A resistor-inductor-capacitor (RLC) model is produced to simulate the PLL. The RLC model and the device to be measured are mapped together into a test circuit and the characteristics of the test circuit is analyzed to determine whether the device, if attached to the PLL represented by the RLC model, can meet the required standard of performance. This invention can be used to measure the performance of all kinds of devices attached to all kinds of PLLs.

Abstract: A method and system select delay values from a VHDL standard delay file that correspond to an instance of a logic gate in a logic model. Then the system collects all the delay values of the selected instance and builds super generics for the rise-time and the fall-time of the selected instance. Then, the system repeats this process for every delay value in the standard delay file (310) that correspond to every instance of every logic gate in the logic model. The system then outputs a reduced size standard delay file (314) containing the super generics for every instance of every logic gate in the logic model.

Abstract: A method of post-implementation simulation of a hardware description language (HDL) net list file, that does not match a HDL design file from which it was synthesized, comprises the steps of: creating a remap file which translates ports between the HDL net list file and the HDL design file; and simulating the HDL net list file utilizing the remap file and a (HDL) test bench file created for pre-implementation simulation of the HDL design file. The method may be executed in an integrated software environment or a batch software environment.

Abstract: An improved method for debugging of analog and mixed signal behavioral models during simulation using Newton-Raphson iteration replay. The method according to the invention has substantially modified the prior art solution by limiting the interactive debugging steps in a replay of the last iteration of the accepted timepoints. Using this method, the user only interacts with the simulation during the iteration replay, and only for the accepted solution points. If the user is single stepping through this simulation, the simulator enters interactive mode at each statement during the replay. Similarly, if not single stepping, but a breakpoint has been triggered, the simulator enters the interactive mode at the appropriate statement to honor the breakpoint. While the iteration replay is performed, the system of equations does not need to be solved again. Instead, the solution vector is reinstated from the known solution of the last iteration.

Abstract: The present invention relates to a non-linear characteristic reproducing apparatus wherein a non-linear transformation processing is applied to a state quantity to be outputted. A non-linear behavior of products and parts is reproduced through modeling. [Solving means] there are provided a non-linear characteristic reproducing unit for receiving an estimated observation quantity at the subsequent sampling time of an input state quantity and determining a normalized estimated value in which an estimated value is normalized by an estimated observation quantity at the subsequent sampling time, and a state quantity transformation unit for transforming the input state quantity at the subsequent sampling time to the output state quantity at the subsequent sampling time in accordance with a non-linear operation based on the a normalized estimated value determined in the non-linear characteristic reproducing unit.

Abstract: A method of generating simulation reports regarding an integrated circuit layout is provided. The method can include providing a plurality of control points associated with the integrated circuit layout. A single simulation of the plurality of control points can be performed. Detailed information from the single simulation can be stored in a database. Desired information can then be extracted from the database to generate the simulation reports.

Abstract: An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. The elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.

Abstract: A debugger produces a display based on instructions executed by a circuit simulator or verification tool and on waveform data produced by the simulator or verification tool when executing the instructions. The instructions include a set of statements, each corresponding to a separate circuit signal generated by a circuit and each including a function defining a value of the circuit signal as a function of values of other circuit signals. The simulator evaluates the statements at various simulation times to compute signal values at those simulation times. The waveform data indicates signal values the simulator computes when evaluating the statements. The debugger display includes a set of statement event symbols, each corresponding to a separate evaluation of a statement and each positioned in the display to indicate a simulation time at which the simulator evaluated the statement.

Abstract: A cipher for enciphering and deciphering a signal includes a plurality of sequentially coupled cipher units, each cipher unit being operable to carry out a reversible operation on the signal. The couplings between cipher units can be randomly configured using a cipher code. The cipher code can be secretly shared between the encipher and decipher. A signal which is enciphered using this technique is thus deciphered using a randomly selected cipher circuit as described by the cipher code.

Abstract: The present invention is related to a method for estimating power consumption and noise levels of an integrated circuit which is composed of logic gates connected in the form of a plurality of stages.

Abstract: A method for evaluating a logic state of a design node involves compiling a logic design to generate an annotated symbol table and a levelized design, obtaining a logic evaluation cost from the levelized design, locating a strategic node using the logic evaluation cost, marking the strategic node, and computing the logic state of the design node using the annotated symbol table, the strategic node, and the levelized design.

Abstract: Circuit synthesis is performed utilizing an optimizer that selects design parameters for a synthesis model of a circuit based on desired performance characteristics and performance characteristics/design parameters of previously synthesized circuits. Performance characteristics and design parameters of each synthesized circuit are maintain in conjunction with the synthesis model of the circuit being synthesized. A synthesis plan identifies the synthesis model and specific instructions on how to perform optimized selection of design parameters, how to set up test benches, and how to perform the simulation.

Abstract: A method for generating a test vector for functional verification of circuits includes providing a representation of a circuit, where the representation includes a control logic component and a datapath logic component. The method also includes reading one or more vector generation targets, and performing word-level ATPG justification on the control logic component to obtain a control logic solution. The method further includes extracting one or more arithmetic functions for the datapath logic component based on the control logic solution, and solving the one or more arithmetic functions using a modular constraint solver. The modular constraint solver is based on a modular number system.

Abstract: A method for designing an integrated circuit where the integrated circuit includes a plurality of modules and where each module includes an initiator port and a target port coupled to a distributed routing network. The initiator port is implemented by configuring whether the initiator or the distributed routing network is responsible for ordering responses to requests issued by the initiator port and defining the maximum number of requests that are permitted to be outstanding at the same time. The initiator port is further configured to define whether a delay stage is required in said initiator port. The distributed routing network is defined by the number of routing resources between the initiator and the target, an arbitration method for arbitrating between requests and an association between the routing resources and the targets.